1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved. 4 */ 5 6#include <linux/io.h> 7#include <linux/clk-provider.h> 8#include <linux/of.h> 9#include <linux/of_address.h> 10#include <linux/delay.h> 11#include <linux/export.h> 12#include <linux/clk/tegra.h> 13#include <dt-bindings/clock/tegra114-car.h> 14 15#include "clk.h" 16#include "clk-id.h" 17 18#define RST_DFLL_DVCO 0x2F4 19#define CPU_FINETRIM_SELECT 0x4d4 /* override default prop dlys */ 20#define CPU_FINETRIM_DR 0x4d8 /* rise->rise prop dly A */ 21#define CPU_FINETRIM_R 0x4e4 /* rise->rise prop dly inc A */ 22 23/* RST_DFLL_DVCO bitfields */ 24#define DVFS_DFLL_RESET_SHIFT 0 25 26/* CPU_FINETRIM_SELECT and CPU_FINETRIM_DR bitfields */ 27#define CPU_FINETRIM_1_FCPU_1 BIT(0) /* fcpu0 */ 28#define CPU_FINETRIM_1_FCPU_2 BIT(1) /* fcpu1 */ 29#define CPU_FINETRIM_1_FCPU_3 BIT(2) /* fcpu2 */ 30#define CPU_FINETRIM_1_FCPU_4 BIT(3) /* fcpu3 */ 31#define CPU_FINETRIM_1_FCPU_5 BIT(4) /* fl2 */ 32#define CPU_FINETRIM_1_FCPU_6 BIT(5) /* ftop */ 33 34/* CPU_FINETRIM_R bitfields */ 35#define CPU_FINETRIM_R_FCPU_1_SHIFT 0 /* fcpu0 */ 36#define CPU_FINETRIM_R_FCPU_1_MASK (0x3 << CPU_FINETRIM_R_FCPU_1_SHIFT) 37#define CPU_FINETRIM_R_FCPU_2_SHIFT 2 /* fcpu1 */ 38#define CPU_FINETRIM_R_FCPU_2_MASK (0x3 << CPU_FINETRIM_R_FCPU_2_SHIFT) 39#define CPU_FINETRIM_R_FCPU_3_SHIFT 4 /* fcpu2 */ 40#define CPU_FINETRIM_R_FCPU_3_MASK (0x3 << CPU_FINETRIM_R_FCPU_3_SHIFT) 41#define CPU_FINETRIM_R_FCPU_4_SHIFT 6 /* fcpu3 */ 42#define CPU_FINETRIM_R_FCPU_4_MASK (0x3 << CPU_FINETRIM_R_FCPU_4_SHIFT) 43#define CPU_FINETRIM_R_FCPU_5_SHIFT 8 /* fl2 */ 44#define CPU_FINETRIM_R_FCPU_5_MASK (0x3 << CPU_FINETRIM_R_FCPU_5_SHIFT) 45#define CPU_FINETRIM_R_FCPU_6_SHIFT 10 /* ftop */ 46#define CPU_FINETRIM_R_FCPU_6_MASK (0x3 << CPU_FINETRIM_R_FCPU_6_SHIFT) 47 48#define TEGRA114_CLK_PERIPH_BANKS 5 49 50#define PLLC_BASE 0x80 51#define PLLC_MISC2 0x88 52#define PLLC_MISC 0x8c 53#define PLLC2_BASE 0x4e8 54#define PLLC2_MISC 0x4ec 55#define PLLC3_BASE 0x4fc 56#define PLLC3_MISC 0x500 57#define PLLM_BASE 0x90 58#define PLLM_MISC 0x9c 59#define PLLP_BASE 0xa0 60#define PLLP_MISC 0xac 61#define PLLX_BASE 0xe0 62#define PLLX_MISC 0xe4 63#define PLLX_MISC2 0x514 64#define PLLX_MISC3 0x518 65#define PLLD_BASE 0xd0 66#define PLLD_MISC 0xdc 67#define PLLD2_BASE 0x4b8 68#define PLLD2_MISC 0x4bc 69#define PLLE_BASE 0xe8 70#define PLLE_MISC 0xec 71#define PLLA_BASE 0xb0 72#define PLLA_MISC 0xbc 73#define PLLU_BASE 0xc0 74#define PLLU_MISC 0xcc 75#define PLLRE_BASE 0x4c4 76#define PLLRE_MISC 0x4c8 77 78#define PLL_MISC_LOCK_ENABLE 18 79#define PLLC_MISC_LOCK_ENABLE 24 80#define PLLDU_MISC_LOCK_ENABLE 22 81#define PLLE_MISC_LOCK_ENABLE 9 82#define PLLRE_MISC_LOCK_ENABLE 30 83 84#define PLLC_IDDQ_BIT 26 85#define PLLX_IDDQ_BIT 3 86#define PLLRE_IDDQ_BIT 16 87 88#define PLL_BASE_LOCK BIT(27) 89#define PLLE_MISC_LOCK BIT(11) 90#define PLLRE_MISC_LOCK BIT(24) 91#define PLLCX_BASE_LOCK (BIT(26)|BIT(27)) 92 93#define PLLE_AUX 0x48c 94#define PLLC_OUT 0x84 95#define PLLM_OUT 0x94 96 97#define OSC_CTRL 0x50 98#define OSC_CTRL_OSC_FREQ_SHIFT 28 99#define OSC_CTRL_PLL_REF_DIV_SHIFT 26 100 101#define PLLXC_SW_MAX_P 6 102 103#define CCLKG_BURST_POLICY 0x368 104 105#define CLK_SOURCE_CSITE 0x1d4 106#define CLK_SOURCE_EMC 0x19c 107 108/* PLLM override registers */ 109#define PMC_PLLM_WB0_OVERRIDE 0x1dc 110#define PMC_PLLM_WB0_OVERRIDE_2 0x2b0 111 112/* Tegra CPU clock and reset control regs */ 113#define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470 114 115#define MUX8(_name, _parents, _offset, \ 116 _clk_num, _gate_flags, _clk_id) \ 117 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\ 118 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\ 119 _clk_num, _gate_flags, _clk_id, _parents##_idx, 0,\ 120 NULL) 121 122#ifdef CONFIG_PM_SLEEP 123static struct cpu_clk_suspend_context { 124 u32 clk_csite_src; 125 u32 cclkg_burst; 126 u32 cclkg_divider; 127} tegra114_cpu_clk_sctx; 128#endif 129 130static void __iomem *clk_base; 131static void __iomem *pmc_base; 132 133static DEFINE_SPINLOCK(pll_d_lock); 134static DEFINE_SPINLOCK(pll_d2_lock); 135static DEFINE_SPINLOCK(pll_u_lock); 136static DEFINE_SPINLOCK(pll_re_lock); 137static DEFINE_SPINLOCK(emc_lock); 138 139static struct div_nmp pllxc_nmp = { 140 .divm_shift = 0, 141 .divm_width = 8, 142 .divn_shift = 8, 143 .divn_width = 8, 144 .divp_shift = 20, 145 .divp_width = 4, 146}; 147 148static const struct pdiv_map pllxc_p[] = { 149 { .pdiv = 1, .hw_val = 0 }, 150 { .pdiv = 2, .hw_val = 1 }, 151 { .pdiv = 3, .hw_val = 2 }, 152 { .pdiv = 4, .hw_val = 3 }, 153 { .pdiv = 5, .hw_val = 4 }, 154 { .pdiv = 6, .hw_val = 5 }, 155 { .pdiv = 8, .hw_val = 6 }, 156 { .pdiv = 10, .hw_val = 7 }, 157 { .pdiv = 12, .hw_val = 8 }, 158 { .pdiv = 16, .hw_val = 9 }, 159 { .pdiv = 12, .hw_val = 10 }, 160 { .pdiv = 16, .hw_val = 11 }, 161 { .pdiv = 20, .hw_val = 12 }, 162 { .pdiv = 24, .hw_val = 13 }, 163 { .pdiv = 32, .hw_val = 14 }, 164 { .pdiv = 0, .hw_val = 0 }, 165}; 166 167static struct tegra_clk_pll_freq_table pll_c_freq_table[] = { 168 { 12000000, 624000000, 104, 1, 2, 0 }, 169 { 12000000, 600000000, 100, 1, 2, 0 }, 170 { 13000000, 600000000, 92, 1, 2, 0 }, /* actual: 598.0 MHz */ 171 { 16800000, 600000000, 71, 1, 2, 0 }, /* actual: 596.4 MHz */ 172 { 19200000, 600000000, 62, 1, 2, 0 }, /* actual: 595.2 MHz */ 173 { 26000000, 600000000, 92, 2, 2, 0 }, /* actual: 598.0 MHz */ 174 { 0, 0, 0, 0, 0, 0 }, 175}; 176 177static struct tegra_clk_pll_params pll_c_params = { 178 .input_min = 12000000, 179 .input_max = 800000000, 180 .cf_min = 12000000, 181 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */ 182 .vco_min = 600000000, 183 .vco_max = 1400000000, 184 .base_reg = PLLC_BASE, 185 .misc_reg = PLLC_MISC, 186 .lock_mask = PLL_BASE_LOCK, 187 .lock_enable_bit_idx = PLLC_MISC_LOCK_ENABLE, 188 .lock_delay = 300, 189 .iddq_reg = PLLC_MISC, 190 .iddq_bit_idx = PLLC_IDDQ_BIT, 191 .max_p = PLLXC_SW_MAX_P, 192 .dyn_ramp_reg = PLLC_MISC2, 193 .stepa_shift = 17, 194 .stepb_shift = 9, 195 .pdiv_tohw = pllxc_p, 196 .div_nmp = &pllxc_nmp, 197 .freq_table = pll_c_freq_table, 198 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE, 199}; 200 201static struct div_nmp pllcx_nmp = { 202 .divm_shift = 0, 203 .divm_width = 2, 204 .divn_shift = 8, 205 .divn_width = 8, 206 .divp_shift = 20, 207 .divp_width = 3, 208}; 209 210static const struct pdiv_map pllc_p[] = { 211 { .pdiv = 1, .hw_val = 0 }, 212 { .pdiv = 2, .hw_val = 1 }, 213 { .pdiv = 4, .hw_val = 3 }, 214 { .pdiv = 8, .hw_val = 5 }, 215 { .pdiv = 16, .hw_val = 7 }, 216 { .pdiv = 0, .hw_val = 0 }, 217}; 218 219static struct tegra_clk_pll_freq_table pll_cx_freq_table[] = { 220 { 12000000, 600000000, 100, 1, 2, 0 }, 221 { 13000000, 600000000, 92, 1, 2, 0 }, /* actual: 598.0 MHz */ 222 { 16800000, 600000000, 71, 1, 2, 0 }, /* actual: 596.4 MHz */ 223 { 19200000, 600000000, 62, 1, 2, 0 }, /* actual: 595.2 MHz */ 224 { 26000000, 600000000, 92, 2, 2, 0 }, /* actual: 598.0 MHz */ 225 { 0, 0, 0, 0, 0, 0 }, 226}; 227 228static struct tegra_clk_pll_params pll_c2_params = { 229 .input_min = 12000000, 230 .input_max = 48000000, 231 .cf_min = 12000000, 232 .cf_max = 19200000, 233 .vco_min = 600000000, 234 .vco_max = 1200000000, 235 .base_reg = PLLC2_BASE, 236 .misc_reg = PLLC2_MISC, 237 .lock_mask = PLL_BASE_LOCK, 238 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 239 .lock_delay = 300, 240 .pdiv_tohw = pllc_p, 241 .div_nmp = &pllcx_nmp, 242 .max_p = 7, 243 .ext_misc_reg[0] = 0x4f0, 244 .ext_misc_reg[1] = 0x4f4, 245 .ext_misc_reg[2] = 0x4f8, 246 .freq_table = pll_cx_freq_table, 247 .flags = TEGRA_PLL_USE_LOCK, 248}; 249 250static struct tegra_clk_pll_params pll_c3_params = { 251 .input_min = 12000000, 252 .input_max = 48000000, 253 .cf_min = 12000000, 254 .cf_max = 19200000, 255 .vco_min = 600000000, 256 .vco_max = 1200000000, 257 .base_reg = PLLC3_BASE, 258 .misc_reg = PLLC3_MISC, 259 .lock_mask = PLL_BASE_LOCK, 260 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 261 .lock_delay = 300, 262 .pdiv_tohw = pllc_p, 263 .div_nmp = &pllcx_nmp, 264 .max_p = 7, 265 .ext_misc_reg[0] = 0x504, 266 .ext_misc_reg[1] = 0x508, 267 .ext_misc_reg[2] = 0x50c, 268 .freq_table = pll_cx_freq_table, 269 .flags = TEGRA_PLL_USE_LOCK, 270}; 271 272static struct div_nmp pllm_nmp = { 273 .divm_shift = 0, 274 .divm_width = 8, 275 .override_divm_shift = 0, 276 .divn_shift = 8, 277 .divn_width = 8, 278 .override_divn_shift = 8, 279 .divp_shift = 20, 280 .divp_width = 1, 281 .override_divp_shift = 27, 282}; 283 284static const struct pdiv_map pllm_p[] = { 285 { .pdiv = 1, .hw_val = 0 }, 286 { .pdiv = 2, .hw_val = 1 }, 287 { .pdiv = 0, .hw_val = 0 }, 288}; 289 290static struct tegra_clk_pll_freq_table pll_m_freq_table[] = { 291 { 12000000, 800000000, 66, 1, 1, 0 }, /* actual: 792.0 MHz */ 292 { 13000000, 800000000, 61, 1, 1, 0 }, /* actual: 793.0 MHz */ 293 { 16800000, 800000000, 47, 1, 1, 0 }, /* actual: 789.6 MHz */ 294 { 19200000, 800000000, 41, 1, 1, 0 }, /* actual: 787.2 MHz */ 295 { 26000000, 800000000, 61, 2, 1, 0 }, /* actual: 793.0 MHz */ 296 { 0, 0, 0, 0, 0, 0 }, 297}; 298 299static struct tegra_clk_pll_params pll_m_params = { 300 .input_min = 12000000, 301 .input_max = 500000000, 302 .cf_min = 12000000, 303 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */ 304 .vco_min = 400000000, 305 .vco_max = 1066000000, 306 .base_reg = PLLM_BASE, 307 .misc_reg = PLLM_MISC, 308 .lock_mask = PLL_BASE_LOCK, 309 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 310 .lock_delay = 300, 311 .max_p = 2, 312 .pdiv_tohw = pllm_p, 313 .div_nmp = &pllm_nmp, 314 .pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE, 315 .pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE_2, 316 .freq_table = pll_m_freq_table, 317 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE | 318 TEGRA_PLL_FIXED, 319}; 320 321static struct div_nmp pllp_nmp = { 322 .divm_shift = 0, 323 .divm_width = 5, 324 .divn_shift = 8, 325 .divn_width = 10, 326 .divp_shift = 20, 327 .divp_width = 3, 328}; 329 330static struct tegra_clk_pll_freq_table pll_p_freq_table[] = { 331 { 12000000, 216000000, 432, 12, 2, 8 }, 332 { 13000000, 216000000, 432, 13, 2, 8 }, 333 { 16800000, 216000000, 360, 14, 2, 8 }, 334 { 19200000, 216000000, 360, 16, 2, 8 }, 335 { 26000000, 216000000, 432, 26, 2, 8 }, 336 { 0, 0, 0, 0, 0, 0 }, 337}; 338 339static struct tegra_clk_pll_params pll_p_params = { 340 .input_min = 2000000, 341 .input_max = 31000000, 342 .cf_min = 1000000, 343 .cf_max = 6000000, 344 .vco_min = 200000000, 345 .vco_max = 700000000, 346 .base_reg = PLLP_BASE, 347 .misc_reg = PLLP_MISC, 348 .lock_mask = PLL_BASE_LOCK, 349 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 350 .lock_delay = 300, 351 .div_nmp = &pllp_nmp, 352 .freq_table = pll_p_freq_table, 353 .flags = TEGRA_PLL_FIXED | TEGRA_PLL_USE_LOCK | 354 TEGRA_PLL_HAS_LOCK_ENABLE, 355 .fixed_rate = 408000000, 356}; 357 358static struct tegra_clk_pll_freq_table pll_a_freq_table[] = { 359 { 9600000, 282240000, 147, 5, 1, 4 }, 360 { 9600000, 368640000, 192, 5, 1, 4 }, 361 { 9600000, 240000000, 200, 8, 1, 8 }, 362 { 28800000, 282240000, 245, 25, 1, 8 }, 363 { 28800000, 368640000, 320, 25, 1, 8 }, 364 { 28800000, 240000000, 200, 24, 1, 8 }, 365 { 0, 0, 0, 0, 0, 0 }, 366}; 367 368 369static struct tegra_clk_pll_params pll_a_params = { 370 .input_min = 2000000, 371 .input_max = 31000000, 372 .cf_min = 1000000, 373 .cf_max = 6000000, 374 .vco_min = 200000000, 375 .vco_max = 700000000, 376 .base_reg = PLLA_BASE, 377 .misc_reg = PLLA_MISC, 378 .lock_mask = PLL_BASE_LOCK, 379 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 380 .lock_delay = 300, 381 .div_nmp = &pllp_nmp, 382 .freq_table = pll_a_freq_table, 383 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK | 384 TEGRA_PLL_HAS_LOCK_ENABLE, 385}; 386 387static struct tegra_clk_pll_freq_table pll_d_freq_table[] = { 388 { 12000000, 216000000, 864, 12, 4, 12 }, 389 { 13000000, 216000000, 864, 13, 4, 12 }, 390 { 16800000, 216000000, 720, 14, 4, 12 }, 391 { 19200000, 216000000, 720, 16, 4, 12 }, 392 { 26000000, 216000000, 864, 26, 4, 12 }, 393 { 12000000, 594000000, 594, 12, 1, 12 }, 394 { 13000000, 594000000, 594, 13, 1, 12 }, 395 { 16800000, 594000000, 495, 14, 1, 12 }, 396 { 19200000, 594000000, 495, 16, 1, 12 }, 397 { 26000000, 594000000, 594, 26, 1, 12 }, 398 { 12000000, 1000000000, 1000, 12, 1, 12 }, 399 { 13000000, 1000000000, 1000, 13, 1, 12 }, 400 { 19200000, 1000000000, 625, 12, 1, 12 }, 401 { 26000000, 1000000000, 1000, 26, 1, 12 }, 402 { 0, 0, 0, 0, 0, 0 }, 403}; 404 405static struct tegra_clk_pll_params pll_d_params = { 406 .input_min = 2000000, 407 .input_max = 40000000, 408 .cf_min = 1000000, 409 .cf_max = 6000000, 410 .vco_min = 500000000, 411 .vco_max = 1000000000, 412 .base_reg = PLLD_BASE, 413 .misc_reg = PLLD_MISC, 414 .lock_mask = PLL_BASE_LOCK, 415 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 416 .lock_delay = 1000, 417 .div_nmp = &pllp_nmp, 418 .freq_table = pll_d_freq_table, 419 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON | 420 TEGRA_PLL_HAS_LOCK_ENABLE, 421}; 422 423static struct tegra_clk_pll_params pll_d2_params = { 424 .input_min = 2000000, 425 .input_max = 40000000, 426 .cf_min = 1000000, 427 .cf_max = 6000000, 428 .vco_min = 500000000, 429 .vco_max = 1000000000, 430 .base_reg = PLLD2_BASE, 431 .misc_reg = PLLD2_MISC, 432 .lock_mask = PLL_BASE_LOCK, 433 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 434 .lock_delay = 1000, 435 .div_nmp = &pllp_nmp, 436 .freq_table = pll_d_freq_table, 437 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON | 438 TEGRA_PLL_HAS_LOCK_ENABLE, 439}; 440 441static const struct pdiv_map pllu_p[] = { 442 { .pdiv = 1, .hw_val = 1 }, 443 { .pdiv = 2, .hw_val = 0 }, 444 { .pdiv = 0, .hw_val = 0 }, 445}; 446 447static struct div_nmp pllu_nmp = { 448 .divm_shift = 0, 449 .divm_width = 5, 450 .divn_shift = 8, 451 .divn_width = 10, 452 .divp_shift = 20, 453 .divp_width = 1, 454}; 455 456static struct tegra_clk_pll_freq_table pll_u_freq_table[] = { 457 { 12000000, 480000000, 960, 12, 2, 12 }, 458 { 13000000, 480000000, 960, 13, 2, 12 }, 459 { 16800000, 480000000, 400, 7, 2, 5 }, 460 { 19200000, 480000000, 200, 4, 2, 3 }, 461 { 26000000, 480000000, 960, 26, 2, 12 }, 462 { 0, 0, 0, 0, 0, 0 }, 463}; 464 465static struct tegra_clk_pll_params pll_u_params = { 466 .input_min = 2000000, 467 .input_max = 40000000, 468 .cf_min = 1000000, 469 .cf_max = 6000000, 470 .vco_min = 480000000, 471 .vco_max = 960000000, 472 .base_reg = PLLU_BASE, 473 .misc_reg = PLLU_MISC, 474 .lock_mask = PLL_BASE_LOCK, 475 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 476 .lock_delay = 1000, 477 .pdiv_tohw = pllu_p, 478 .div_nmp = &pllu_nmp, 479 .freq_table = pll_u_freq_table, 480 .flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON | 481 TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE, 482}; 483 484static struct tegra_clk_pll_freq_table pll_x_freq_table[] = { 485 /* 1 GHz */ 486 { 12000000, 1000000000, 83, 1, 1, 0 }, /* actual: 996.0 MHz */ 487 { 13000000, 1000000000, 76, 1, 1, 0 }, /* actual: 988.0 MHz */ 488 { 16800000, 1000000000, 59, 1, 1, 0 }, /* actual: 991.2 MHz */ 489 { 19200000, 1000000000, 52, 1, 1, 0 }, /* actual: 998.4 MHz */ 490 { 26000000, 1000000000, 76, 2, 1, 0 }, /* actual: 988.0 MHz */ 491 { 0, 0, 0, 0, 0, 0 }, 492}; 493 494static struct tegra_clk_pll_params pll_x_params = { 495 .input_min = 12000000, 496 .input_max = 800000000, 497 .cf_min = 12000000, 498 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */ 499 .vco_min = 700000000, 500 .vco_max = 2400000000U, 501 .base_reg = PLLX_BASE, 502 .misc_reg = PLLX_MISC, 503 .lock_mask = PLL_BASE_LOCK, 504 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 505 .lock_delay = 300, 506 .iddq_reg = PLLX_MISC3, 507 .iddq_bit_idx = PLLX_IDDQ_BIT, 508 .max_p = PLLXC_SW_MAX_P, 509 .dyn_ramp_reg = PLLX_MISC2, 510 .stepa_shift = 16, 511 .stepb_shift = 24, 512 .pdiv_tohw = pllxc_p, 513 .div_nmp = &pllxc_nmp, 514 .freq_table = pll_x_freq_table, 515 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE, 516}; 517 518static struct tegra_clk_pll_freq_table pll_e_freq_table[] = { 519 /* PLLE special case: use cpcon field to store cml divider value */ 520 { 336000000, 100000000, 100, 21, 16, 11 }, 521 { 312000000, 100000000, 200, 26, 24, 13 }, 522 { 12000000, 100000000, 200, 1, 24, 13 }, 523 { 0, 0, 0, 0, 0, 0 }, 524}; 525 526static const struct pdiv_map plle_p[] = { 527 { .pdiv = 1, .hw_val = 0 }, 528 { .pdiv = 2, .hw_val = 1 }, 529 { .pdiv = 3, .hw_val = 2 }, 530 { .pdiv = 4, .hw_val = 3 }, 531 { .pdiv = 5, .hw_val = 4 }, 532 { .pdiv = 6, .hw_val = 5 }, 533 { .pdiv = 8, .hw_val = 6 }, 534 { .pdiv = 10, .hw_val = 7 }, 535 { .pdiv = 12, .hw_val = 8 }, 536 { .pdiv = 16, .hw_val = 9 }, 537 { .pdiv = 12, .hw_val = 10 }, 538 { .pdiv = 16, .hw_val = 11 }, 539 { .pdiv = 20, .hw_val = 12 }, 540 { .pdiv = 24, .hw_val = 13 }, 541 { .pdiv = 32, .hw_val = 14 }, 542 { .pdiv = 0, .hw_val = 0 } 543}; 544 545static struct div_nmp plle_nmp = { 546 .divm_shift = 0, 547 .divm_width = 8, 548 .divn_shift = 8, 549 .divn_width = 8, 550 .divp_shift = 24, 551 .divp_width = 4, 552}; 553 554static struct tegra_clk_pll_params pll_e_params = { 555 .input_min = 12000000, 556 .input_max = 1000000000, 557 .cf_min = 12000000, 558 .cf_max = 75000000, 559 .vco_min = 1600000000, 560 .vco_max = 2400000000U, 561 .base_reg = PLLE_BASE, 562 .misc_reg = PLLE_MISC, 563 .aux_reg = PLLE_AUX, 564 .lock_mask = PLLE_MISC_LOCK, 565 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE, 566 .lock_delay = 300, 567 .pdiv_tohw = plle_p, 568 .div_nmp = &plle_nmp, 569 .freq_table = pll_e_freq_table, 570 .flags = TEGRA_PLL_FIXED | TEGRA_PLL_HAS_LOCK_ENABLE, 571 .fixed_rate = 100000000, 572}; 573 574static struct div_nmp pllre_nmp = { 575 .divm_shift = 0, 576 .divm_width = 8, 577 .divn_shift = 8, 578 .divn_width = 8, 579 .divp_shift = 16, 580 .divp_width = 4, 581}; 582 583static struct tegra_clk_pll_params pll_re_vco_params = { 584 .input_min = 12000000, 585 .input_max = 1000000000, 586 .cf_min = 12000000, 587 .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */ 588 .vco_min = 300000000, 589 .vco_max = 600000000, 590 .base_reg = PLLRE_BASE, 591 .misc_reg = PLLRE_MISC, 592 .lock_mask = PLLRE_MISC_LOCK, 593 .lock_enable_bit_idx = PLLRE_MISC_LOCK_ENABLE, 594 .lock_delay = 300, 595 .iddq_reg = PLLRE_MISC, 596 .iddq_bit_idx = PLLRE_IDDQ_BIT, 597 .div_nmp = &pllre_nmp, 598 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE | 599 TEGRA_PLL_LOCK_MISC, 600}; 601 602/* possible OSC frequencies in Hz */ 603static unsigned long tegra114_input_freq[] = { 604 [ 0] = 13000000, 605 [ 1] = 16800000, 606 [ 4] = 19200000, 607 [ 5] = 38400000, 608 [ 8] = 12000000, 609 [ 9] = 48000000, 610 [12] = 26000000, 611}; 612 613#define MASK(x) (BIT(x) - 1) 614 615/* peripheral mux definitions */ 616 617static const char *mux_plld_out0_plld2_out0[] = { 618 "pll_d_out0", "pll_d2_out0", 619}; 620#define mux_plld_out0_plld2_out0_idx NULL 621 622static const char *mux_pllmcp_clkm[] = { 623 "pll_m_out0", "pll_c_out0", "pll_p_out0", "clk_m", "pll_m_ud", 624}; 625 626static const struct clk_div_table pll_re_div_table[] = { 627 { .val = 0, .div = 1 }, 628 { .val = 1, .div = 2 }, 629 { .val = 2, .div = 3 }, 630 { .val = 3, .div = 4 }, 631 { .val = 4, .div = 5 }, 632 { .val = 5, .div = 6 }, 633 { .val = 0, .div = 0 }, 634}; 635 636static struct tegra_clk tegra114_clks[tegra_clk_max] __initdata = { 637 [tegra_clk_rtc] = { .dt_id = TEGRA114_CLK_RTC, .present = true }, 638 [tegra_clk_timer] = { .dt_id = TEGRA114_CLK_TIMER, .present = true }, 639 [tegra_clk_uarta] = { .dt_id = TEGRA114_CLK_UARTA, .present = true }, 640 [tegra_clk_uartd] = { .dt_id = TEGRA114_CLK_UARTD, .present = true }, 641 [tegra_clk_sdmmc2_8] = { .dt_id = TEGRA114_CLK_SDMMC2, .present = true }, 642 [tegra_clk_i2s1] = { .dt_id = TEGRA114_CLK_I2S1, .present = true }, 643 [tegra_clk_i2c1] = { .dt_id = TEGRA114_CLK_I2C1, .present = true }, 644 [tegra_clk_ndflash] = { .dt_id = TEGRA114_CLK_NDFLASH, .present = true }, 645 [tegra_clk_sdmmc1_8] = { .dt_id = TEGRA114_CLK_SDMMC1, .present = true }, 646 [tegra_clk_sdmmc4_8] = { .dt_id = TEGRA114_CLK_SDMMC4, .present = true }, 647 [tegra_clk_pwm] = { .dt_id = TEGRA114_CLK_PWM, .present = true }, 648 [tegra_clk_i2s0] = { .dt_id = TEGRA114_CLK_I2S0, .present = true }, 649 [tegra_clk_i2s2] = { .dt_id = TEGRA114_CLK_I2S2, .present = true }, 650 [tegra_clk_epp_8] = { .dt_id = TEGRA114_CLK_EPP, .present = true }, 651 [tegra_clk_gr2d_8] = { .dt_id = TEGRA114_CLK_GR2D, .present = true }, 652 [tegra_clk_usbd] = { .dt_id = TEGRA114_CLK_USBD, .present = true }, 653 [tegra_clk_isp] = { .dt_id = TEGRA114_CLK_ISP, .present = true }, 654 [tegra_clk_gr3d_8] = { .dt_id = TEGRA114_CLK_GR3D, .present = true }, 655 [tegra_clk_disp2] = { .dt_id = TEGRA114_CLK_DISP2, .present = true }, 656 [tegra_clk_disp1] = { .dt_id = TEGRA114_CLK_DISP1, .present = true }, 657 [tegra_clk_host1x_8] = { .dt_id = TEGRA114_CLK_HOST1X, .present = true }, 658 [tegra_clk_vcp] = { .dt_id = TEGRA114_CLK_VCP, .present = true }, 659 [tegra_clk_apbdma] = { .dt_id = TEGRA114_CLK_APBDMA, .present = true }, 660 [tegra_clk_kbc] = { .dt_id = TEGRA114_CLK_KBC, .present = true }, 661 [tegra_clk_kfuse] = { .dt_id = TEGRA114_CLK_KFUSE, .present = true }, 662 [tegra_clk_sbc1_8] = { .dt_id = TEGRA114_CLK_SBC1, .present = true }, 663 [tegra_clk_nor] = { .dt_id = TEGRA114_CLK_NOR, .present = true }, 664 [tegra_clk_sbc2_8] = { .dt_id = TEGRA114_CLK_SBC2, .present = true }, 665 [tegra_clk_sbc3_8] = { .dt_id = TEGRA114_CLK_SBC3, .present = true }, 666 [tegra_clk_i2c5] = { .dt_id = TEGRA114_CLK_I2C5, .present = true }, 667 [tegra_clk_mipi] = { .dt_id = TEGRA114_CLK_MIPI, .present = true }, 668 [tegra_clk_hdmi] = { .dt_id = TEGRA114_CLK_HDMI, .present = true }, 669 [tegra_clk_csi] = { .dt_id = TEGRA114_CLK_CSI, .present = true }, 670 [tegra_clk_i2c2] = { .dt_id = TEGRA114_CLK_I2C2, .present = true }, 671 [tegra_clk_uartc] = { .dt_id = TEGRA114_CLK_UARTC, .present = true }, 672 [tegra_clk_emc] = { .dt_id = TEGRA114_CLK_EMC, .present = true }, 673 [tegra_clk_usb2] = { .dt_id = TEGRA114_CLK_USB2, .present = true }, 674 [tegra_clk_usb3] = { .dt_id = TEGRA114_CLK_USB3, .present = true }, 675 [tegra_clk_vde_8] = { .dt_id = TEGRA114_CLK_VDE, .present = true }, 676 [tegra_clk_bsea] = { .dt_id = TEGRA114_CLK_BSEA, .present = true }, 677 [tegra_clk_bsev] = { .dt_id = TEGRA114_CLK_BSEV, .present = true }, 678 [tegra_clk_i2c3] = { .dt_id = TEGRA114_CLK_I2C3, .present = true }, 679 [tegra_clk_sbc4_8] = { .dt_id = TEGRA114_CLK_SBC4, .present = true }, 680 [tegra_clk_sdmmc3_8] = { .dt_id = TEGRA114_CLK_SDMMC3, .present = true }, 681 [tegra_clk_owr] = { .dt_id = TEGRA114_CLK_OWR, .present = true }, 682 [tegra_clk_csite] = { .dt_id = TEGRA114_CLK_CSITE, .present = true }, 683 [tegra_clk_la] = { .dt_id = TEGRA114_CLK_LA, .present = true }, 684 [tegra_clk_trace] = { .dt_id = TEGRA114_CLK_TRACE, .present = true }, 685 [tegra_clk_soc_therm] = { .dt_id = TEGRA114_CLK_SOC_THERM, .present = true }, 686 [tegra_clk_dtv] = { .dt_id = TEGRA114_CLK_DTV, .present = true }, 687 [tegra_clk_ndspeed] = { .dt_id = TEGRA114_CLK_NDSPEED, .present = true }, 688 [tegra_clk_i2cslow] = { .dt_id = TEGRA114_CLK_I2CSLOW, .present = true }, 689 [tegra_clk_tsec] = { .dt_id = TEGRA114_CLK_TSEC, .present = true }, 690 [tegra_clk_xusb_host] = { .dt_id = TEGRA114_CLK_XUSB_HOST, .present = true }, 691 [tegra_clk_msenc] = { .dt_id = TEGRA114_CLK_MSENC, .present = true }, 692 [tegra_clk_csus] = { .dt_id = TEGRA114_CLK_CSUS, .present = true }, 693 [tegra_clk_mselect] = { .dt_id = TEGRA114_CLK_MSELECT, .present = true }, 694 [tegra_clk_tsensor] = { .dt_id = TEGRA114_CLK_TSENSOR, .present = true }, 695 [tegra_clk_i2s3] = { .dt_id = TEGRA114_CLK_I2S3, .present = true }, 696 [tegra_clk_i2s4] = { .dt_id = TEGRA114_CLK_I2S4, .present = true }, 697 [tegra_clk_i2c4] = { .dt_id = TEGRA114_CLK_I2C4, .present = true }, 698 [tegra_clk_sbc5_8] = { .dt_id = TEGRA114_CLK_SBC5, .present = true }, 699 [tegra_clk_sbc6_8] = { .dt_id = TEGRA114_CLK_SBC6, .present = true }, 700 [tegra_clk_d_audio] = { .dt_id = TEGRA114_CLK_D_AUDIO, .present = true }, 701 [tegra_clk_apbif] = { .dt_id = TEGRA114_CLK_APBIF, .present = true }, 702 [tegra_clk_dam0] = { .dt_id = TEGRA114_CLK_DAM0, .present = true }, 703 [tegra_clk_dam1] = { .dt_id = TEGRA114_CLK_DAM1, .present = true }, 704 [tegra_clk_dam2] = { .dt_id = TEGRA114_CLK_DAM2, .present = true }, 705 [tegra_clk_hda2codec_2x] = { .dt_id = TEGRA114_CLK_HDA2CODEC_2X, .present = true }, 706 [tegra_clk_audio0_2x] = { .dt_id = TEGRA114_CLK_AUDIO0_2X, .present = true }, 707 [tegra_clk_audio1_2x] = { .dt_id = TEGRA114_CLK_AUDIO1_2X, .present = true }, 708 [tegra_clk_audio2_2x] = { .dt_id = TEGRA114_CLK_AUDIO2_2X, .present = true }, 709 [tegra_clk_audio3_2x] = { .dt_id = TEGRA114_CLK_AUDIO3_2X, .present = true }, 710 [tegra_clk_audio4_2x] = { .dt_id = TEGRA114_CLK_AUDIO4_2X, .present = true }, 711 [tegra_clk_spdif_2x] = { .dt_id = TEGRA114_CLK_SPDIF_2X, .present = true }, 712 [tegra_clk_actmon] = { .dt_id = TEGRA114_CLK_ACTMON, .present = true }, 713 [tegra_clk_extern1] = { .dt_id = TEGRA114_CLK_EXTERN1, .present = true }, 714 [tegra_clk_extern2] = { .dt_id = TEGRA114_CLK_EXTERN2, .present = true }, 715 [tegra_clk_extern3] = { .dt_id = TEGRA114_CLK_EXTERN3, .present = true }, 716 [tegra_clk_hda] = { .dt_id = TEGRA114_CLK_HDA, .present = true }, 717 [tegra_clk_se] = { .dt_id = TEGRA114_CLK_SE, .present = true }, 718 [tegra_clk_hda2hdmi] = { .dt_id = TEGRA114_CLK_HDA2HDMI, .present = true }, 719 [tegra_clk_cilab] = { .dt_id = TEGRA114_CLK_CILAB, .present = true }, 720 [tegra_clk_cilcd] = { .dt_id = TEGRA114_CLK_CILCD, .present = true }, 721 [tegra_clk_cile] = { .dt_id = TEGRA114_CLK_CILE, .present = true }, 722 [tegra_clk_dsialp] = { .dt_id = TEGRA114_CLK_DSIALP, .present = true }, 723 [tegra_clk_dsiblp] = { .dt_id = TEGRA114_CLK_DSIBLP, .present = true }, 724 [tegra_clk_dds] = { .dt_id = TEGRA114_CLK_DDS, .present = true }, 725 [tegra_clk_dp2] = { .dt_id = TEGRA114_CLK_DP2, .present = true }, 726 [tegra_clk_amx] = { .dt_id = TEGRA114_CLK_AMX, .present = true }, 727 [tegra_clk_adx] = { .dt_id = TEGRA114_CLK_ADX, .present = true }, 728 [tegra_clk_xusb_ss] = { .dt_id = TEGRA114_CLK_XUSB_SS, .present = true }, 729 [tegra_clk_uartb] = { .dt_id = TEGRA114_CLK_UARTB, .present = true }, 730 [tegra_clk_vfir] = { .dt_id = TEGRA114_CLK_VFIR, .present = true }, 731 [tegra_clk_spdif_in] = { .dt_id = TEGRA114_CLK_SPDIF_IN, .present = true }, 732 [tegra_clk_spdif_out] = { .dt_id = TEGRA114_CLK_SPDIF_OUT, .present = true }, 733 [tegra_clk_vi_8] = { .dt_id = TEGRA114_CLK_VI, .present = true }, 734 [tegra_clk_fuse] = { .dt_id = TEGRA114_CLK_FUSE, .present = true }, 735 [tegra_clk_fuse_burn] = { .dt_id = TEGRA114_CLK_FUSE_BURN, .present = true }, 736 [tegra_clk_clk_32k] = { .dt_id = TEGRA114_CLK_CLK_32K, .present = true }, 737 [tegra_clk_clk_m] = { .dt_id = TEGRA114_CLK_CLK_M, .present = true }, 738 [tegra_clk_osc] = { .dt_id = TEGRA114_CLK_OSC, .present = true }, 739 [tegra_clk_osc_div2] = { .dt_id = TEGRA114_CLK_OSC_DIV2, .present = true }, 740 [tegra_clk_osc_div4] = { .dt_id = TEGRA114_CLK_OSC_DIV4, .present = true }, 741 [tegra_clk_pll_ref] = { .dt_id = TEGRA114_CLK_PLL_REF, .present = true }, 742 [tegra_clk_pll_c] = { .dt_id = TEGRA114_CLK_PLL_C, .present = true }, 743 [tegra_clk_pll_c_out1] = { .dt_id = TEGRA114_CLK_PLL_C_OUT1, .present = true }, 744 [tegra_clk_pll_c2] = { .dt_id = TEGRA114_CLK_PLL_C2, .present = true }, 745 [tegra_clk_pll_c3] = { .dt_id = TEGRA114_CLK_PLL_C3, .present = true }, 746 [tegra_clk_pll_m] = { .dt_id = TEGRA114_CLK_PLL_M, .present = true }, 747 [tegra_clk_pll_m_out1] = { .dt_id = TEGRA114_CLK_PLL_M_OUT1, .present = true }, 748 [tegra_clk_pll_p] = { .dt_id = TEGRA114_CLK_PLL_P, .present = true }, 749 [tegra_clk_pll_p_out1] = { .dt_id = TEGRA114_CLK_PLL_P_OUT1, .present = true }, 750 [tegra_clk_pll_p_out2_int] = { .dt_id = TEGRA114_CLK_PLL_P_OUT2, .present = true }, 751 [tegra_clk_pll_p_out3] = { .dt_id = TEGRA114_CLK_PLL_P_OUT3, .present = true }, 752 [tegra_clk_pll_p_out4] = { .dt_id = TEGRA114_CLK_PLL_P_OUT4, .present = true }, 753 [tegra_clk_pll_a] = { .dt_id = TEGRA114_CLK_PLL_A, .present = true }, 754 [tegra_clk_pll_a_out0] = { .dt_id = TEGRA114_CLK_PLL_A_OUT0, .present = true }, 755 [tegra_clk_pll_d] = { .dt_id = TEGRA114_CLK_PLL_D, .present = true }, 756 [tegra_clk_pll_d_out0] = { .dt_id = TEGRA114_CLK_PLL_D_OUT0, .present = true }, 757 [tegra_clk_pll_d2] = { .dt_id = TEGRA114_CLK_PLL_D2, .present = true }, 758 [tegra_clk_pll_d2_out0] = { .dt_id = TEGRA114_CLK_PLL_D2_OUT0, .present = true }, 759 [tegra_clk_pll_u] = { .dt_id = TEGRA114_CLK_PLL_U, .present = true }, 760 [tegra_clk_pll_u_480m] = { .dt_id = TEGRA114_CLK_PLL_U_480M, .present = true }, 761 [tegra_clk_pll_u_60m] = { .dt_id = TEGRA114_CLK_PLL_U_60M, .present = true }, 762 [tegra_clk_pll_u_48m] = { .dt_id = TEGRA114_CLK_PLL_U_48M, .present = true }, 763 [tegra_clk_pll_u_12m] = { .dt_id = TEGRA114_CLK_PLL_U_12M, .present = true }, 764 [tegra_clk_pll_x] = { .dt_id = TEGRA114_CLK_PLL_X, .present = true }, 765 [tegra_clk_pll_x_out0] = { .dt_id = TEGRA114_CLK_PLL_X_OUT0, .present = true }, 766 [tegra_clk_pll_re_vco] = { .dt_id = TEGRA114_CLK_PLL_RE_VCO, .present = true }, 767 [tegra_clk_pll_re_out] = { .dt_id = TEGRA114_CLK_PLL_RE_OUT, .present = true }, 768 [tegra_clk_pll_e_out0] = { .dt_id = TEGRA114_CLK_PLL_E_OUT0, .present = true }, 769 [tegra_clk_spdif_in_sync] = { .dt_id = TEGRA114_CLK_SPDIF_IN_SYNC, .present = true }, 770 [tegra_clk_i2s0_sync] = { .dt_id = TEGRA114_CLK_I2S0_SYNC, .present = true }, 771 [tegra_clk_i2s1_sync] = { .dt_id = TEGRA114_CLK_I2S1_SYNC, .present = true }, 772 [tegra_clk_i2s2_sync] = { .dt_id = TEGRA114_CLK_I2S2_SYNC, .present = true }, 773 [tegra_clk_i2s3_sync] = { .dt_id = TEGRA114_CLK_I2S3_SYNC, .present = true }, 774 [tegra_clk_i2s4_sync] = { .dt_id = TEGRA114_CLK_I2S4_SYNC, .present = true }, 775 [tegra_clk_vimclk_sync] = { .dt_id = TEGRA114_CLK_VIMCLK_SYNC, .present = true }, 776 [tegra_clk_audio0] = { .dt_id = TEGRA114_CLK_AUDIO0, .present = true }, 777 [tegra_clk_audio1] = { .dt_id = TEGRA114_CLK_AUDIO1, .present = true }, 778 [tegra_clk_audio2] = { .dt_id = TEGRA114_CLK_AUDIO2, .present = true }, 779 [tegra_clk_audio3] = { .dt_id = TEGRA114_CLK_AUDIO3, .present = true }, 780 [tegra_clk_audio4] = { .dt_id = TEGRA114_CLK_AUDIO4, .present = true }, 781 [tegra_clk_spdif] = { .dt_id = TEGRA114_CLK_SPDIF, .present = true }, 782 [tegra_clk_xusb_host_src] = { .dt_id = TEGRA114_CLK_XUSB_HOST_SRC, .present = true }, 783 [tegra_clk_xusb_falcon_src] = { .dt_id = TEGRA114_CLK_XUSB_FALCON_SRC, .present = true }, 784 [tegra_clk_xusb_fs_src] = { .dt_id = TEGRA114_CLK_XUSB_FS_SRC, .present = true }, 785 [tegra_clk_xusb_ss_src] = { .dt_id = TEGRA114_CLK_XUSB_SS_SRC, .present = true }, 786 [tegra_clk_xusb_ss_div2] = { .dt_id = TEGRA114_CLK_XUSB_SS_DIV2, .present = true}, 787 [tegra_clk_xusb_dev_src] = { .dt_id = TEGRA114_CLK_XUSB_DEV_SRC, .present = true }, 788 [tegra_clk_xusb_dev] = { .dt_id = TEGRA114_CLK_XUSB_DEV, .present = true }, 789 [tegra_clk_xusb_hs_src] = { .dt_id = TEGRA114_CLK_XUSB_HS_SRC, .present = true }, 790 [tegra_clk_sclk] = { .dt_id = TEGRA114_CLK_SCLK, .present = true }, 791 [tegra_clk_hclk] = { .dt_id = TEGRA114_CLK_HCLK, .present = true }, 792 [tegra_clk_pclk] = { .dt_id = TEGRA114_CLK_PCLK, .present = true }, 793 [tegra_clk_cclk_g] = { .dt_id = TEGRA114_CLK_CCLK_G, .present = true }, 794 [tegra_clk_cclk_lp] = { .dt_id = TEGRA114_CLK_CCLK_LP, .present = true }, 795 [tegra_clk_dfll_ref] = { .dt_id = TEGRA114_CLK_DFLL_REF, .present = true }, 796 [tegra_clk_dfll_soc] = { .dt_id = TEGRA114_CLK_DFLL_SOC, .present = true }, 797 [tegra_clk_audio0_mux] = { .dt_id = TEGRA114_CLK_AUDIO0_MUX, .present = true }, 798 [tegra_clk_audio1_mux] = { .dt_id = TEGRA114_CLK_AUDIO1_MUX, .present = true }, 799 [tegra_clk_audio2_mux] = { .dt_id = TEGRA114_CLK_AUDIO2_MUX, .present = true }, 800 [tegra_clk_audio3_mux] = { .dt_id = TEGRA114_CLK_AUDIO3_MUX, .present = true }, 801 [tegra_clk_audio4_mux] = { .dt_id = TEGRA114_CLK_AUDIO4_MUX, .present = true }, 802 [tegra_clk_spdif_mux] = { .dt_id = TEGRA114_CLK_SPDIF_MUX, .present = true }, 803 [tegra_clk_dsia_mux] = { .dt_id = TEGRA114_CLK_DSIA_MUX, .present = true }, 804 [tegra_clk_dsib_mux] = { .dt_id = TEGRA114_CLK_DSIB_MUX, .present = true }, 805 [tegra_clk_cec] = { .dt_id = TEGRA114_CLK_CEC, .present = true }, 806}; 807 808static struct tegra_devclk devclks[] __initdata = { 809 { .con_id = "clk_m", .dt_id = TEGRA114_CLK_CLK_M }, 810 { .con_id = "pll_ref", .dt_id = TEGRA114_CLK_PLL_REF }, 811 { .con_id = "clk_32k", .dt_id = TEGRA114_CLK_CLK_32K }, 812 { .con_id = "osc", .dt_id = TEGRA114_CLK_OSC }, 813 { .con_id = "osc_div2", .dt_id = TEGRA114_CLK_OSC_DIV2 }, 814 { .con_id = "osc_div4", .dt_id = TEGRA114_CLK_OSC_DIV4 }, 815 { .con_id = "pll_c", .dt_id = TEGRA114_CLK_PLL_C }, 816 { .con_id = "pll_c_out1", .dt_id = TEGRA114_CLK_PLL_C_OUT1 }, 817 { .con_id = "pll_c2", .dt_id = TEGRA114_CLK_PLL_C2 }, 818 { .con_id = "pll_c3", .dt_id = TEGRA114_CLK_PLL_C3 }, 819 { .con_id = "pll_p", .dt_id = TEGRA114_CLK_PLL_P }, 820 { .con_id = "pll_p_out1", .dt_id = TEGRA114_CLK_PLL_P_OUT1 }, 821 { .con_id = "pll_p_out2", .dt_id = TEGRA114_CLK_PLL_P_OUT2 }, 822 { .con_id = "pll_p_out3", .dt_id = TEGRA114_CLK_PLL_P_OUT3 }, 823 { .con_id = "pll_p_out4", .dt_id = TEGRA114_CLK_PLL_P_OUT4 }, 824 { .con_id = "pll_m", .dt_id = TEGRA114_CLK_PLL_M }, 825 { .con_id = "pll_m_out1", .dt_id = TEGRA114_CLK_PLL_M_OUT1 }, 826 { .con_id = "pll_x", .dt_id = TEGRA114_CLK_PLL_X }, 827 { .con_id = "pll_x_out0", .dt_id = TEGRA114_CLK_PLL_X_OUT0 }, 828 { .con_id = "pll_u", .dt_id = TEGRA114_CLK_PLL_U }, 829 { .con_id = "pll_u_480M", .dt_id = TEGRA114_CLK_PLL_U_480M }, 830 { .con_id = "pll_u_60M", .dt_id = TEGRA114_CLK_PLL_U_60M }, 831 { .con_id = "pll_u_48M", .dt_id = TEGRA114_CLK_PLL_U_48M }, 832 { .con_id = "pll_u_12M", .dt_id = TEGRA114_CLK_PLL_U_12M }, 833 { .con_id = "pll_d", .dt_id = TEGRA114_CLK_PLL_D }, 834 { .con_id = "pll_d_out0", .dt_id = TEGRA114_CLK_PLL_D_OUT0 }, 835 { .con_id = "pll_d2", .dt_id = TEGRA114_CLK_PLL_D2 }, 836 { .con_id = "pll_d2_out0", .dt_id = TEGRA114_CLK_PLL_D2_OUT0 }, 837 { .con_id = "pll_a", .dt_id = TEGRA114_CLK_PLL_A }, 838 { .con_id = "pll_a_out0", .dt_id = TEGRA114_CLK_PLL_A_OUT0 }, 839 { .con_id = "pll_re_vco", .dt_id = TEGRA114_CLK_PLL_RE_VCO }, 840 { .con_id = "pll_re_out", .dt_id = TEGRA114_CLK_PLL_RE_OUT }, 841 { .con_id = "pll_e_out0", .dt_id = TEGRA114_CLK_PLL_E_OUT0 }, 842 { .con_id = "spdif_in_sync", .dt_id = TEGRA114_CLK_SPDIF_IN_SYNC }, 843 { .con_id = "i2s0_sync", .dt_id = TEGRA114_CLK_I2S0_SYNC }, 844 { .con_id = "i2s1_sync", .dt_id = TEGRA114_CLK_I2S1_SYNC }, 845 { .con_id = "i2s2_sync", .dt_id = TEGRA114_CLK_I2S2_SYNC }, 846 { .con_id = "i2s3_sync", .dt_id = TEGRA114_CLK_I2S3_SYNC }, 847 { .con_id = "i2s4_sync", .dt_id = TEGRA114_CLK_I2S4_SYNC }, 848 { .con_id = "vimclk_sync", .dt_id = TEGRA114_CLK_VIMCLK_SYNC }, 849 { .con_id = "audio0", .dt_id = TEGRA114_CLK_AUDIO0 }, 850 { .con_id = "audio1", .dt_id = TEGRA114_CLK_AUDIO1 }, 851 { .con_id = "audio2", .dt_id = TEGRA114_CLK_AUDIO2 }, 852 { .con_id = "audio3", .dt_id = TEGRA114_CLK_AUDIO3 }, 853 { .con_id = "audio4", .dt_id = TEGRA114_CLK_AUDIO4 }, 854 { .con_id = "spdif", .dt_id = TEGRA114_CLK_SPDIF }, 855 { .con_id = "audio0_2x", .dt_id = TEGRA114_CLK_AUDIO0_2X }, 856 { .con_id = "audio1_2x", .dt_id = TEGRA114_CLK_AUDIO1_2X }, 857 { .con_id = "audio2_2x", .dt_id = TEGRA114_CLK_AUDIO2_2X }, 858 { .con_id = "audio3_2x", .dt_id = TEGRA114_CLK_AUDIO3_2X }, 859 { .con_id = "audio4_2x", .dt_id = TEGRA114_CLK_AUDIO4_2X }, 860 { .con_id = "spdif_2x", .dt_id = TEGRA114_CLK_SPDIF_2X }, 861 { .con_id = "extern1", .dt_id = TEGRA114_CLK_EXTERN1 }, 862 { .con_id = "extern2", .dt_id = TEGRA114_CLK_EXTERN2 }, 863 { .con_id = "extern3", .dt_id = TEGRA114_CLK_EXTERN3 }, 864 { .con_id = "cclk_g", .dt_id = TEGRA114_CLK_CCLK_G }, 865 { .con_id = "cclk_lp", .dt_id = TEGRA114_CLK_CCLK_LP }, 866 { .con_id = "sclk", .dt_id = TEGRA114_CLK_SCLK }, 867 { .con_id = "hclk", .dt_id = TEGRA114_CLK_HCLK }, 868 { .con_id = "pclk", .dt_id = TEGRA114_CLK_PCLK }, 869 { .con_id = "fuse", .dt_id = TEGRA114_CLK_FUSE }, 870 { .dev_id = "rtc-tegra", .dt_id = TEGRA114_CLK_RTC }, 871 { .dev_id = "timer", .dt_id = TEGRA114_CLK_TIMER }, 872}; 873 874static const char *mux_pllm_pllc2_c_c3_pllp_plla[] = { 875 "pll_m", "pll_c2", "pll_c", "pll_c3", "pll_p", "pll_a_out0" 876}; 877static u32 mux_pllm_pllc2_c_c3_pllp_plla_idx[] = { 878 [0] = 0, [1] = 1, [2] = 2, [3] = 3, [4] = 4, [5] = 6, 879}; 880 881static struct tegra_audio_clk_info tegra114_audio_plls[] = { 882 { "pll_a", &pll_a_params, tegra_clk_pll_a, "pll_p_out1" }, 883}; 884 885static struct clk **clks; 886 887static unsigned long osc_freq; 888static unsigned long pll_ref_freq; 889 890static void __init tegra114_fixed_clk_init(void __iomem *clk_base) 891{ 892 struct clk *clk; 893 894 /* clk_32k */ 895 clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, 0, 32768); 896 clks[TEGRA114_CLK_CLK_32K] = clk; 897} 898 899static void __init tegra114_pll_init(void __iomem *clk_base, 900 void __iomem *pmc) 901{ 902 struct clk *clk; 903 904 /* PLLC */ 905 clk = tegra_clk_register_pllxc("pll_c", "pll_ref", clk_base, 906 pmc, 0, &pll_c_params, NULL); 907 clks[TEGRA114_CLK_PLL_C] = clk; 908 909 /* PLLC_OUT1 */ 910 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c", 911 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP, 912 8, 8, 1, NULL); 913 clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div", 914 clk_base + PLLC_OUT, 1, 0, 915 CLK_SET_RATE_PARENT, 0, NULL); 916 clks[TEGRA114_CLK_PLL_C_OUT1] = clk; 917 918 /* PLLC2 */ 919 clk = tegra_clk_register_pllc("pll_c2", "pll_ref", clk_base, pmc, 0, 920 &pll_c2_params, NULL); 921 clks[TEGRA114_CLK_PLL_C2] = clk; 922 923 /* PLLC3 */ 924 clk = tegra_clk_register_pllc("pll_c3", "pll_ref", clk_base, pmc, 0, 925 &pll_c3_params, NULL); 926 clks[TEGRA114_CLK_PLL_C3] = clk; 927 928 /* PLLM */ 929 clk = tegra_clk_register_pllm("pll_m", "pll_ref", clk_base, pmc, 930 CLK_SET_RATE_GATE, &pll_m_params, NULL); 931 clks[TEGRA114_CLK_PLL_M] = clk; 932 933 /* PLLM_OUT1 */ 934 clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m", 935 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP, 936 8, 8, 1, NULL); 937 clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div", 938 clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED | 939 CLK_SET_RATE_PARENT, 0, NULL); 940 clks[TEGRA114_CLK_PLL_M_OUT1] = clk; 941 942 /* PLLM_UD */ 943 clk = clk_register_fixed_factor(NULL, "pll_m_ud", "pll_m", 944 CLK_SET_RATE_PARENT, 1, 1); 945 946 /* PLLU */ 947 clk = tegra_clk_register_pllu_tegra114("pll_u", "pll_ref", clk_base, 0, 948 &pll_u_params, &pll_u_lock); 949 clks[TEGRA114_CLK_PLL_U] = clk; 950 951 /* PLLU_480M */ 952 clk = clk_register_gate(NULL, "pll_u_480M", "pll_u", 953 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE, 954 22, 0, &pll_u_lock); 955 clks[TEGRA114_CLK_PLL_U_480M] = clk; 956 957 /* PLLU_60M */ 958 clk = clk_register_fixed_factor(NULL, "pll_u_60M", "pll_u", 959 CLK_SET_RATE_PARENT, 1, 8); 960 clks[TEGRA114_CLK_PLL_U_60M] = clk; 961 962 /* PLLU_48M */ 963 clk = clk_register_fixed_factor(NULL, "pll_u_48M", "pll_u", 964 CLK_SET_RATE_PARENT, 1, 10); 965 clks[TEGRA114_CLK_PLL_U_48M] = clk; 966 967 /* PLLU_12M */ 968 clk = clk_register_fixed_factor(NULL, "pll_u_12M", "pll_u", 969 CLK_SET_RATE_PARENT, 1, 40); 970 clks[TEGRA114_CLK_PLL_U_12M] = clk; 971 972 /* PLLD */ 973 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc, 0, 974 &pll_d_params, &pll_d_lock); 975 clks[TEGRA114_CLK_PLL_D] = clk; 976 977 /* PLLD_OUT0 */ 978 clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d", 979 CLK_SET_RATE_PARENT, 1, 2); 980 clks[TEGRA114_CLK_PLL_D_OUT0] = clk; 981 982 /* PLLD2 */ 983 clk = tegra_clk_register_pll("pll_d2", "pll_ref", clk_base, pmc, 0, 984 &pll_d2_params, &pll_d2_lock); 985 clks[TEGRA114_CLK_PLL_D2] = clk; 986 987 /* PLLD2_OUT0 */ 988 clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2", 989 CLK_SET_RATE_PARENT, 1, 2); 990 clks[TEGRA114_CLK_PLL_D2_OUT0] = clk; 991 992 /* PLLRE */ 993 clk = tegra_clk_register_pllre("pll_re_vco", "pll_ref", clk_base, pmc, 994 0, &pll_re_vco_params, &pll_re_lock, pll_ref_freq); 995 clks[TEGRA114_CLK_PLL_RE_VCO] = clk; 996 997 clk = clk_register_divider_table(NULL, "pll_re_out", "pll_re_vco", 0, 998 clk_base + PLLRE_BASE, 16, 4, 0, 999 pll_re_div_table, &pll_re_lock); 1000 clks[TEGRA114_CLK_PLL_RE_OUT] = clk; 1001 1002 /* PLLE */ 1003 clk = tegra_clk_register_plle_tegra114("pll_e_out0", "pll_ref", 1004 clk_base, 0, &pll_e_params, NULL); 1005 clks[TEGRA114_CLK_PLL_E_OUT0] = clk; 1006} 1007 1008#define CLK_SOURCE_VI_SENSOR 0x1a8 1009 1010static struct tegra_periph_init_data tegra_periph_clk_list[] = { 1011 MUX8("vi_sensor", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR, 20, TEGRA_PERIPH_NO_RESET, TEGRA114_CLK_VI_SENSOR), 1012}; 1013 1014static __init void tegra114_periph_clk_init(void __iomem *clk_base, 1015 void __iomem *pmc_base) 1016{ 1017 struct clk *clk; 1018 struct tegra_periph_init_data *data; 1019 unsigned int i; 1020 1021 /* xusb_ss_div2 */ 1022 clk = clk_register_fixed_factor(NULL, "xusb_ss_div2", "xusb_ss_src", 0, 1023 1, 2); 1024 clks[TEGRA114_CLK_XUSB_SS_DIV2] = clk; 1025 1026 /* dsia mux */ 1027 clk = clk_register_mux(NULL, "dsia_mux", mux_plld_out0_plld2_out0, 1028 ARRAY_SIZE(mux_plld_out0_plld2_out0), 1029 CLK_SET_RATE_NO_REPARENT, 1030 clk_base + PLLD_BASE, 25, 1, 0, &pll_d_lock); 1031 clks[TEGRA114_CLK_DSIA_MUX] = clk; 1032 1033 /* dsib mux */ 1034 clk = clk_register_mux(NULL, "dsib_mux", mux_plld_out0_plld2_out0, 1035 ARRAY_SIZE(mux_plld_out0_plld2_out0), 1036 CLK_SET_RATE_NO_REPARENT, 1037 clk_base + PLLD2_BASE, 25, 1, 0, &pll_d2_lock); 1038 clks[TEGRA114_CLK_DSIB_MUX] = clk; 1039 1040 clk = tegra_clk_register_periph_gate("dsia", "dsia_mux", 0, clk_base, 1041 0, 48, periph_clk_enb_refcnt); 1042 clks[TEGRA114_CLK_DSIA] = clk; 1043 1044 clk = tegra_clk_register_periph_gate("dsib", "dsib_mux", 0, clk_base, 1045 0, 82, periph_clk_enb_refcnt); 1046 clks[TEGRA114_CLK_DSIB] = clk; 1047 1048 /* emc mux */ 1049 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm, 1050 ARRAY_SIZE(mux_pllmcp_clkm), 1051 CLK_SET_RATE_NO_REPARENT, 1052 clk_base + CLK_SOURCE_EMC, 1053 29, 3, 0, &emc_lock); 1054 1055 clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC, 1056 &emc_lock); 1057 clks[TEGRA114_CLK_MC] = clk; 1058 1059 clk = tegra_clk_register_periph_gate("mipi-cal", "clk_m", 0, clk_base, 1060 CLK_SET_RATE_PARENT, 56, 1061 periph_clk_enb_refcnt); 1062 clks[TEGRA114_CLK_MIPI_CAL] = clk; 1063 1064 for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) { 1065 data = &tegra_periph_clk_list[i]; 1066 clk = tegra_clk_register_periph_data(clk_base, data); 1067 clks[data->clk_id] = clk; 1068 } 1069 1070 tegra_periph_clk_init(clk_base, pmc_base, tegra114_clks, 1071 &pll_p_params); 1072} 1073 1074/* Tegra114 CPU clock and reset control functions */ 1075static void tegra114_wait_cpu_in_reset(u32 cpu) 1076{ 1077 unsigned int reg; 1078 1079 do { 1080 reg = readl(clk_base + CLK_RST_CONTROLLER_CPU_CMPLX_STATUS); 1081 cpu_relax(); 1082 } while (!(reg & (1 << cpu))); /* check CPU been reset or not */ 1083} 1084 1085static void tegra114_disable_cpu_clock(u32 cpu) 1086{ 1087 /* flow controller would take care in the power sequence. */ 1088} 1089 1090#ifdef CONFIG_PM_SLEEP 1091static void tegra114_cpu_clock_suspend(void) 1092{ 1093 /* switch coresite to clk_m, save off original source */ 1094 tegra114_cpu_clk_sctx.clk_csite_src = 1095 readl(clk_base + CLK_SOURCE_CSITE); 1096 writel(3 << 30, clk_base + CLK_SOURCE_CSITE); 1097 1098 tegra114_cpu_clk_sctx.cclkg_burst = 1099 readl(clk_base + CCLKG_BURST_POLICY); 1100 tegra114_cpu_clk_sctx.cclkg_divider = 1101 readl(clk_base + CCLKG_BURST_POLICY + 4); 1102} 1103 1104static void tegra114_cpu_clock_resume(void) 1105{ 1106 writel(tegra114_cpu_clk_sctx.clk_csite_src, 1107 clk_base + CLK_SOURCE_CSITE); 1108 1109 writel(tegra114_cpu_clk_sctx.cclkg_burst, 1110 clk_base + CCLKG_BURST_POLICY); 1111 writel(tegra114_cpu_clk_sctx.cclkg_divider, 1112 clk_base + CCLKG_BURST_POLICY + 4); 1113} 1114#endif 1115 1116static struct tegra_cpu_car_ops tegra114_cpu_car_ops = { 1117 .wait_for_reset = tegra114_wait_cpu_in_reset, 1118 .disable_clock = tegra114_disable_cpu_clock, 1119#ifdef CONFIG_PM_SLEEP 1120 .suspend = tegra114_cpu_clock_suspend, 1121 .resume = tegra114_cpu_clock_resume, 1122#endif 1123}; 1124 1125static const struct of_device_id pmc_match[] __initconst = { 1126 { .compatible = "nvidia,tegra114-pmc" }, 1127 { }, 1128}; 1129 1130/* 1131 * dfll_soc/dfll_ref apparently must be kept enabled, otherwise I2C5 1132 * breaks 1133 */ 1134static struct tegra_clk_init_table init_table[] __initdata = { 1135 { TEGRA114_CLK_UARTA, TEGRA114_CLK_PLL_P, 408000000, 0 }, 1136 { TEGRA114_CLK_UARTB, TEGRA114_CLK_PLL_P, 408000000, 0 }, 1137 { TEGRA114_CLK_UARTC, TEGRA114_CLK_PLL_P, 408000000, 0 }, 1138 { TEGRA114_CLK_UARTD, TEGRA114_CLK_PLL_P, 408000000, 0 }, 1139 { TEGRA114_CLK_PLL_A, TEGRA114_CLK_CLK_MAX, 564480000, 0 }, 1140 { TEGRA114_CLK_PLL_A_OUT0, TEGRA114_CLK_CLK_MAX, 11289600, 0 }, 1141 { TEGRA114_CLK_I2S0, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 }, 1142 { TEGRA114_CLK_I2S1, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 }, 1143 { TEGRA114_CLK_I2S2, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 }, 1144 { TEGRA114_CLK_I2S3, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 }, 1145 { TEGRA114_CLK_I2S4, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 }, 1146 { TEGRA114_CLK_HOST1X, TEGRA114_CLK_PLL_P, 136000000, 0 }, 1147 { TEGRA114_CLK_DFLL_SOC, TEGRA114_CLK_PLL_P, 51000000, 1 }, 1148 { TEGRA114_CLK_DFLL_REF, TEGRA114_CLK_PLL_P, 51000000, 1 }, 1149 { TEGRA114_CLK_DISP1, TEGRA114_CLK_PLL_P, 0, 0 }, 1150 { TEGRA114_CLK_DISP2, TEGRA114_CLK_PLL_P, 0, 0 }, 1151 { TEGRA114_CLK_GR2D, TEGRA114_CLK_PLL_C2, 300000000, 0 }, 1152 { TEGRA114_CLK_GR3D, TEGRA114_CLK_PLL_C2, 300000000, 0 }, 1153 { TEGRA114_CLK_DSIALP, TEGRA114_CLK_PLL_P, 68000000, 0 }, 1154 { TEGRA114_CLK_DSIBLP, TEGRA114_CLK_PLL_P, 68000000, 0 }, 1155 { TEGRA114_CLK_PLL_RE_VCO, TEGRA114_CLK_CLK_MAX, 612000000, 0 }, 1156 { TEGRA114_CLK_XUSB_SS_SRC, TEGRA114_CLK_PLL_RE_OUT, 122400000, 0 }, 1157 { TEGRA114_CLK_XUSB_FS_SRC, TEGRA114_CLK_PLL_U_48M, 48000000, 0 }, 1158 { TEGRA114_CLK_XUSB_HS_SRC, TEGRA114_CLK_XUSB_SS_DIV2, 61200000, 0 }, 1159 { TEGRA114_CLK_XUSB_FALCON_SRC, TEGRA114_CLK_PLL_P, 204000000, 0 }, 1160 { TEGRA114_CLK_XUSB_HOST_SRC, TEGRA114_CLK_PLL_P, 102000000, 0 }, 1161 { TEGRA114_CLK_VDE, TEGRA114_CLK_CLK_MAX, 600000000, 0 }, 1162 { TEGRA114_CLK_SPDIF_IN_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 }, 1163 { TEGRA114_CLK_I2S0_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 }, 1164 { TEGRA114_CLK_I2S1_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 }, 1165 { TEGRA114_CLK_I2S2_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 }, 1166 { TEGRA114_CLK_I2S3_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 }, 1167 { TEGRA114_CLK_I2S4_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 }, 1168 { TEGRA114_CLK_VIMCLK_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 }, 1169 /* must be the last entry */ 1170 { TEGRA114_CLK_CLK_MAX, TEGRA114_CLK_CLK_MAX, 0, 0 }, 1171}; 1172 1173static void __init tegra114_clock_apply_init_table(void) 1174{ 1175 tegra_init_from_table(init_table, clks, TEGRA114_CLK_CLK_MAX); 1176} 1177 1178/** 1179 * tegra114_car_barrier - wait for pending writes to the CAR to complete 1180 * 1181 * Wait for any outstanding writes to the CAR MMIO space from this CPU 1182 * to complete before continuing execution. No return value. 1183 */ 1184static void tegra114_car_barrier(void) 1185{ 1186 wmb(); /* probably unnecessary */ 1187 readl_relaxed(clk_base + CPU_FINETRIM_SELECT); 1188} 1189 1190/** 1191 * tegra114_clock_tune_cpu_trimmers_high - use high-voltage propagation delays 1192 * 1193 * When the CPU rail voltage is in the high-voltage range, use the 1194 * built-in hardwired clock propagation delays in the CPU clock 1195 * shaper. No return value. 1196 */ 1197void tegra114_clock_tune_cpu_trimmers_high(void) 1198{ 1199 u32 select = 0; 1200 1201 /* Use hardwired rise->rise & fall->fall clock propagation delays */ 1202 select |= ~(CPU_FINETRIM_1_FCPU_1 | CPU_FINETRIM_1_FCPU_2 | 1203 CPU_FINETRIM_1_FCPU_3 | CPU_FINETRIM_1_FCPU_4 | 1204 CPU_FINETRIM_1_FCPU_5 | CPU_FINETRIM_1_FCPU_6); 1205 writel_relaxed(select, clk_base + CPU_FINETRIM_SELECT); 1206 1207 tegra114_car_barrier(); 1208} 1209EXPORT_SYMBOL(tegra114_clock_tune_cpu_trimmers_high); 1210 1211/** 1212 * tegra114_clock_tune_cpu_trimmers_low - use low-voltage propagation delays 1213 * 1214 * When the CPU rail voltage is in the low-voltage range, use the 1215 * extended clock propagation delays set by 1216 * tegra114_clock_tune_cpu_trimmers_init(). The intention is to 1217 * maintain the input clock duty cycle that the FCPU subsystem 1218 * expects. No return value. 1219 */ 1220void tegra114_clock_tune_cpu_trimmers_low(void) 1221{ 1222 u32 select = 0; 1223 1224 /* 1225 * Use software-specified rise->rise & fall->fall clock 1226 * propagation delays (from 1227 * tegra114_clock_tune_cpu_trimmers_init() 1228 */ 1229 select |= (CPU_FINETRIM_1_FCPU_1 | CPU_FINETRIM_1_FCPU_2 | 1230 CPU_FINETRIM_1_FCPU_3 | CPU_FINETRIM_1_FCPU_4 | 1231 CPU_FINETRIM_1_FCPU_5 | CPU_FINETRIM_1_FCPU_6); 1232 writel_relaxed(select, clk_base + CPU_FINETRIM_SELECT); 1233 1234 tegra114_car_barrier(); 1235} 1236EXPORT_SYMBOL(tegra114_clock_tune_cpu_trimmers_low); 1237 1238/** 1239 * tegra114_clock_tune_cpu_trimmers_init - set up and enable clk prop delays 1240 * 1241 * Program extended clock propagation delays into the FCPU clock 1242 * shaper and enable them. XXX Define the purpose - peak current 1243 * reduction? No return value. 1244 */ 1245/* XXX Initial voltage rail state assumption issues? */ 1246void tegra114_clock_tune_cpu_trimmers_init(void) 1247{ 1248 u32 dr = 0, r = 0; 1249 1250 /* Increment the rise->rise clock delay by four steps */ 1251 r |= (CPU_FINETRIM_R_FCPU_1_MASK | CPU_FINETRIM_R_FCPU_2_MASK | 1252 CPU_FINETRIM_R_FCPU_3_MASK | CPU_FINETRIM_R_FCPU_4_MASK | 1253 CPU_FINETRIM_R_FCPU_5_MASK | CPU_FINETRIM_R_FCPU_6_MASK); 1254 writel_relaxed(r, clk_base + CPU_FINETRIM_R); 1255 1256 /* 1257 * Use the rise->rise clock propagation delay specified in the 1258 * r field 1259 */ 1260 dr |= (CPU_FINETRIM_1_FCPU_1 | CPU_FINETRIM_1_FCPU_2 | 1261 CPU_FINETRIM_1_FCPU_3 | CPU_FINETRIM_1_FCPU_4 | 1262 CPU_FINETRIM_1_FCPU_5 | CPU_FINETRIM_1_FCPU_6); 1263 writel_relaxed(dr, clk_base + CPU_FINETRIM_DR); 1264 1265 tegra114_clock_tune_cpu_trimmers_low(); 1266} 1267EXPORT_SYMBOL(tegra114_clock_tune_cpu_trimmers_init); 1268 1269/** 1270 * tegra114_clock_assert_dfll_dvco_reset - assert the DFLL's DVCO reset 1271 * 1272 * Assert the reset line of the DFLL's DVCO. No return value. 1273 */ 1274void tegra114_clock_assert_dfll_dvco_reset(void) 1275{ 1276 u32 v; 1277 1278 v = readl_relaxed(clk_base + RST_DFLL_DVCO); 1279 v |= (1 << DVFS_DFLL_RESET_SHIFT); 1280 writel_relaxed(v, clk_base + RST_DFLL_DVCO); 1281 tegra114_car_barrier(); 1282} 1283EXPORT_SYMBOL(tegra114_clock_assert_dfll_dvco_reset); 1284 1285/** 1286 * tegra114_clock_deassert_dfll_dvco_reset - deassert the DFLL's DVCO reset 1287 * 1288 * Deassert the reset line of the DFLL's DVCO, allowing the DVCO to 1289 * operate. No return value. 1290 */ 1291void tegra114_clock_deassert_dfll_dvco_reset(void) 1292{ 1293 u32 v; 1294 1295 v = readl_relaxed(clk_base + RST_DFLL_DVCO); 1296 v &= ~(1 << DVFS_DFLL_RESET_SHIFT); 1297 writel_relaxed(v, clk_base + RST_DFLL_DVCO); 1298 tegra114_car_barrier(); 1299} 1300EXPORT_SYMBOL(tegra114_clock_deassert_dfll_dvco_reset); 1301 1302static void __init tegra114_clock_init(struct device_node *np) 1303{ 1304 struct device_node *node; 1305 1306 clk_base = of_iomap(np, 0); 1307 if (!clk_base) { 1308 pr_err("ioremap tegra114 CAR failed\n"); 1309 return; 1310 } 1311 1312 node = of_find_matching_node(NULL, pmc_match); 1313 if (!node) { 1314 pr_err("Failed to find pmc node\n"); 1315 WARN_ON(1); 1316 return; 1317 } 1318 1319 pmc_base = of_iomap(node, 0); 1320 of_node_put(node); 1321 if (!pmc_base) { 1322 pr_err("Can't map pmc registers\n"); 1323 WARN_ON(1); 1324 return; 1325 } 1326 1327 clks = tegra_clk_init(clk_base, TEGRA114_CLK_CLK_MAX, 1328 TEGRA114_CLK_PERIPH_BANKS); 1329 if (!clks) 1330 return; 1331 1332 if (tegra_osc_clk_init(clk_base, tegra114_clks, tegra114_input_freq, 1333 ARRAY_SIZE(tegra114_input_freq), 1, &osc_freq, 1334 &pll_ref_freq) < 0) 1335 return; 1336 1337 tegra114_fixed_clk_init(clk_base); 1338 tegra114_pll_init(clk_base, pmc_base); 1339 tegra114_periph_clk_init(clk_base, pmc_base); 1340 tegra_audio_clk_init(clk_base, pmc_base, tegra114_clks, 1341 tegra114_audio_plls, 1342 ARRAY_SIZE(tegra114_audio_plls), 24000000); 1343 tegra_super_clk_gen4_init(clk_base, pmc_base, tegra114_clks, 1344 &pll_x_params); 1345 1346 tegra_add_of_provider(np, of_clk_src_onecell_get); 1347 tegra_register_devclks(devclks, ARRAY_SIZE(devclks)); 1348 1349 tegra_clk_apply_init_table = tegra114_clock_apply_init_table; 1350 1351 tegra_cpu_car_ops = &tegra114_cpu_car_ops; 1352} 1353CLK_OF_DECLARE(tegra114, "nvidia,tegra114-car", tegra114_clock_init); 1354