18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0+ */ 28c2ecf20Sopenharmony_ci/* 38c2ecf20Sopenharmony_ci * Copyright 2017 Icenowy Zheng <icenowy@aosc.io> 48c2ecf20Sopenharmony_ci * 58c2ecf20Sopenharmony_ci */ 68c2ecf20Sopenharmony_ci 78c2ecf20Sopenharmony_ci#ifndef _CCU_SUNIV_F1C100S_H_ 88c2ecf20Sopenharmony_ci#define _CCU_SUNIV_F1C100S_H_ 98c2ecf20Sopenharmony_ci 108c2ecf20Sopenharmony_ci#include <dt-bindings/clock/suniv-ccu-f1c100s.h> 118c2ecf20Sopenharmony_ci#include <dt-bindings/reset/suniv-ccu-f1c100s.h> 128c2ecf20Sopenharmony_ci 138c2ecf20Sopenharmony_ci#define CLK_PLL_CPU 0 148c2ecf20Sopenharmony_ci#define CLK_PLL_AUDIO_BASE 1 158c2ecf20Sopenharmony_ci#define CLK_PLL_AUDIO 2 168c2ecf20Sopenharmony_ci#define CLK_PLL_AUDIO_2X 3 178c2ecf20Sopenharmony_ci#define CLK_PLL_AUDIO_4X 4 188c2ecf20Sopenharmony_ci#define CLK_PLL_AUDIO_8X 5 198c2ecf20Sopenharmony_ci#define CLK_PLL_VIDEO 6 208c2ecf20Sopenharmony_ci#define CLK_PLL_VIDEO_2X 7 218c2ecf20Sopenharmony_ci#define CLK_PLL_VE 8 228c2ecf20Sopenharmony_ci#define CLK_PLL_DDR0 9 238c2ecf20Sopenharmony_ci#define CLK_PLL_PERIPH 10 248c2ecf20Sopenharmony_ci 258c2ecf20Sopenharmony_ci/* CPU clock is exported */ 268c2ecf20Sopenharmony_ci 278c2ecf20Sopenharmony_ci#define CLK_AHB 12 288c2ecf20Sopenharmony_ci#define CLK_APB 13 298c2ecf20Sopenharmony_ci 308c2ecf20Sopenharmony_ci/* All bus gates, DRAM gates and mod clocks are exported */ 318c2ecf20Sopenharmony_ci 328c2ecf20Sopenharmony_ci#define CLK_NUMBER (CLK_AVS + 1) 338c2ecf20Sopenharmony_ci 348c2ecf20Sopenharmony_ci#endif /* _CCU_SUNIV_F1C100S_H_ */ 35