18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0-or-later */ 28c2ecf20Sopenharmony_ci/* 38c2ecf20Sopenharmony_ci * Copyright (c) 2016 Icenowy Zheng <icenowy@aosc.xyz> 48c2ecf20Sopenharmony_ci * 58c2ecf20Sopenharmony_ci * Based on ccu-sun8i-h3.h, which is: 68c2ecf20Sopenharmony_ci * Copyright (c) 2016 Maxime Ripard <maxime.ripard@free-electrons.com> 78c2ecf20Sopenharmony_ci */ 88c2ecf20Sopenharmony_ci 98c2ecf20Sopenharmony_ci#ifndef _CCU_SUN8I_H3_H_ 108c2ecf20Sopenharmony_ci#define _CCU_SUN8I_H3_H_ 118c2ecf20Sopenharmony_ci 128c2ecf20Sopenharmony_ci#include <dt-bindings/clock/sun8i-v3s-ccu.h> 138c2ecf20Sopenharmony_ci#include <dt-bindings/reset/sun8i-v3s-ccu.h> 148c2ecf20Sopenharmony_ci 158c2ecf20Sopenharmony_ci#define CLK_PLL_CPU 0 168c2ecf20Sopenharmony_ci#define CLK_PLL_AUDIO_BASE 1 178c2ecf20Sopenharmony_ci#define CLK_PLL_AUDIO 2 188c2ecf20Sopenharmony_ci#define CLK_PLL_AUDIO_2X 3 198c2ecf20Sopenharmony_ci#define CLK_PLL_AUDIO_4X 4 208c2ecf20Sopenharmony_ci#define CLK_PLL_AUDIO_8X 5 218c2ecf20Sopenharmony_ci#define CLK_PLL_VIDEO 6 228c2ecf20Sopenharmony_ci#define CLK_PLL_VE 7 238c2ecf20Sopenharmony_ci#define CLK_PLL_DDR0 8 248c2ecf20Sopenharmony_ci#define CLK_PLL_PERIPH0 9 258c2ecf20Sopenharmony_ci#define CLK_PLL_PERIPH0_2X 10 268c2ecf20Sopenharmony_ci#define CLK_PLL_ISP 11 278c2ecf20Sopenharmony_ci#define CLK_PLL_PERIPH1 12 288c2ecf20Sopenharmony_ci/* Reserve one number for not implemented and not used PLL_DDR1 */ 298c2ecf20Sopenharmony_ci 308c2ecf20Sopenharmony_ci/* The CPU clock is exported */ 318c2ecf20Sopenharmony_ci 328c2ecf20Sopenharmony_ci#define CLK_AXI 15 338c2ecf20Sopenharmony_ci#define CLK_AHB1 16 348c2ecf20Sopenharmony_ci#define CLK_APB1 17 358c2ecf20Sopenharmony_ci#define CLK_APB2 18 368c2ecf20Sopenharmony_ci#define CLK_AHB2 19 378c2ecf20Sopenharmony_ci 388c2ecf20Sopenharmony_ci/* All the bus gates are exported */ 398c2ecf20Sopenharmony_ci 408c2ecf20Sopenharmony_ci/* The first bunch of module clocks are exported */ 418c2ecf20Sopenharmony_ci 428c2ecf20Sopenharmony_ci#define CLK_DRAM 58 438c2ecf20Sopenharmony_ci 448c2ecf20Sopenharmony_ci/* All the DRAM gates are exported */ 458c2ecf20Sopenharmony_ci 468c2ecf20Sopenharmony_ci/* Some more module clocks are exported */ 478c2ecf20Sopenharmony_ci 488c2ecf20Sopenharmony_ci#define CLK_MBUS 72 498c2ecf20Sopenharmony_ci 508c2ecf20Sopenharmony_ci/* And the GPU module clock is exported */ 518c2ecf20Sopenharmony_ci 528c2ecf20Sopenharmony_ci#define CLK_PLL_DDR1 74 538c2ecf20Sopenharmony_ci 548c2ecf20Sopenharmony_ci#endif /* _CCU_SUN8I_H3_H_ */ 55