1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2017 Icenowy Zheng <icenowy@aosc.io> 4 */ 5 6#include <linux/clk-provider.h> 7#include <linux/io.h> 8#include <linux/platform_device.h> 9#include <linux/regmap.h> 10 11#include "ccu_common.h" 12#include "ccu_reset.h" 13 14#include "ccu_div.h" 15#include "ccu_gate.h" 16#include "ccu_mp.h" 17#include "ccu_mult.h" 18#include "ccu_nk.h" 19#include "ccu_nkm.h" 20#include "ccu_nkmp.h" 21#include "ccu_nm.h" 22#include "ccu_phase.h" 23 24#include "ccu-sun8i-r40.h" 25 26/* TODO: The result of N*K is required to be in [10, 88] range. */ 27static struct ccu_nkmp pll_cpu_clk = { 28 .enable = BIT(31), 29 .lock = BIT(28), 30 .n = _SUNXI_CCU_MULT(8, 5), 31 .k = _SUNXI_CCU_MULT(4, 2), 32 .m = _SUNXI_CCU_DIV(0, 2), 33 .p = _SUNXI_CCU_DIV_MAX(16, 2, 4), 34 .common = { 35 .reg = 0x000, 36 .hw.init = CLK_HW_INIT("pll-cpu", 37 "osc24M", 38 &ccu_nkmp_ops, 39 CLK_SET_RATE_UNGATE), 40 }, 41}; 42 43/* 44 * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from 45 * the base (2x, 4x and 8x), and one variable divider (the one true 46 * pll audio). 47 * 48 * With sigma-delta modulation for fractional-N on the audio PLL, 49 * we have to use specific dividers. This means the variable divider 50 * can no longer be used, as the audio codec requests the exact clock 51 * rates we support through this mechanism. So we now hard code the 52 * variable divider to 1. This means the clock rates will no longer 53 * match the clock names. 54 */ 55#define SUN8I_R40_PLL_AUDIO_REG 0x008 56 57static struct ccu_sdm_setting pll_audio_sdm_table[] = { 58 { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 }, 59 { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 }, 60}; 61 62static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base", 63 "osc24M", 0x008, 64 8, 7, /* N */ 65 0, 5, /* M */ 66 pll_audio_sdm_table, BIT(24), 67 0x284, BIT(31), 68 BIT(31), /* gate */ 69 BIT(28), /* lock */ 70 CLK_SET_RATE_UNGATE); 71 72static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video0_clk, "pll-video0", 73 "osc24M", 0x0010, 74 192000000, /* Minimum rate */ 75 1008000000, /* Maximum rate */ 76 8, 7, /* N */ 77 0, 4, /* M */ 78 BIT(24), /* frac enable */ 79 BIT(25), /* frac select */ 80 270000000, /* frac rate 0 */ 81 297000000, /* frac rate 1 */ 82 BIT(31), /* gate */ 83 BIT(28), /* lock */ 84 CLK_SET_RATE_UNGATE); 85 86/* TODO: The result of N/M is required to be in [8, 25] range. */ 87static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve", 88 "osc24M", 0x0018, 89 8, 7, /* N */ 90 0, 4, /* M */ 91 BIT(24), /* frac enable */ 92 BIT(25), /* frac select */ 93 270000000, /* frac rate 0 */ 94 297000000, /* frac rate 1 */ 95 BIT(31), /* gate */ 96 BIT(28), /* lock */ 97 CLK_SET_RATE_UNGATE); 98 99/* TODO: The result of N*K is required to be in [10, 77] range. */ 100static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr0", 101 "osc24M", 0x020, 102 8, 5, /* N */ 103 4, 2, /* K */ 104 0, 2, /* M */ 105 BIT(31), /* gate */ 106 BIT(28), /* lock */ 107 CLK_SET_RATE_UNGATE); 108 109/* TODO: The result of N*K is required to be in [21, 58] range. */ 110static struct ccu_nk pll_periph0_clk = { 111 .enable = BIT(31), 112 .lock = BIT(28), 113 .n = _SUNXI_CCU_MULT(8, 5), 114 .k = _SUNXI_CCU_MULT(4, 2), 115 .fixed_post_div = 2, 116 .common = { 117 .reg = 0x028, 118 .features = CCU_FEATURE_FIXED_POSTDIV, 119 .hw.init = CLK_HW_INIT("pll-periph0", "osc24M", 120 &ccu_nk_ops, 121 CLK_SET_RATE_UNGATE), 122 }, 123}; 124 125static struct ccu_div pll_periph0_sata_clk = { 126 .enable = BIT(24), 127 .div = _SUNXI_CCU_DIV(0, 2), 128 /* 129 * The formula of pll-periph0 (1x) is 24MHz*N*K/2, and the formula 130 * of pll-periph0-sata is 24MHz*N*K/M/6, so the postdiv here is 131 * 6/2 = 3. 132 */ 133 .fixed_post_div = 3, 134 .common = { 135 .reg = 0x028, 136 .features = CCU_FEATURE_FIXED_POSTDIV, 137 .hw.init = CLK_HW_INIT("pll-periph0-sata", 138 "pll-periph0", 139 &ccu_div_ops, 0), 140 }, 141}; 142 143/* TODO: The result of N*K is required to be in [21, 58] range. */ 144static struct ccu_nk pll_periph1_clk = { 145 .enable = BIT(31), 146 .lock = BIT(28), 147 .n = _SUNXI_CCU_MULT(8, 5), 148 .k = _SUNXI_CCU_MULT(4, 2), 149 .fixed_post_div = 2, 150 .common = { 151 .reg = 0x02c, 152 .features = CCU_FEATURE_FIXED_POSTDIV, 153 .hw.init = CLK_HW_INIT("pll-periph1", "osc24M", 154 &ccu_nk_ops, 155 CLK_SET_RATE_UNGATE), 156 }, 157}; 158 159static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video1_clk, "pll-video1", 160 "osc24M", 0x030, 161 192000000, /* Minimum rate */ 162 1008000000, /* Maximum rate */ 163 8, 7, /* N */ 164 0, 4, /* M */ 165 BIT(24), /* frac enable */ 166 BIT(25), /* frac select */ 167 270000000, /* frac rate 0 */ 168 297000000, /* frac rate 1 */ 169 BIT(31), /* gate */ 170 BIT(28), /* lock */ 171 CLK_SET_RATE_UNGATE); 172 173static struct ccu_nkm pll_sata_clk = { 174 .enable = BIT(31), 175 .lock = BIT(28), 176 .n = _SUNXI_CCU_MULT(8, 5), 177 .k = _SUNXI_CCU_MULT(4, 2), 178 .m = _SUNXI_CCU_DIV(0, 2), 179 .fixed_post_div = 6, 180 .common = { 181 .reg = 0x034, 182 .features = CCU_FEATURE_FIXED_POSTDIV, 183 .hw.init = CLK_HW_INIT("pll-sata", "osc24M", 184 &ccu_nkm_ops, 185 CLK_SET_RATE_UNGATE), 186 }, 187}; 188 189static const char * const pll_sata_out_parents[] = { "pll-sata", 190 "pll-periph0-sata" }; 191static SUNXI_CCU_MUX_WITH_GATE(pll_sata_out_clk, "pll-sata-out", 192 pll_sata_out_parents, 0x034, 193 30, 1, /* mux */ 194 BIT(14), /* gate */ 195 CLK_SET_RATE_PARENT); 196 197/* TODO: The result of N/M is required to be in [8, 25] range. */ 198static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu", 199 "osc24M", 0x038, 200 8, 7, /* N */ 201 0, 4, /* M */ 202 BIT(24), /* frac enable */ 203 BIT(25), /* frac select */ 204 270000000, /* frac rate 0 */ 205 297000000, /* frac rate 1 */ 206 BIT(31), /* gate */ 207 BIT(28), /* lock */ 208 CLK_SET_RATE_UNGATE); 209 210/* 211 * The MIPI PLL has 2 modes: "MIPI" and "HDMI". 212 * 213 * The MIPI mode is a standard NKM-style clock. The HDMI mode is an 214 * integer / fractional clock with switchable multipliers and dividers. 215 * This is not supported here. We hardcode the PLL to MIPI mode. 216 * 217 * TODO: In the MIPI mode, M/N is required to be equal or lesser than 3, 218 * which cannot be implemented now. 219 */ 220#define SUN8I_R40_PLL_MIPI_REG 0x040 221 222static const char * const pll_mipi_parents[] = { "pll-video0" }; 223static struct ccu_nkm pll_mipi_clk = { 224 .enable = BIT(31) | BIT(23) | BIT(22), 225 .lock = BIT(28), 226 .n = _SUNXI_CCU_MULT(8, 4), 227 .k = _SUNXI_CCU_MULT_MIN(4, 2, 2), 228 .m = _SUNXI_CCU_DIV(0, 4), 229 .mux = _SUNXI_CCU_MUX(21, 1), 230 .common = { 231 .reg = 0x040, 232 .hw.init = CLK_HW_INIT_PARENTS("pll-mipi", 233 pll_mipi_parents, 234 &ccu_nkm_ops, 235 CLK_SET_RATE_UNGATE) 236 }, 237}; 238 239/* TODO: The result of N/M is required to be in [8, 25] range. */ 240static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de", 241 "osc24M", 0x048, 242 8, 7, /* N */ 243 0, 4, /* M */ 244 BIT(24), /* frac enable */ 245 BIT(25), /* frac select */ 246 270000000, /* frac rate 0 */ 247 297000000, /* frac rate 1 */ 248 BIT(31), /* gate */ 249 BIT(28), /* lock */ 250 CLK_SET_RATE_UNGATE); 251 252/* TODO: The N factor is required to be in [16, 75] range. */ 253static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_ddr1_clk, "pll-ddr1", 254 "osc24M", 0x04c, 255 8, 7, /* N */ 256 0, 2, /* M */ 257 BIT(31), /* gate */ 258 BIT(28), /* lock */ 259 CLK_SET_RATE_UNGATE); 260 261static const char * const cpu_parents[] = { "osc32k", "osc24M", 262 "pll-cpu", "pll-cpu" }; 263static SUNXI_CCU_MUX(cpu_clk, "cpu", cpu_parents, 264 0x050, 16, 2, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT); 265 266static SUNXI_CCU_M(axi_clk, "axi", "cpu", 0x050, 0, 2, 0); 267 268static const char * const ahb1_parents[] = { "osc32k", "osc24M", 269 "axi", "pll-periph0" }; 270static const struct ccu_mux_var_prediv ahb1_predivs[] = { 271 { .index = 3, .shift = 6, .width = 2 }, 272}; 273static struct ccu_div ahb1_clk = { 274 .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO), 275 276 .mux = { 277 .shift = 12, 278 .width = 2, 279 280 .var_predivs = ahb1_predivs, 281 .n_var_predivs = ARRAY_SIZE(ahb1_predivs), 282 }, 283 284 .common = { 285 .reg = 0x054, 286 .features = CCU_FEATURE_VARIABLE_PREDIV, 287 .hw.init = CLK_HW_INIT_PARENTS("ahb1", 288 ahb1_parents, 289 &ccu_div_ops, 290 0), 291 }, 292}; 293 294static struct clk_div_table apb1_div_table[] = { 295 { .val = 0, .div = 2 }, 296 { .val = 1, .div = 2 }, 297 { .val = 2, .div = 4 }, 298 { .val = 3, .div = 8 }, 299 { /* Sentinel */ }, 300}; 301static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1", 302 0x054, 8, 2, apb1_div_table, 0); 303 304static const char * const apb2_parents[] = { "osc32k", "osc24M", 305 "pll-periph0-2x", 306 "pll-periph0-2x" }; 307static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058, 308 0, 5, /* M */ 309 16, 2, /* P */ 310 24, 2, /* mux */ 311 0); 312 313static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb1", 314 0x060, BIT(1), 0); 315static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce", "ahb1", 316 0x060, BIT(5), 0); 317static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1", 318 0x060, BIT(6), 0); 319static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1", 320 0x060, BIT(8), 0); 321static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1", 322 0x060, BIT(9), 0); 323static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1", 324 0x060, BIT(10), 0); 325static SUNXI_CCU_GATE(bus_mmc3_clk, "bus-mmc3", "ahb1", 326 0x060, BIT(11), 0); 327static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb1", 328 0x060, BIT(13), 0); 329static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb1", 330 0x060, BIT(14), 0); 331static SUNXI_CCU_GATE(bus_emac_clk, "bus-emac", "ahb1", 332 0x060, BIT(17), 0); 333static SUNXI_CCU_GATE(bus_ts_clk, "bus-ts", "ahb1", 334 0x060, BIT(18), 0); 335static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1", 336 0x060, BIT(19), 0); 337static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb1", 338 0x060, BIT(20), 0); 339static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb1", 340 0x060, BIT(21), 0); 341static SUNXI_CCU_GATE(bus_spi2_clk, "bus-spi2", "ahb1", 342 0x060, BIT(22), 0); 343static SUNXI_CCU_GATE(bus_spi3_clk, "bus-spi3", "ahb1", 344 0x060, BIT(23), 0); 345static SUNXI_CCU_GATE(bus_sata_clk, "bus-sata", "ahb1", 346 0x060, BIT(24), 0); 347static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb1", 348 0x060, BIT(25), 0); 349static SUNXI_CCU_GATE(bus_ehci0_clk, "bus-ehci0", "ahb1", 350 0x060, BIT(26), 0); 351static SUNXI_CCU_GATE(bus_ehci1_clk, "bus-ehci1", "ahb1", 352 0x060, BIT(27), 0); 353static SUNXI_CCU_GATE(bus_ehci2_clk, "bus-ehci2", "ahb1", 354 0x060, BIT(28), 0); 355static SUNXI_CCU_GATE(bus_ohci0_clk, "bus-ohci0", "ahb1", 356 0x060, BIT(29), 0); 357static SUNXI_CCU_GATE(bus_ohci1_clk, "bus-ohci1", "ahb1", 358 0x060, BIT(30), 0); 359static SUNXI_CCU_GATE(bus_ohci2_clk, "bus-ohci2", "ahb1", 360 0x060, BIT(31), 0); 361 362static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb1", 363 0x064, BIT(0), 0); 364static SUNXI_CCU_GATE(bus_mp_clk, "bus-mp", "ahb1", 365 0x064, BIT(2), 0); 366static SUNXI_CCU_GATE(bus_deinterlace_clk, "bus-deinterlace", "ahb1", 367 0x064, BIT(5), 0); 368static SUNXI_CCU_GATE(bus_csi0_clk, "bus-csi0", "ahb1", 369 0x064, BIT(8), 0); 370static SUNXI_CCU_GATE(bus_csi1_clk, "bus-csi1", "ahb1", 371 0x064, BIT(9), 0); 372static SUNXI_CCU_GATE(bus_hdmi0_clk, "bus-hdmi0", "ahb1", 373 0x064, BIT(10), 0); 374static SUNXI_CCU_GATE(bus_hdmi1_clk, "bus-hdmi1", "ahb1", 375 0x064, BIT(11), 0); 376static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "ahb1", 377 0x064, BIT(12), 0); 378static SUNXI_CCU_GATE(bus_tve0_clk, "bus-tve0", "ahb1", 379 0x064, BIT(13), 0); 380static SUNXI_CCU_GATE(bus_tve1_clk, "bus-tve1", "ahb1", 381 0x064, BIT(14), 0); 382static SUNXI_CCU_GATE(bus_tve_top_clk, "bus-tve-top", "ahb1", 383 0x064, BIT(15), 0); 384static SUNXI_CCU_GATE(bus_gmac_clk, "bus-gmac", "ahb1", 385 0x064, BIT(17), 0); 386static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "ahb1", 387 0x064, BIT(20), 0); 388static SUNXI_CCU_GATE(bus_tvd0_clk, "bus-tvd0", "ahb1", 389 0x064, BIT(21), 0); 390static SUNXI_CCU_GATE(bus_tvd1_clk, "bus-tvd1", "ahb1", 391 0x064, BIT(22), 0); 392static SUNXI_CCU_GATE(bus_tvd2_clk, "bus-tvd2", "ahb1", 393 0x064, BIT(23), 0); 394static SUNXI_CCU_GATE(bus_tvd3_clk, "bus-tvd3", "ahb1", 395 0x064, BIT(24), 0); 396static SUNXI_CCU_GATE(bus_tvd_top_clk, "bus-tvd-top", "ahb1", 397 0x064, BIT(25), 0); 398static SUNXI_CCU_GATE(bus_tcon_lcd0_clk, "bus-tcon-lcd0", "ahb1", 399 0x064, BIT(26), 0); 400static SUNXI_CCU_GATE(bus_tcon_lcd1_clk, "bus-tcon-lcd1", "ahb1", 401 0x064, BIT(27), 0); 402static SUNXI_CCU_GATE(bus_tcon_tv0_clk, "bus-tcon-tv0", "ahb1", 403 0x064, BIT(28), 0); 404static SUNXI_CCU_GATE(bus_tcon_tv1_clk, "bus-tcon-tv1", "ahb1", 405 0x064, BIT(29), 0); 406static SUNXI_CCU_GATE(bus_tcon_top_clk, "bus-tcon-top", "ahb1", 407 0x064, BIT(30), 0); 408 409static SUNXI_CCU_GATE(bus_codec_clk, "bus-codec", "apb1", 410 0x068, BIT(0), 0); 411static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb1", 412 0x068, BIT(1), 0); 413static SUNXI_CCU_GATE(bus_ac97_clk, "bus-ac97", "apb1", 414 0x068, BIT(2), 0); 415static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb1", 416 0x068, BIT(5), 0); 417static SUNXI_CCU_GATE(bus_ir0_clk, "bus-ir0", "apb1", 418 0x068, BIT(6), 0); 419static SUNXI_CCU_GATE(bus_ir1_clk, "bus-ir1", "apb1", 420 0x068, BIT(7), 0); 421static SUNXI_CCU_GATE(bus_ths_clk, "bus-ths", "apb1", 422 0x068, BIT(8), 0); 423static SUNXI_CCU_GATE(bus_keypad_clk, "bus-keypad", "apb1", 424 0x068, BIT(10), 0); 425static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1", 426 0x068, BIT(12), 0); 427static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb1", 428 0x068, BIT(13), 0); 429static SUNXI_CCU_GATE(bus_i2s2_clk, "bus-i2s2", "apb1", 430 0x068, BIT(14), 0); 431 432static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2", 433 0x06c, BIT(0), 0); 434static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2", 435 0x06c, BIT(1), 0); 436static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2", 437 0x06c, BIT(2), 0); 438static SUNXI_CCU_GATE(bus_i2c3_clk, "bus-i2c3", "apb2", 439 0x06c, BIT(3), 0); 440/* 441 * In datasheet here's "Reserved", however the gate exists in BSP soucre 442 * code. 443 */ 444static SUNXI_CCU_GATE(bus_can_clk, "bus-can", "apb2", 445 0x06c, BIT(4), 0); 446static SUNXI_CCU_GATE(bus_scr_clk, "bus-scr", "apb2", 447 0x06c, BIT(5), 0); 448static SUNXI_CCU_GATE(bus_ps20_clk, "bus-ps20", "apb2", 449 0x06c, BIT(6), 0); 450static SUNXI_CCU_GATE(bus_ps21_clk, "bus-ps21", "apb2", 451 0x06c, BIT(7), 0); 452static SUNXI_CCU_GATE(bus_i2c4_clk, "bus-i2c4", "apb2", 453 0x06c, BIT(15), 0); 454static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2", 455 0x06c, BIT(16), 0); 456static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2", 457 0x06c, BIT(17), 0); 458static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2", 459 0x06c, BIT(18), 0); 460static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2", 461 0x06c, BIT(19), 0); 462static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb2", 463 0x06c, BIT(20), 0); 464static SUNXI_CCU_GATE(bus_uart5_clk, "bus-uart5", "apb2", 465 0x06c, BIT(21), 0); 466static SUNXI_CCU_GATE(bus_uart6_clk, "bus-uart6", "apb2", 467 0x06c, BIT(22), 0); 468static SUNXI_CCU_GATE(bus_uart7_clk, "bus-uart7", "apb2", 469 0x06c, BIT(23), 0); 470 471static SUNXI_CCU_GATE(bus_dbg_clk, "bus-dbg", "ahb1", 472 0x070, BIT(7), 0); 473 474static const char * const ths_parents[] = { "osc24M" }; 475static struct ccu_div ths_clk = { 476 .enable = BIT(31), 477 .div = _SUNXI_CCU_DIV_FLAGS(0, 2, CLK_DIVIDER_POWER_OF_TWO), 478 .mux = _SUNXI_CCU_MUX(24, 2), 479 .common = { 480 .reg = 0x074, 481 .hw.init = CLK_HW_INIT_PARENTS("ths", 482 ths_parents, 483 &ccu_div_ops, 484 0), 485 }, 486}; 487 488static const char * const mod0_default_parents[] = { "osc24M", "pll-periph0", 489 "pll-periph1" }; 490static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080, 491 0, 4, /* M */ 492 16, 2, /* P */ 493 24, 2, /* mux */ 494 BIT(31), /* gate */ 495 0); 496 497static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x088, 498 0, 4, /* M */ 499 16, 2, /* P */ 500 24, 2, /* mux */ 501 BIT(31), /* gate */ 502 0); 503 504static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x08c, 505 0, 4, /* M */ 506 16, 2, /* P */ 507 24, 2, /* mux */ 508 BIT(31), /* gate */ 509 0); 510 511static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents, 0x090, 512 0, 4, /* M */ 513 16, 2, /* P */ 514 24, 2, /* mux */ 515 BIT(31), /* gate */ 516 0); 517 518static SUNXI_CCU_MP_WITH_MUX_GATE(mmc3_clk, "mmc3", mod0_default_parents, 0x094, 519 0, 4, /* M */ 520 16, 2, /* P */ 521 24, 2, /* mux */ 522 BIT(31), /* gate */ 523 0); 524 525static const char * const ts_parents[] = { "osc24M", "pll-periph0", }; 526static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", ts_parents, 0x098, 527 0, 4, /* M */ 528 16, 2, /* P */ 529 24, 4, /* mux */ 530 BIT(31), /* gate */ 531 0); 532 533static const char * const ce_parents[] = { "osc24M", "pll-periph0-2x", 534 "pll-periph1-2x" }; 535static SUNXI_CCU_MP_WITH_MUX_GATE(ce_clk, "ce", ce_parents, 0x09c, 536 0, 4, /* M */ 537 16, 2, /* P */ 538 24, 2, /* mux */ 539 BIT(31), /* gate */ 540 0); 541 542static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0, 543 0, 4, /* M */ 544 16, 2, /* P */ 545 24, 2, /* mux */ 546 BIT(31), /* gate */ 547 0); 548 549static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4, 550 0, 4, /* M */ 551 16, 2, /* P */ 552 24, 2, /* mux */ 553 BIT(31), /* gate */ 554 0); 555 556static SUNXI_CCU_MP_WITH_MUX_GATE(spi2_clk, "spi2", mod0_default_parents, 0x0a8, 557 0, 4, /* M */ 558 16, 2, /* P */ 559 24, 2, /* mux */ 560 BIT(31), /* gate */ 561 0); 562 563static SUNXI_CCU_MP_WITH_MUX_GATE(spi3_clk, "spi3", mod0_default_parents, 0x0ac, 564 0, 4, /* M */ 565 16, 2, /* P */ 566 24, 2, /* mux */ 567 BIT(31), /* gate */ 568 0); 569 570static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x", 571 "pll-audio-2x", "pll-audio" }; 572static SUNXI_CCU_MUX_WITH_GATE(i2s0_clk, "i2s0", i2s_parents, 573 0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT); 574 575static SUNXI_CCU_MUX_WITH_GATE(i2s1_clk, "i2s1", i2s_parents, 576 0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT); 577 578static SUNXI_CCU_MUX_WITH_GATE(i2s2_clk, "i2s2", i2s_parents, 579 0x0b8, 16, 2, BIT(31), CLK_SET_RATE_PARENT); 580 581static SUNXI_CCU_MUX_WITH_GATE(ac97_clk, "ac97", i2s_parents, 582 0x0bc, 16, 2, BIT(31), CLK_SET_RATE_PARENT); 583 584static SUNXI_CCU_MUX_WITH_GATE(spdif_clk, "spdif", i2s_parents, 585 0x0c0, 16, 2, BIT(31), CLK_SET_RATE_PARENT); 586 587static const char * const keypad_parents[] = { "osc24M", "osc32k" }; 588static const u8 keypad_table[] = { 0, 2 }; 589static struct ccu_mp keypad_clk = { 590 .enable = BIT(31), 591 .m = _SUNXI_CCU_DIV(0, 5), 592 .p = _SUNXI_CCU_DIV(16, 2), 593 .mux = _SUNXI_CCU_MUX_TABLE(24, 2, keypad_table), 594 .common = { 595 .reg = 0x0c4, 596 .hw.init = CLK_HW_INIT_PARENTS("keypad", 597 keypad_parents, 598 &ccu_mp_ops, 599 0), 600 } 601}; 602 603static const char * const sata_parents[] = { "pll-sata-out", "sata-ext" }; 604static SUNXI_CCU_MUX_WITH_GATE(sata_clk, "sata", sata_parents, 605 0x0c8, 24, 1, BIT(31), CLK_SET_RATE_PARENT); 606 607/* 608 * There are 3 OHCI 12M clock source selection bits in this register. 609 * We will force them to 0 (12M divided from 48M). 610 */ 611#define SUN8I_R40_USB_CLK_REG 0x0cc 612 613static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M", 614 0x0cc, BIT(8), 0); 615static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M", 616 0x0cc, BIT(9), 0); 617static SUNXI_CCU_GATE(usb_phy2_clk, "usb-phy2", "osc24M", 618 0x0cc, BIT(10), 0); 619static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc12M", 620 0x0cc, BIT(16), 0); 621static SUNXI_CCU_GATE(usb_ohci1_clk, "usb-ohci1", "osc12M", 622 0x0cc, BIT(17), 0); 623static SUNXI_CCU_GATE(usb_ohci2_clk, "usb-ohci2", "osc12M", 624 0x0cc, BIT(18), 0); 625 626static const char * const ir_parents[] = { "osc24M", "pll-periph0", 627 "pll-periph1", "osc32k" }; 628static SUNXI_CCU_MP_WITH_MUX_GATE(ir0_clk, "ir0", ir_parents, 0x0d0, 629 0, 4, /* M */ 630 16, 2, /* P */ 631 24, 2, /* mux */ 632 BIT(31), /* gate */ 633 0); 634 635static SUNXI_CCU_MP_WITH_MUX_GATE(ir1_clk, "ir1", ir_parents, 0x0d4, 636 0, 4, /* M */ 637 16, 2, /* P */ 638 24, 2, /* mux */ 639 BIT(31), /* gate */ 640 0); 641 642static const char * const dram_parents[] = { "pll-ddr0", "pll-ddr1" }; 643static SUNXI_CCU_M_WITH_MUX(dram_clk, "dram", dram_parents, 644 0x0f4, 0, 2, 20, 2, CLK_IS_CRITICAL); 645 646static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "dram", 647 0x100, BIT(0), 0); 648static SUNXI_CCU_GATE(dram_csi0_clk, "dram-csi0", "dram", 649 0x100, BIT(1), 0); 650static SUNXI_CCU_GATE(dram_csi1_clk, "dram-csi1", "dram", 651 0x100, BIT(2), 0); 652static SUNXI_CCU_GATE(dram_ts_clk, "dram-ts", "dram", 653 0x100, BIT(3), 0); 654static SUNXI_CCU_GATE(dram_tvd_clk, "dram-tvd", "dram", 655 0x100, BIT(4), 0); 656static SUNXI_CCU_GATE(dram_mp_clk, "dram-mp", "dram", 657 0x100, BIT(5), 0); 658static SUNXI_CCU_GATE(dram_deinterlace_clk, "dram-deinterlace", "dram", 659 0x100, BIT(6), 0); 660 661static const char * const de_parents[] = { "pll-periph0-2x", "pll-de" }; 662static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents, 663 0x104, 0, 4, 24, 3, BIT(31), 664 CLK_SET_RATE_PARENT); 665static SUNXI_CCU_M_WITH_MUX_GATE(mp_clk, "mp", de_parents, 666 0x108, 0, 4, 24, 3, BIT(31), 0); 667 668static const char * const tcon_parents[] = { "pll-video0", "pll-video1", 669 "pll-video0-2x", "pll-video1-2x", 670 "pll-mipi" }; 671static SUNXI_CCU_MUX_WITH_GATE(tcon_lcd0_clk, "tcon-lcd0", tcon_parents, 672 0x110, 24, 3, BIT(31), CLK_SET_RATE_PARENT); 673static SUNXI_CCU_MUX_WITH_GATE(tcon_lcd1_clk, "tcon-lcd1", tcon_parents, 674 0x114, 24, 3, BIT(31), CLK_SET_RATE_PARENT); 675static SUNXI_CCU_M_WITH_MUX_GATE(tcon_tv0_clk, "tcon-tv0", tcon_parents, 676 0x118, 0, 4, 24, 3, BIT(31), 677 CLK_SET_RATE_PARENT); 678static SUNXI_CCU_M_WITH_MUX_GATE(tcon_tv1_clk, "tcon-tv1", tcon_parents, 679 0x11c, 0, 4, 24, 3, BIT(31), 680 CLK_SET_RATE_PARENT); 681 682static const char * const deinterlace_parents[] = { "pll-periph0", 683 "pll-periph1" }; 684static SUNXI_CCU_M_WITH_MUX_GATE(deinterlace_clk, "deinterlace", 685 deinterlace_parents, 0x124, 0, 4, 24, 3, 686 BIT(31), 0); 687 688static const char * const csi_mclk_parents[] = { "osc24M", "pll-video1", 689 "pll-periph1" }; 690static SUNXI_CCU_M_WITH_MUX_GATE(csi1_mclk_clk, "csi1-mclk", csi_mclk_parents, 691 0x130, 0, 5, 8, 3, BIT(15), 0); 692 693static const char * const csi_sclk_parents[] = { "pll-periph0", "pll-periph1" }; 694static SUNXI_CCU_M_WITH_MUX_GATE(csi_sclk_clk, "csi-sclk", csi_sclk_parents, 695 0x134, 16, 4, 24, 3, BIT(31), 0); 696 697static SUNXI_CCU_M_WITH_MUX_GATE(csi0_mclk_clk, "csi0-mclk", csi_mclk_parents, 698 0x134, 0, 5, 8, 3, BIT(15), 0); 699 700static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve", 701 0x13c, 16, 3, BIT(31), CLK_SET_RATE_PARENT); 702 703static SUNXI_CCU_GATE(codec_clk, "codec", "pll-audio", 704 0x140, BIT(31), CLK_SET_RATE_PARENT); 705static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M", 706 0x144, BIT(31), 0); 707 708static const char * const hdmi_parents[] = { "pll-video0", "pll-video1" }; 709static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents, 710 0x150, 0, 4, 24, 2, BIT(31), 711 CLK_SET_RATE_PARENT); 712 713static SUNXI_CCU_GATE(hdmi_slow_clk, "hdmi-slow", "osc24M", 714 0x154, BIT(31), 0); 715 716/* 717 * In the SoC's user manual, the P factor is mentioned, but not used in 718 * the frequency formula. 719 * 720 * Here the factor is included, according to the BSP kernel source, 721 * which contains the P factor of this clock. 722 */ 723static const char * const mbus_parents[] = { "osc24M", "pll-periph0-2x", 724 "pll-ddr0" }; 725static SUNXI_CCU_MP_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents, 0x15c, 726 0, 4, /* M */ 727 16, 2, /* P */ 728 24, 2, /* mux */ 729 BIT(31), /* gate */ 730 CLK_IS_CRITICAL); 731 732static const char * const dsi_dphy_parents[] = { "pll-video0", "pll-video1", 733 "pll-periph0" }; 734static SUNXI_CCU_M_WITH_MUX_GATE(dsi_dphy_clk, "dsi-dphy", dsi_dphy_parents, 735 0x168, 0, 4, 8, 2, BIT(15), 0); 736 737static SUNXI_CCU_M_WITH_MUX_GATE(tve0_clk, "tve0", tcon_parents, 738 0x180, 0, 4, 24, 3, BIT(31), 0); 739static SUNXI_CCU_M_WITH_MUX_GATE(tve1_clk, "tve1", tcon_parents, 740 0x184, 0, 4, 24, 3, BIT(31), 0); 741 742static const char * const tvd_parents[] = { "pll-video0", "pll-video1", 743 "pll-video0-2x", "pll-video1-2x" }; 744static SUNXI_CCU_M_WITH_MUX_GATE(tvd0_clk, "tvd0", tvd_parents, 745 0x188, 0, 4, 24, 3, BIT(31), 0); 746static SUNXI_CCU_M_WITH_MUX_GATE(tvd1_clk, "tvd1", tvd_parents, 747 0x18c, 0, 4, 24, 3, BIT(31), 0); 748static SUNXI_CCU_M_WITH_MUX_GATE(tvd2_clk, "tvd2", tvd_parents, 749 0x190, 0, 4, 24, 3, BIT(31), 0); 750static SUNXI_CCU_M_WITH_MUX_GATE(tvd3_clk, "tvd3", tvd_parents, 751 0x194, 0, 4, 24, 3, BIT(31), 0); 752 753static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu", 754 0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT); 755 756static const char * const out_parents[] = { "osc24M", "osc32k", "osc24M" }; 757static const struct ccu_mux_fixed_prediv out_predivs[] = { 758 { .index = 0, .div = 750, }, 759}; 760 761static struct ccu_mp outa_clk = { 762 .enable = BIT(31), 763 .m = _SUNXI_CCU_DIV(8, 5), 764 .p = _SUNXI_CCU_DIV(20, 2), 765 .mux = { 766 .shift = 24, 767 .width = 2, 768 .fixed_predivs = out_predivs, 769 .n_predivs = ARRAY_SIZE(out_predivs), 770 }, 771 .common = { 772 .reg = 0x1f0, 773 .features = CCU_FEATURE_FIXED_PREDIV, 774 .hw.init = CLK_HW_INIT_PARENTS("outa", out_parents, 775 &ccu_mp_ops, 776 CLK_SET_RATE_PARENT), 777 } 778}; 779 780static struct ccu_mp outb_clk = { 781 .enable = BIT(31), 782 .m = _SUNXI_CCU_DIV(8, 5), 783 .p = _SUNXI_CCU_DIV(20, 2), 784 .mux = { 785 .shift = 24, 786 .width = 2, 787 .fixed_predivs = out_predivs, 788 .n_predivs = ARRAY_SIZE(out_predivs), 789 }, 790 .common = { 791 .reg = 0x1f4, 792 .features = CCU_FEATURE_FIXED_PREDIV, 793 .hw.init = CLK_HW_INIT_PARENTS("outb", out_parents, 794 &ccu_mp_ops, 795 CLK_SET_RATE_PARENT), 796 } 797}; 798 799static struct ccu_common *sun8i_r40_ccu_clks[] = { 800 &pll_cpu_clk.common, 801 &pll_audio_base_clk.common, 802 &pll_video0_clk.common, 803 &pll_ve_clk.common, 804 &pll_ddr0_clk.common, 805 &pll_periph0_clk.common, 806 &pll_periph0_sata_clk.common, 807 &pll_periph1_clk.common, 808 &pll_video1_clk.common, 809 &pll_sata_clk.common, 810 &pll_sata_out_clk.common, 811 &pll_gpu_clk.common, 812 &pll_mipi_clk.common, 813 &pll_de_clk.common, 814 &pll_ddr1_clk.common, 815 &cpu_clk.common, 816 &axi_clk.common, 817 &ahb1_clk.common, 818 &apb1_clk.common, 819 &apb2_clk.common, 820 &bus_mipi_dsi_clk.common, 821 &bus_ce_clk.common, 822 &bus_dma_clk.common, 823 &bus_mmc0_clk.common, 824 &bus_mmc1_clk.common, 825 &bus_mmc2_clk.common, 826 &bus_mmc3_clk.common, 827 &bus_nand_clk.common, 828 &bus_dram_clk.common, 829 &bus_emac_clk.common, 830 &bus_ts_clk.common, 831 &bus_hstimer_clk.common, 832 &bus_spi0_clk.common, 833 &bus_spi1_clk.common, 834 &bus_spi2_clk.common, 835 &bus_spi3_clk.common, 836 &bus_sata_clk.common, 837 &bus_otg_clk.common, 838 &bus_ehci0_clk.common, 839 &bus_ehci1_clk.common, 840 &bus_ehci2_clk.common, 841 &bus_ohci0_clk.common, 842 &bus_ohci1_clk.common, 843 &bus_ohci2_clk.common, 844 &bus_ve_clk.common, 845 &bus_mp_clk.common, 846 &bus_deinterlace_clk.common, 847 &bus_csi0_clk.common, 848 &bus_csi1_clk.common, 849 &bus_hdmi0_clk.common, 850 &bus_hdmi1_clk.common, 851 &bus_de_clk.common, 852 &bus_tve0_clk.common, 853 &bus_tve1_clk.common, 854 &bus_tve_top_clk.common, 855 &bus_gmac_clk.common, 856 &bus_gpu_clk.common, 857 &bus_tvd0_clk.common, 858 &bus_tvd1_clk.common, 859 &bus_tvd2_clk.common, 860 &bus_tvd3_clk.common, 861 &bus_tvd_top_clk.common, 862 &bus_tcon_lcd0_clk.common, 863 &bus_tcon_lcd1_clk.common, 864 &bus_tcon_tv0_clk.common, 865 &bus_tcon_tv1_clk.common, 866 &bus_tcon_top_clk.common, 867 &bus_codec_clk.common, 868 &bus_spdif_clk.common, 869 &bus_ac97_clk.common, 870 &bus_pio_clk.common, 871 &bus_ir0_clk.common, 872 &bus_ir1_clk.common, 873 &bus_ths_clk.common, 874 &bus_keypad_clk.common, 875 &bus_i2s0_clk.common, 876 &bus_i2s1_clk.common, 877 &bus_i2s2_clk.common, 878 &bus_i2c0_clk.common, 879 &bus_i2c1_clk.common, 880 &bus_i2c2_clk.common, 881 &bus_i2c3_clk.common, 882 &bus_can_clk.common, 883 &bus_scr_clk.common, 884 &bus_ps20_clk.common, 885 &bus_ps21_clk.common, 886 &bus_i2c4_clk.common, 887 &bus_uart0_clk.common, 888 &bus_uart1_clk.common, 889 &bus_uart2_clk.common, 890 &bus_uart3_clk.common, 891 &bus_uart4_clk.common, 892 &bus_uart5_clk.common, 893 &bus_uart6_clk.common, 894 &bus_uart7_clk.common, 895 &bus_dbg_clk.common, 896 &ths_clk.common, 897 &nand_clk.common, 898 &mmc0_clk.common, 899 &mmc1_clk.common, 900 &mmc2_clk.common, 901 &mmc3_clk.common, 902 &ts_clk.common, 903 &ce_clk.common, 904 &spi0_clk.common, 905 &spi1_clk.common, 906 &spi2_clk.common, 907 &spi3_clk.common, 908 &i2s0_clk.common, 909 &i2s1_clk.common, 910 &i2s2_clk.common, 911 &ac97_clk.common, 912 &spdif_clk.common, 913 &keypad_clk.common, 914 &sata_clk.common, 915 &usb_phy0_clk.common, 916 &usb_phy1_clk.common, 917 &usb_phy2_clk.common, 918 &usb_ohci0_clk.common, 919 &usb_ohci1_clk.common, 920 &usb_ohci2_clk.common, 921 &ir0_clk.common, 922 &ir1_clk.common, 923 &dram_clk.common, 924 &dram_ve_clk.common, 925 &dram_csi0_clk.common, 926 &dram_csi1_clk.common, 927 &dram_ts_clk.common, 928 &dram_tvd_clk.common, 929 &dram_mp_clk.common, 930 &dram_deinterlace_clk.common, 931 &de_clk.common, 932 &mp_clk.common, 933 &tcon_lcd0_clk.common, 934 &tcon_lcd1_clk.common, 935 &tcon_tv0_clk.common, 936 &tcon_tv1_clk.common, 937 &deinterlace_clk.common, 938 &csi1_mclk_clk.common, 939 &csi_sclk_clk.common, 940 &csi0_mclk_clk.common, 941 &ve_clk.common, 942 &codec_clk.common, 943 &avs_clk.common, 944 &hdmi_clk.common, 945 &hdmi_slow_clk.common, 946 &mbus_clk.common, 947 &dsi_dphy_clk.common, 948 &tve0_clk.common, 949 &tve1_clk.common, 950 &tvd0_clk.common, 951 &tvd1_clk.common, 952 &tvd2_clk.common, 953 &tvd3_clk.common, 954 &gpu_clk.common, 955 &outa_clk.common, 956 &outb_clk.common, 957}; 958 959/* Fixed Factor clocks */ 960static CLK_FIXED_FACTOR_FW_NAME(osc12M_clk, "osc12M", "hosc", 2, 1, 0); 961 962static const struct clk_hw *clk_parent_pll_audio[] = { 963 &pll_audio_base_clk.common.hw 964}; 965 966/* We hardcode the divider to 1 for now */ 967static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio", 968 clk_parent_pll_audio, 969 1, 1, CLK_SET_RATE_PARENT); 970static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x", 971 clk_parent_pll_audio, 972 2, 1, CLK_SET_RATE_PARENT); 973static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x", 974 clk_parent_pll_audio, 975 1, 1, CLK_SET_RATE_PARENT); 976static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x", 977 clk_parent_pll_audio, 978 1, 2, CLK_SET_RATE_PARENT); 979static CLK_FIXED_FACTOR_HW(pll_periph0_2x_clk, "pll-periph0-2x", 980 &pll_periph0_clk.common.hw, 981 1, 2, 0); 982static CLK_FIXED_FACTOR_HW(pll_periph1_2x_clk, "pll-periph1-2x", 983 &pll_periph1_clk.common.hw, 984 1, 2, 0); 985static CLK_FIXED_FACTOR_HW(pll_video0_2x_clk, "pll-video0-2x", 986 &pll_video0_clk.common.hw, 987 1, 2, 0); 988static CLK_FIXED_FACTOR_HW(pll_video1_2x_clk, "pll-video1-2x", 989 &pll_video1_clk.common.hw, 990 1, 2, 0); 991 992static struct clk_hw_onecell_data sun8i_r40_hw_clks = { 993 .hws = { 994 [CLK_OSC_12M] = &osc12M_clk.hw, 995 [CLK_PLL_CPU] = &pll_cpu_clk.common.hw, 996 [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw, 997 [CLK_PLL_AUDIO] = &pll_audio_clk.hw, 998 [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw, 999 [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw, 1000 [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw, 1001 [CLK_PLL_VIDEO0] = &pll_video0_clk.common.hw, 1002 [CLK_PLL_VIDEO0_2X] = &pll_video0_2x_clk.hw, 1003 [CLK_PLL_VE] = &pll_ve_clk.common.hw, 1004 [CLK_PLL_DDR0] = &pll_ddr0_clk.common.hw, 1005 [CLK_PLL_PERIPH0] = &pll_periph0_clk.common.hw, 1006 [CLK_PLL_PERIPH0_SATA] = &pll_periph0_sata_clk.common.hw, 1007 [CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.hw, 1008 [CLK_PLL_PERIPH1] = &pll_periph1_clk.common.hw, 1009 [CLK_PLL_PERIPH1_2X] = &pll_periph1_2x_clk.hw, 1010 [CLK_PLL_VIDEO1] = &pll_video1_clk.common.hw, 1011 [CLK_PLL_VIDEO1_2X] = &pll_video1_2x_clk.hw, 1012 [CLK_PLL_SATA] = &pll_sata_clk.common.hw, 1013 [CLK_PLL_SATA_OUT] = &pll_sata_out_clk.common.hw, 1014 [CLK_PLL_GPU] = &pll_gpu_clk.common.hw, 1015 [CLK_PLL_MIPI] = &pll_mipi_clk.common.hw, 1016 [CLK_PLL_DE] = &pll_de_clk.common.hw, 1017 [CLK_PLL_DDR1] = &pll_ddr1_clk.common.hw, 1018 [CLK_CPU] = &cpu_clk.common.hw, 1019 [CLK_AXI] = &axi_clk.common.hw, 1020 [CLK_AHB1] = &ahb1_clk.common.hw, 1021 [CLK_APB1] = &apb1_clk.common.hw, 1022 [CLK_APB2] = &apb2_clk.common.hw, 1023 [CLK_BUS_MIPI_DSI] = &bus_mipi_dsi_clk.common.hw, 1024 [CLK_BUS_CE] = &bus_ce_clk.common.hw, 1025 [CLK_BUS_DMA] = &bus_dma_clk.common.hw, 1026 [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw, 1027 [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw, 1028 [CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw, 1029 [CLK_BUS_MMC3] = &bus_mmc3_clk.common.hw, 1030 [CLK_BUS_NAND] = &bus_nand_clk.common.hw, 1031 [CLK_BUS_DRAM] = &bus_dram_clk.common.hw, 1032 [CLK_BUS_EMAC] = &bus_emac_clk.common.hw, 1033 [CLK_BUS_TS] = &bus_ts_clk.common.hw, 1034 [CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw, 1035 [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw, 1036 [CLK_BUS_SPI1] = &bus_spi1_clk.common.hw, 1037 [CLK_BUS_SPI2] = &bus_spi2_clk.common.hw, 1038 [CLK_BUS_SPI3] = &bus_spi3_clk.common.hw, 1039 [CLK_BUS_SATA] = &bus_sata_clk.common.hw, 1040 [CLK_BUS_OTG] = &bus_otg_clk.common.hw, 1041 [CLK_BUS_EHCI0] = &bus_ehci0_clk.common.hw, 1042 [CLK_BUS_EHCI1] = &bus_ehci1_clk.common.hw, 1043 [CLK_BUS_EHCI2] = &bus_ehci2_clk.common.hw, 1044 [CLK_BUS_OHCI0] = &bus_ohci0_clk.common.hw, 1045 [CLK_BUS_OHCI1] = &bus_ohci1_clk.common.hw, 1046 [CLK_BUS_OHCI2] = &bus_ohci2_clk.common.hw, 1047 [CLK_BUS_VE] = &bus_ve_clk.common.hw, 1048 [CLK_BUS_MP] = &bus_mp_clk.common.hw, 1049 [CLK_BUS_DEINTERLACE] = &bus_deinterlace_clk.common.hw, 1050 [CLK_BUS_CSI0] = &bus_csi0_clk.common.hw, 1051 [CLK_BUS_CSI1] = &bus_csi1_clk.common.hw, 1052 [CLK_BUS_HDMI0] = &bus_hdmi0_clk.common.hw, 1053 [CLK_BUS_HDMI1] = &bus_hdmi1_clk.common.hw, 1054 [CLK_BUS_DE] = &bus_de_clk.common.hw, 1055 [CLK_BUS_TVE0] = &bus_tve0_clk.common.hw, 1056 [CLK_BUS_TVE1] = &bus_tve1_clk.common.hw, 1057 [CLK_BUS_TVE_TOP] = &bus_tve_top_clk.common.hw, 1058 [CLK_BUS_GMAC] = &bus_gmac_clk.common.hw, 1059 [CLK_BUS_GPU] = &bus_gpu_clk.common.hw, 1060 [CLK_BUS_TVD0] = &bus_tvd0_clk.common.hw, 1061 [CLK_BUS_TVD1] = &bus_tvd1_clk.common.hw, 1062 [CLK_BUS_TVD2] = &bus_tvd2_clk.common.hw, 1063 [CLK_BUS_TVD3] = &bus_tvd3_clk.common.hw, 1064 [CLK_BUS_TVD_TOP] = &bus_tvd_top_clk.common.hw, 1065 [CLK_BUS_TCON_LCD0] = &bus_tcon_lcd0_clk.common.hw, 1066 [CLK_BUS_TCON_LCD1] = &bus_tcon_lcd1_clk.common.hw, 1067 [CLK_BUS_TCON_TV0] = &bus_tcon_tv0_clk.common.hw, 1068 [CLK_BUS_TCON_TV1] = &bus_tcon_tv1_clk.common.hw, 1069 [CLK_BUS_TCON_TOP] = &bus_tcon_top_clk.common.hw, 1070 [CLK_BUS_CODEC] = &bus_codec_clk.common.hw, 1071 [CLK_BUS_SPDIF] = &bus_spdif_clk.common.hw, 1072 [CLK_BUS_AC97] = &bus_ac97_clk.common.hw, 1073 [CLK_BUS_PIO] = &bus_pio_clk.common.hw, 1074 [CLK_BUS_IR0] = &bus_ir0_clk.common.hw, 1075 [CLK_BUS_IR1] = &bus_ir1_clk.common.hw, 1076 [CLK_BUS_THS] = &bus_ths_clk.common.hw, 1077 [CLK_BUS_KEYPAD] = &bus_keypad_clk.common.hw, 1078 [CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw, 1079 [CLK_BUS_I2S1] = &bus_i2s1_clk.common.hw, 1080 [CLK_BUS_I2S2] = &bus_i2s2_clk.common.hw, 1081 [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw, 1082 [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw, 1083 [CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw, 1084 [CLK_BUS_I2C3] = &bus_i2c3_clk.common.hw, 1085 [CLK_BUS_CAN] = &bus_can_clk.common.hw, 1086 [CLK_BUS_SCR] = &bus_scr_clk.common.hw, 1087 [CLK_BUS_PS20] = &bus_ps20_clk.common.hw, 1088 [CLK_BUS_PS21] = &bus_ps21_clk.common.hw, 1089 [CLK_BUS_I2C4] = &bus_i2c4_clk.common.hw, 1090 [CLK_BUS_UART0] = &bus_uart0_clk.common.hw, 1091 [CLK_BUS_UART1] = &bus_uart1_clk.common.hw, 1092 [CLK_BUS_UART2] = &bus_uart2_clk.common.hw, 1093 [CLK_BUS_UART3] = &bus_uart3_clk.common.hw, 1094 [CLK_BUS_UART4] = &bus_uart4_clk.common.hw, 1095 [CLK_BUS_UART5] = &bus_uart5_clk.common.hw, 1096 [CLK_BUS_UART6] = &bus_uart6_clk.common.hw, 1097 [CLK_BUS_UART7] = &bus_uart7_clk.common.hw, 1098 [CLK_BUS_DBG] = &bus_dbg_clk.common.hw, 1099 [CLK_THS] = &ths_clk.common.hw, 1100 [CLK_NAND] = &nand_clk.common.hw, 1101 [CLK_MMC0] = &mmc0_clk.common.hw, 1102 [CLK_MMC1] = &mmc1_clk.common.hw, 1103 [CLK_MMC2] = &mmc2_clk.common.hw, 1104 [CLK_MMC3] = &mmc3_clk.common.hw, 1105 [CLK_TS] = &ts_clk.common.hw, 1106 [CLK_CE] = &ce_clk.common.hw, 1107 [CLK_SPI0] = &spi0_clk.common.hw, 1108 [CLK_SPI1] = &spi1_clk.common.hw, 1109 [CLK_SPI2] = &spi2_clk.common.hw, 1110 [CLK_SPI3] = &spi3_clk.common.hw, 1111 [CLK_I2S0] = &i2s0_clk.common.hw, 1112 [CLK_I2S1] = &i2s1_clk.common.hw, 1113 [CLK_I2S2] = &i2s2_clk.common.hw, 1114 [CLK_AC97] = &ac97_clk.common.hw, 1115 [CLK_SPDIF] = &spdif_clk.common.hw, 1116 [CLK_KEYPAD] = &keypad_clk.common.hw, 1117 [CLK_SATA] = &sata_clk.common.hw, 1118 [CLK_USB_PHY0] = &usb_phy0_clk.common.hw, 1119 [CLK_USB_PHY1] = &usb_phy1_clk.common.hw, 1120 [CLK_USB_PHY2] = &usb_phy2_clk.common.hw, 1121 [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw, 1122 [CLK_USB_OHCI1] = &usb_ohci1_clk.common.hw, 1123 [CLK_USB_OHCI2] = &usb_ohci2_clk.common.hw, 1124 [CLK_IR0] = &ir0_clk.common.hw, 1125 [CLK_IR1] = &ir1_clk.common.hw, 1126 [CLK_DRAM] = &dram_clk.common.hw, 1127 [CLK_DRAM_VE] = &dram_ve_clk.common.hw, 1128 [CLK_DRAM_CSI0] = &dram_csi0_clk.common.hw, 1129 [CLK_DRAM_CSI1] = &dram_csi1_clk.common.hw, 1130 [CLK_DRAM_TS] = &dram_ts_clk.common.hw, 1131 [CLK_DRAM_TVD] = &dram_tvd_clk.common.hw, 1132 [CLK_DRAM_MP] = &dram_mp_clk.common.hw, 1133 [CLK_DRAM_DEINTERLACE] = &dram_deinterlace_clk.common.hw, 1134 [CLK_DE] = &de_clk.common.hw, 1135 [CLK_MP] = &mp_clk.common.hw, 1136 [CLK_TCON_LCD0] = &tcon_lcd0_clk.common.hw, 1137 [CLK_TCON_LCD1] = &tcon_lcd1_clk.common.hw, 1138 [CLK_TCON_TV0] = &tcon_tv0_clk.common.hw, 1139 [CLK_TCON_TV1] = &tcon_tv1_clk.common.hw, 1140 [CLK_DEINTERLACE] = &deinterlace_clk.common.hw, 1141 [CLK_CSI1_MCLK] = &csi1_mclk_clk.common.hw, 1142 [CLK_CSI_SCLK] = &csi_sclk_clk.common.hw, 1143 [CLK_CSI0_MCLK] = &csi0_mclk_clk.common.hw, 1144 [CLK_VE] = &ve_clk.common.hw, 1145 [CLK_CODEC] = &codec_clk.common.hw, 1146 [CLK_AVS] = &avs_clk.common.hw, 1147 [CLK_HDMI] = &hdmi_clk.common.hw, 1148 [CLK_HDMI_SLOW] = &hdmi_slow_clk.common.hw, 1149 [CLK_MBUS] = &mbus_clk.common.hw, 1150 [CLK_DSI_DPHY] = &dsi_dphy_clk.common.hw, 1151 [CLK_TVE0] = &tve0_clk.common.hw, 1152 [CLK_TVE1] = &tve1_clk.common.hw, 1153 [CLK_TVD0] = &tvd0_clk.common.hw, 1154 [CLK_TVD1] = &tvd1_clk.common.hw, 1155 [CLK_TVD2] = &tvd2_clk.common.hw, 1156 [CLK_TVD3] = &tvd3_clk.common.hw, 1157 [CLK_GPU] = &gpu_clk.common.hw, 1158 [CLK_OUTA] = &outa_clk.common.hw, 1159 [CLK_OUTB] = &outb_clk.common.hw, 1160 }, 1161 .num = CLK_NUMBER, 1162}; 1163 1164static struct ccu_reset_map sun8i_r40_ccu_resets[] = { 1165 [RST_USB_PHY0] = { 0x0cc, BIT(0) }, 1166 [RST_USB_PHY1] = { 0x0cc, BIT(1) }, 1167 [RST_USB_PHY2] = { 0x0cc, BIT(2) }, 1168 1169 [RST_DRAM] = { 0x0f4, BIT(31) }, 1170 [RST_MBUS] = { 0x0fc, BIT(31) }, 1171 1172 [RST_BUS_MIPI_DSI] = { 0x2c0, BIT(1) }, 1173 [RST_BUS_CE] = { 0x2c0, BIT(5) }, 1174 [RST_BUS_DMA] = { 0x2c0, BIT(6) }, 1175 [RST_BUS_MMC0] = { 0x2c0, BIT(8) }, 1176 [RST_BUS_MMC1] = { 0x2c0, BIT(9) }, 1177 [RST_BUS_MMC2] = { 0x2c0, BIT(10) }, 1178 [RST_BUS_MMC3] = { 0x2c0, BIT(11) }, 1179 [RST_BUS_NAND] = { 0x2c0, BIT(13) }, 1180 [RST_BUS_DRAM] = { 0x2c0, BIT(14) }, 1181 [RST_BUS_EMAC] = { 0x2c0, BIT(17) }, 1182 [RST_BUS_TS] = { 0x2c0, BIT(18) }, 1183 [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) }, 1184 [RST_BUS_SPI0] = { 0x2c0, BIT(20) }, 1185 [RST_BUS_SPI1] = { 0x2c0, BIT(21) }, 1186 [RST_BUS_SPI2] = { 0x2c0, BIT(22) }, 1187 [RST_BUS_SPI3] = { 0x2c0, BIT(23) }, 1188 [RST_BUS_SATA] = { 0x2c0, BIT(24) }, 1189 [RST_BUS_OTG] = { 0x2c0, BIT(25) }, 1190 [RST_BUS_EHCI0] = { 0x2c0, BIT(26) }, 1191 [RST_BUS_EHCI1] = { 0x2c0, BIT(27) }, 1192 [RST_BUS_EHCI2] = { 0x2c0, BIT(28) }, 1193 [RST_BUS_OHCI0] = { 0x2c0, BIT(29) }, 1194 [RST_BUS_OHCI1] = { 0x2c0, BIT(30) }, 1195 [RST_BUS_OHCI2] = { 0x2c0, BIT(31) }, 1196 1197 [RST_BUS_VE] = { 0x2c4, BIT(0) }, 1198 [RST_BUS_MP] = { 0x2c4, BIT(2) }, 1199 [RST_BUS_DEINTERLACE] = { 0x2c4, BIT(5) }, 1200 [RST_BUS_CSI0] = { 0x2c4, BIT(8) }, 1201 [RST_BUS_CSI1] = { 0x2c4, BIT(9) }, 1202 [RST_BUS_HDMI0] = { 0x2c4, BIT(10) }, 1203 [RST_BUS_HDMI1] = { 0x2c4, BIT(11) }, 1204 [RST_BUS_DE] = { 0x2c4, BIT(12) }, 1205 [RST_BUS_TVE0] = { 0x2c4, BIT(13) }, 1206 [RST_BUS_TVE1] = { 0x2c4, BIT(14) }, 1207 [RST_BUS_TVE_TOP] = { 0x2c4, BIT(15) }, 1208 [RST_BUS_GMAC] = { 0x2c4, BIT(17) }, 1209 [RST_BUS_GPU] = { 0x2c4, BIT(20) }, 1210 [RST_BUS_TVD0] = { 0x2c4, BIT(21) }, 1211 [RST_BUS_TVD1] = { 0x2c4, BIT(22) }, 1212 [RST_BUS_TVD2] = { 0x2c4, BIT(23) }, 1213 [RST_BUS_TVD3] = { 0x2c4, BIT(24) }, 1214 [RST_BUS_TVD_TOP] = { 0x2c4, BIT(25) }, 1215 [RST_BUS_TCON_LCD0] = { 0x2c4, BIT(26) }, 1216 [RST_BUS_TCON_LCD1] = { 0x2c4, BIT(27) }, 1217 [RST_BUS_TCON_TV0] = { 0x2c4, BIT(28) }, 1218 [RST_BUS_TCON_TV1] = { 0x2c4, BIT(29) }, 1219 [RST_BUS_TCON_TOP] = { 0x2c4, BIT(30) }, 1220 [RST_BUS_DBG] = { 0x2c4, BIT(31) }, 1221 1222 [RST_BUS_LVDS] = { 0x2c8, BIT(0) }, 1223 1224 [RST_BUS_CODEC] = { 0x2d0, BIT(0) }, 1225 [RST_BUS_SPDIF] = { 0x2d0, BIT(1) }, 1226 [RST_BUS_AC97] = { 0x2d0, BIT(2) }, 1227 [RST_BUS_IR0] = { 0x2d0, BIT(6) }, 1228 [RST_BUS_IR1] = { 0x2d0, BIT(7) }, 1229 [RST_BUS_THS] = { 0x2d0, BIT(8) }, 1230 [RST_BUS_KEYPAD] = { 0x2d0, BIT(10) }, 1231 [RST_BUS_I2S0] = { 0x2d0, BIT(12) }, 1232 [RST_BUS_I2S1] = { 0x2d0, BIT(13) }, 1233 [RST_BUS_I2S2] = { 0x2d0, BIT(14) }, 1234 1235 [RST_BUS_I2C0] = { 0x2d8, BIT(0) }, 1236 [RST_BUS_I2C1] = { 0x2d8, BIT(1) }, 1237 [RST_BUS_I2C2] = { 0x2d8, BIT(2) }, 1238 [RST_BUS_I2C3] = { 0x2d8, BIT(3) }, 1239 [RST_BUS_CAN] = { 0x2d8, BIT(4) }, 1240 [RST_BUS_SCR] = { 0x2d8, BIT(5) }, 1241 [RST_BUS_PS20] = { 0x2d8, BIT(6) }, 1242 [RST_BUS_PS21] = { 0x2d8, BIT(7) }, 1243 [RST_BUS_I2C4] = { 0x2d8, BIT(15) }, 1244 [RST_BUS_UART0] = { 0x2d8, BIT(16) }, 1245 [RST_BUS_UART1] = { 0x2d8, BIT(17) }, 1246 [RST_BUS_UART2] = { 0x2d8, BIT(18) }, 1247 [RST_BUS_UART3] = { 0x2d8, BIT(19) }, 1248 [RST_BUS_UART4] = { 0x2d8, BIT(20) }, 1249 [RST_BUS_UART5] = { 0x2d8, BIT(21) }, 1250 [RST_BUS_UART6] = { 0x2d8, BIT(22) }, 1251 [RST_BUS_UART7] = { 0x2d8, BIT(23) }, 1252}; 1253 1254static const struct sunxi_ccu_desc sun8i_r40_ccu_desc = { 1255 .ccu_clks = sun8i_r40_ccu_clks, 1256 .num_ccu_clks = ARRAY_SIZE(sun8i_r40_ccu_clks), 1257 1258 .hw_clks = &sun8i_r40_hw_clks, 1259 1260 .resets = sun8i_r40_ccu_resets, 1261 .num_resets = ARRAY_SIZE(sun8i_r40_ccu_resets), 1262}; 1263 1264static struct ccu_pll_nb sun8i_r40_pll_cpu_nb = { 1265 .common = &pll_cpu_clk.common, 1266 /* copy from pll_cpu_clk */ 1267 .enable = BIT(31), 1268 .lock = BIT(28), 1269}; 1270 1271static struct ccu_mux_nb sun8i_r40_cpu_nb = { 1272 .common = &cpu_clk.common, 1273 .cm = &cpu_clk.mux, 1274 .delay_us = 1, /* > 8 clock cycles at 24 MHz */ 1275 .bypass_index = 1, /* index of 24 MHz oscillator */ 1276}; 1277 1278/* 1279 * Add a regmap for the GMAC driver (dwmac-sun8i) to access the 1280 * GMAC configuration register. 1281 * Only this register is allowed to be written, in order to 1282 * prevent overriding critical clock configuration. 1283 */ 1284 1285#define SUN8I_R40_GMAC_CFG_REG 0x164 1286static bool sun8i_r40_ccu_regmap_accessible_reg(struct device *dev, 1287 unsigned int reg) 1288{ 1289 if (reg == SUN8I_R40_GMAC_CFG_REG) 1290 return true; 1291 return false; 1292} 1293 1294static struct regmap_config sun8i_r40_ccu_regmap_config = { 1295 .reg_bits = 32, 1296 .val_bits = 32, 1297 .reg_stride = 4, 1298 .max_register = 0x320, /* PLL_LOCK_CTRL_REG */ 1299 1300 /* other devices have no business accessing other registers */ 1301 .readable_reg = sun8i_r40_ccu_regmap_accessible_reg, 1302 .writeable_reg = sun8i_r40_ccu_regmap_accessible_reg, 1303}; 1304 1305#define SUN8I_R40_SYS_32K_CLK_REG 0x310 1306#define SUN8I_R40_SYS_32K_CLK_KEY (0x16AA << 16) 1307 1308static int sun8i_r40_ccu_probe(struct platform_device *pdev) 1309{ 1310 struct resource *res; 1311 struct regmap *regmap; 1312 void __iomem *reg; 1313 u32 val; 1314 int ret; 1315 1316 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1317 reg = devm_ioremap_resource(&pdev->dev, res); 1318 if (IS_ERR(reg)) 1319 return PTR_ERR(reg); 1320 1321 /* Force the PLL-Audio-1x divider to 1 */ 1322 val = readl(reg + SUN8I_R40_PLL_AUDIO_REG); 1323 val &= ~GENMASK(19, 16); 1324 writel(val | (0 << 16), reg + SUN8I_R40_PLL_AUDIO_REG); 1325 1326 /* Force PLL-MIPI to MIPI mode */ 1327 val = readl(reg + SUN8I_R40_PLL_MIPI_REG); 1328 val &= ~BIT(16); 1329 writel(val, reg + SUN8I_R40_PLL_MIPI_REG); 1330 1331 /* Force OHCI 12M parent to 12M divided from 48M */ 1332 val = readl(reg + SUN8I_R40_USB_CLK_REG); 1333 val &= ~GENMASK(25, 20); 1334 writel(val, reg + SUN8I_R40_USB_CLK_REG); 1335 1336 /* 1337 * Force SYS 32k (otherwise known as LOSC throughout the CCU) 1338 * clock parent to LOSC output from RTC module instead of the 1339 * CCU's internal RC oscillator divided output. 1340 */ 1341 writel(SUN8I_R40_SYS_32K_CLK_KEY | BIT(8), 1342 reg + SUN8I_R40_SYS_32K_CLK_REG); 1343 1344 regmap = devm_regmap_init_mmio(&pdev->dev, reg, 1345 &sun8i_r40_ccu_regmap_config); 1346 if (IS_ERR(regmap)) 1347 return PTR_ERR(regmap); 1348 1349 ret = sunxi_ccu_probe(pdev->dev.of_node, reg, &sun8i_r40_ccu_desc); 1350 if (ret) 1351 return ret; 1352 1353 /* Gate then ungate PLL CPU after any rate changes */ 1354 ccu_pll_notifier_register(&sun8i_r40_pll_cpu_nb); 1355 1356 /* Reparent CPU during PLL CPU rate changes */ 1357 ccu_mux_notifier_register(pll_cpu_clk.common.hw.clk, 1358 &sun8i_r40_cpu_nb); 1359 1360 return 0; 1361} 1362 1363static const struct of_device_id sun8i_r40_ccu_ids[] = { 1364 { .compatible = "allwinner,sun8i-r40-ccu" }, 1365 { } 1366}; 1367 1368static struct platform_driver sun8i_r40_ccu_driver = { 1369 .probe = sun8i_r40_ccu_probe, 1370 .driver = { 1371 .name = "sun8i-r40-ccu", 1372 .of_match_table = sun8i_r40_ccu_ids, 1373 }, 1374}; 1375builtin_platform_driver(sun8i_r40_ccu_driver); 1376