1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * Copyright 2016 Maxime Ripard
4 *
5 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 */
7
8#ifndef _CCU_SUN8I_H3_H_
9#define _CCU_SUN8I_H3_H_
10
11#include <dt-bindings/clock/sun8i-h3-ccu.h>
12#include <dt-bindings/reset/sun8i-h3-ccu.h>
13
14#define CLK_PLL_CPUX		0
15#define CLK_PLL_AUDIO_BASE	1
16#define CLK_PLL_AUDIO		2
17#define CLK_PLL_AUDIO_2X	3
18#define CLK_PLL_AUDIO_4X	4
19#define CLK_PLL_AUDIO_8X	5
20
21/* PLL_VIDEO is exported */
22
23#define CLK_PLL_VE		7
24#define CLK_PLL_DDR		8
25
26/* PLL_PERIPH0 exported for PRCM */
27
28#define CLK_PLL_PERIPH0_2X	10
29#define CLK_PLL_GPU		11
30#define CLK_PLL_PERIPH1		12
31#define CLK_PLL_DE		13
32
33/* The CPUX clock is exported */
34
35#define CLK_AXI			15
36#define CLK_AHB1		16
37#define CLK_APB1		17
38#define CLK_APB2		18
39#define CLK_AHB2		19
40
41/* All the bus gates are exported */
42
43/* The first bunch of module clocks are exported */
44
45#define CLK_DRAM		96
46
47/* All the DRAM gates are exported */
48
49/* Some more module clocks are exported */
50
51#define CLK_NUMBER_H3		(CLK_GPU + 1)
52#define CLK_NUMBER_H5		(CLK_BUS_SCR1 + 1)
53
54#endif /* _CCU_SUN8I_H3_H_ */
55