18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0-or-later */ 28c2ecf20Sopenharmony_ci/* 38c2ecf20Sopenharmony_ci * Copyright 2016 Maxime Ripard 48c2ecf20Sopenharmony_ci * 58c2ecf20Sopenharmony_ci * Maxime Ripard <maxime.ripard@free-electrons.com> 68c2ecf20Sopenharmony_ci */ 78c2ecf20Sopenharmony_ci 88c2ecf20Sopenharmony_ci#ifndef _CCU_SUN8I_H3_H_ 98c2ecf20Sopenharmony_ci#define _CCU_SUN8I_H3_H_ 108c2ecf20Sopenharmony_ci 118c2ecf20Sopenharmony_ci#include <dt-bindings/clock/sun8i-h3-ccu.h> 128c2ecf20Sopenharmony_ci#include <dt-bindings/reset/sun8i-h3-ccu.h> 138c2ecf20Sopenharmony_ci 148c2ecf20Sopenharmony_ci#define CLK_PLL_CPUX 0 158c2ecf20Sopenharmony_ci#define CLK_PLL_AUDIO_BASE 1 168c2ecf20Sopenharmony_ci#define CLK_PLL_AUDIO 2 178c2ecf20Sopenharmony_ci#define CLK_PLL_AUDIO_2X 3 188c2ecf20Sopenharmony_ci#define CLK_PLL_AUDIO_4X 4 198c2ecf20Sopenharmony_ci#define CLK_PLL_AUDIO_8X 5 208c2ecf20Sopenharmony_ci 218c2ecf20Sopenharmony_ci/* PLL_VIDEO is exported */ 228c2ecf20Sopenharmony_ci 238c2ecf20Sopenharmony_ci#define CLK_PLL_VE 7 248c2ecf20Sopenharmony_ci#define CLK_PLL_DDR 8 258c2ecf20Sopenharmony_ci 268c2ecf20Sopenharmony_ci/* PLL_PERIPH0 exported for PRCM */ 278c2ecf20Sopenharmony_ci 288c2ecf20Sopenharmony_ci#define CLK_PLL_PERIPH0_2X 10 298c2ecf20Sopenharmony_ci#define CLK_PLL_GPU 11 308c2ecf20Sopenharmony_ci#define CLK_PLL_PERIPH1 12 318c2ecf20Sopenharmony_ci#define CLK_PLL_DE 13 328c2ecf20Sopenharmony_ci 338c2ecf20Sopenharmony_ci/* The CPUX clock is exported */ 348c2ecf20Sopenharmony_ci 358c2ecf20Sopenharmony_ci#define CLK_AXI 15 368c2ecf20Sopenharmony_ci#define CLK_AHB1 16 378c2ecf20Sopenharmony_ci#define CLK_APB1 17 388c2ecf20Sopenharmony_ci#define CLK_APB2 18 398c2ecf20Sopenharmony_ci#define CLK_AHB2 19 408c2ecf20Sopenharmony_ci 418c2ecf20Sopenharmony_ci/* All the bus gates are exported */ 428c2ecf20Sopenharmony_ci 438c2ecf20Sopenharmony_ci/* The first bunch of module clocks are exported */ 448c2ecf20Sopenharmony_ci 458c2ecf20Sopenharmony_ci#define CLK_DRAM 96 468c2ecf20Sopenharmony_ci 478c2ecf20Sopenharmony_ci/* All the DRAM gates are exported */ 488c2ecf20Sopenharmony_ci 498c2ecf20Sopenharmony_ci/* Some more module clocks are exported */ 508c2ecf20Sopenharmony_ci 518c2ecf20Sopenharmony_ci#define CLK_NUMBER_H3 (CLK_GPU + 1) 528c2ecf20Sopenharmony_ci#define CLK_NUMBER_H5 (CLK_BUS_SCR1 + 1) 538c2ecf20Sopenharmony_ci 548c2ecf20Sopenharmony_ci#endif /* _CCU_SUN8I_H3_H_ */ 55