18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0-or-later */ 28c2ecf20Sopenharmony_ci/* 38c2ecf20Sopenharmony_ci * Copyright 2016 Maxime Ripard 48c2ecf20Sopenharmony_ci * 58c2ecf20Sopenharmony_ci * Maxime Ripard <maxime.ripard@free-electrons.com> 68c2ecf20Sopenharmony_ci */ 78c2ecf20Sopenharmony_ci 88c2ecf20Sopenharmony_ci#ifndef _CCU_SUN50I_A64_H_ 98c2ecf20Sopenharmony_ci#define _CCU_SUN50I_A64_H_ 108c2ecf20Sopenharmony_ci 118c2ecf20Sopenharmony_ci#include <dt-bindings/clock/sun50i-a64-ccu.h> 128c2ecf20Sopenharmony_ci#include <dt-bindings/reset/sun50i-a64-ccu.h> 138c2ecf20Sopenharmony_ci 148c2ecf20Sopenharmony_ci#define CLK_OSC_12M 0 158c2ecf20Sopenharmony_ci#define CLK_PLL_CPUX 1 168c2ecf20Sopenharmony_ci#define CLK_PLL_AUDIO_BASE 2 178c2ecf20Sopenharmony_ci#define CLK_PLL_AUDIO 3 188c2ecf20Sopenharmony_ci#define CLK_PLL_AUDIO_2X 4 198c2ecf20Sopenharmony_ci#define CLK_PLL_AUDIO_4X 5 208c2ecf20Sopenharmony_ci#define CLK_PLL_AUDIO_8X 6 218c2ecf20Sopenharmony_ci 228c2ecf20Sopenharmony_ci/* PLL_VIDEO0 exported for HDMI PHY */ 238c2ecf20Sopenharmony_ci 248c2ecf20Sopenharmony_ci#define CLK_PLL_VIDEO0_2X 8 258c2ecf20Sopenharmony_ci#define CLK_PLL_VE 9 268c2ecf20Sopenharmony_ci#define CLK_PLL_DDR0 10 278c2ecf20Sopenharmony_ci 288c2ecf20Sopenharmony_ci/* PLL_PERIPH0 exported for PRCM */ 298c2ecf20Sopenharmony_ci 308c2ecf20Sopenharmony_ci#define CLK_PLL_PERIPH0_2X 12 318c2ecf20Sopenharmony_ci#define CLK_PLL_PERIPH1 13 328c2ecf20Sopenharmony_ci#define CLK_PLL_PERIPH1_2X 14 338c2ecf20Sopenharmony_ci#define CLK_PLL_VIDEO1 15 348c2ecf20Sopenharmony_ci#define CLK_PLL_GPU 16 358c2ecf20Sopenharmony_ci#define CLK_PLL_MIPI 17 368c2ecf20Sopenharmony_ci#define CLK_PLL_HSIC 18 378c2ecf20Sopenharmony_ci#define CLK_PLL_DE 19 388c2ecf20Sopenharmony_ci#define CLK_PLL_DDR1 20 398c2ecf20Sopenharmony_ci#define CLK_AXI 22 408c2ecf20Sopenharmony_ci#define CLK_APB 23 418c2ecf20Sopenharmony_ci#define CLK_AHB1 24 428c2ecf20Sopenharmony_ci#define CLK_APB1 25 438c2ecf20Sopenharmony_ci#define CLK_APB2 26 448c2ecf20Sopenharmony_ci#define CLK_AHB2 27 458c2ecf20Sopenharmony_ci 468c2ecf20Sopenharmony_ci/* All the bus gates are exported */ 478c2ecf20Sopenharmony_ci 488c2ecf20Sopenharmony_ci/* The first bunch of module clocks are exported */ 498c2ecf20Sopenharmony_ci 508c2ecf20Sopenharmony_ci#define CLK_USB_OHCI0_12M 90 518c2ecf20Sopenharmony_ci 528c2ecf20Sopenharmony_ci#define CLK_USB_OHCI1_12M 92 538c2ecf20Sopenharmony_ci 548c2ecf20Sopenharmony_ci#define CLK_DRAM 94 558c2ecf20Sopenharmony_ci 568c2ecf20Sopenharmony_ci/* All the DRAM gates are exported */ 578c2ecf20Sopenharmony_ci 588c2ecf20Sopenharmony_ci/* And the DSI and GPU module clock is exported */ 598c2ecf20Sopenharmony_ci 608c2ecf20Sopenharmony_ci#define CLK_NUMBER (CLK_GPU + 1) 618c2ecf20Sopenharmony_ci 628c2ecf20Sopenharmony_ci#endif /* _CCU_SUN50I_A64_H_ */ 63