18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0 */ 28c2ecf20Sopenharmony_ci/* 38c2ecf20Sopenharmony_ci * Copyright (c) 2020 Yangtao Li <frank@allwinnertech.com> 48c2ecf20Sopenharmony_ci */ 58c2ecf20Sopenharmony_ci 68c2ecf20Sopenharmony_ci#ifndef _CCU_SUN50I_A100_H_ 78c2ecf20Sopenharmony_ci#define _CCU_SUN50I_A100_H_ 88c2ecf20Sopenharmony_ci 98c2ecf20Sopenharmony_ci#include <dt-bindings/clock/sun50i-a100-ccu.h> 108c2ecf20Sopenharmony_ci#include <dt-bindings/reset/sun50i-a100-ccu.h> 118c2ecf20Sopenharmony_ci 128c2ecf20Sopenharmony_ci#define CLK_OSC12M 0 138c2ecf20Sopenharmony_ci#define CLK_PLL_CPUX 1 148c2ecf20Sopenharmony_ci#define CLK_PLL_DDR0 2 158c2ecf20Sopenharmony_ci 168c2ecf20Sopenharmony_ci/* PLL_PERIPH0 exported for PRCM */ 178c2ecf20Sopenharmony_ci 188c2ecf20Sopenharmony_ci#define CLK_PLL_PERIPH0_2X 4 198c2ecf20Sopenharmony_ci#define CLK_PLL_PERIPH1 5 208c2ecf20Sopenharmony_ci#define CLK_PLL_PERIPH1_2X 6 218c2ecf20Sopenharmony_ci#define CLK_PLL_GPU 7 228c2ecf20Sopenharmony_ci#define CLK_PLL_VIDEO0 8 238c2ecf20Sopenharmony_ci#define CLK_PLL_VIDEO0_2X 9 248c2ecf20Sopenharmony_ci#define CLK_PLL_VIDEO0_4X 10 258c2ecf20Sopenharmony_ci#define CLK_PLL_VIDEO1 11 268c2ecf20Sopenharmony_ci#define CLK_PLL_VIDEO1_2X 12 278c2ecf20Sopenharmony_ci#define CLK_PLL_VIDEO1_4X 13 288c2ecf20Sopenharmony_ci#define CLK_PLL_VIDEO2 14 298c2ecf20Sopenharmony_ci#define CLK_PLL_VIDEO2_2X 15 308c2ecf20Sopenharmony_ci#define CLK_PLL_VIDEO2_4X 16 318c2ecf20Sopenharmony_ci#define CLK_PLL_VIDEO3 17 328c2ecf20Sopenharmony_ci#define CLK_PLL_VIDEO3_2X 18 338c2ecf20Sopenharmony_ci#define CLK_PLL_VIDEO3_4X 19 348c2ecf20Sopenharmony_ci#define CLK_PLL_VE 20 358c2ecf20Sopenharmony_ci#define CLK_PLL_COM 21 368c2ecf20Sopenharmony_ci#define CLK_PLL_COM_AUDIO 22 378c2ecf20Sopenharmony_ci#define CLK_PLL_AUDIO 23 388c2ecf20Sopenharmony_ci 398c2ecf20Sopenharmony_ci/* CPUX clock exported for DVFS */ 408c2ecf20Sopenharmony_ci 418c2ecf20Sopenharmony_ci#define CLK_AXI 25 428c2ecf20Sopenharmony_ci#define CLK_CPUX_APB 26 438c2ecf20Sopenharmony_ci#define CLK_PSI_AHB1_AHB2 27 448c2ecf20Sopenharmony_ci#define CLK_AHB3 28 458c2ecf20Sopenharmony_ci 468c2ecf20Sopenharmony_ci/* APB1 clock exported for PIO */ 478c2ecf20Sopenharmony_ci 488c2ecf20Sopenharmony_ci#define CLK_APB2 30 498c2ecf20Sopenharmony_ci 508c2ecf20Sopenharmony_ci/* All module clocks and bus gates are exported except DRAM */ 518c2ecf20Sopenharmony_ci 528c2ecf20Sopenharmony_ci#define CLK_BUS_DRAM 58 538c2ecf20Sopenharmony_ci 548c2ecf20Sopenharmony_ci#define CLK_NUMBER (CLK_CSI_ISP + 1) 558c2ecf20Sopenharmony_ci 568c2ecf20Sopenharmony_ci#endif /* _CCU_SUN50I_A100_H_ */ 57