18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0-or-later */ 28c2ecf20Sopenharmony_ci/* 38c2ecf20Sopenharmony_ci * Copyright 2017 Priit Laes 48c2ecf20Sopenharmony_ci * 58c2ecf20Sopenharmony_ci * Priit Laes <plaes@plaes.org> 68c2ecf20Sopenharmony_ci */ 78c2ecf20Sopenharmony_ci 88c2ecf20Sopenharmony_ci#ifndef _CCU_SUN4I_A10_H_ 98c2ecf20Sopenharmony_ci#define _CCU_SUN4I_A10_H_ 108c2ecf20Sopenharmony_ci 118c2ecf20Sopenharmony_ci#include <dt-bindings/clock/sun4i-a10-ccu.h> 128c2ecf20Sopenharmony_ci#include <dt-bindings/clock/sun7i-a20-ccu.h> 138c2ecf20Sopenharmony_ci#include <dt-bindings/reset/sun4i-a10-ccu.h> 148c2ecf20Sopenharmony_ci 158c2ecf20Sopenharmony_ci/* The HOSC is exported */ 168c2ecf20Sopenharmony_ci#define CLK_PLL_CORE 2 178c2ecf20Sopenharmony_ci#define CLK_PLL_AUDIO_BASE 3 188c2ecf20Sopenharmony_ci#define CLK_PLL_AUDIO 4 198c2ecf20Sopenharmony_ci#define CLK_PLL_AUDIO_2X 5 208c2ecf20Sopenharmony_ci#define CLK_PLL_AUDIO_4X 6 218c2ecf20Sopenharmony_ci#define CLK_PLL_AUDIO_8X 7 228c2ecf20Sopenharmony_ci#define CLK_PLL_VIDEO0 8 238c2ecf20Sopenharmony_ci/* The PLL_VIDEO0_2X clock is exported */ 248c2ecf20Sopenharmony_ci#define CLK_PLL_VE 10 258c2ecf20Sopenharmony_ci#define CLK_PLL_DDR_BASE 11 268c2ecf20Sopenharmony_ci#define CLK_PLL_DDR 12 278c2ecf20Sopenharmony_ci#define CLK_PLL_DDR_OTHER 13 288c2ecf20Sopenharmony_ci#define CLK_PLL_PERIPH_BASE 14 298c2ecf20Sopenharmony_ci#define CLK_PLL_PERIPH 15 308c2ecf20Sopenharmony_ci#define CLK_PLL_PERIPH_SATA 16 318c2ecf20Sopenharmony_ci#define CLK_PLL_VIDEO1 17 328c2ecf20Sopenharmony_ci/* The PLL_VIDEO1_2X clock is exported */ 338c2ecf20Sopenharmony_ci#define CLK_PLL_GPU 19 348c2ecf20Sopenharmony_ci 358c2ecf20Sopenharmony_ci/* The CPU clock is exported */ 368c2ecf20Sopenharmony_ci#define CLK_AXI 21 378c2ecf20Sopenharmony_ci#define CLK_AXI_DRAM 22 388c2ecf20Sopenharmony_ci#define CLK_AHB 23 398c2ecf20Sopenharmony_ci#define CLK_APB0 24 408c2ecf20Sopenharmony_ci#define CLK_APB1 25 418c2ecf20Sopenharmony_ci 428c2ecf20Sopenharmony_ci/* AHB gates are exported (23..68) */ 438c2ecf20Sopenharmony_ci/* APB0 gates are exported (69..78) */ 448c2ecf20Sopenharmony_ci/* APB1 gates are exported (79..95) */ 458c2ecf20Sopenharmony_ci/* IP module clocks are exported (96..128) */ 468c2ecf20Sopenharmony_ci/* DRAM gates are exported (129..142)*/ 478c2ecf20Sopenharmony_ci/* Media (display engine clocks & etc) are exported (143..169) */ 488c2ecf20Sopenharmony_ci 498c2ecf20Sopenharmony_ci#define CLK_NUMBER_SUN4I (CLK_MBUS + 1) 508c2ecf20Sopenharmony_ci#define CLK_NUMBER_SUN7I (CLK_OUT_B + 1) 518c2ecf20Sopenharmony_ci 528c2ecf20Sopenharmony_ci#endif /* _CCU_SUN4I_A10_H_ */ 53