1/* 2 * Clock framework definitions for SPEAr platform 3 * 4 * Copyright (C) 2012 ST Microelectronics 5 * Viresh Kumar <vireshk@kernel.org> 6 * 7 * This file is licensed under the terms of the GNU General Public 8 * License version 2. This program is licensed "as is" without any 9 * warranty of any kind, whether express or implied. 10 */ 11 12#ifndef __SPEAR_CLK_H 13#define __SPEAR_CLK_H 14 15#include <linux/clk-provider.h> 16#include <linux/spinlock_types.h> 17#include <linux/types.h> 18 19/* Auxiliary Synth clk */ 20/* Default masks */ 21#define AUX_EQ_SEL_SHIFT 30 22#define AUX_EQ_SEL_MASK 1 23#define AUX_EQ1_SEL 0 24#define AUX_EQ2_SEL 1 25#define AUX_XSCALE_SHIFT 16 26#define AUX_XSCALE_MASK 0xFFF 27#define AUX_YSCALE_SHIFT 0 28#define AUX_YSCALE_MASK 0xFFF 29#define AUX_SYNT_ENB 31 30 31struct aux_clk_masks { 32 u32 eq_sel_mask; 33 u32 eq_sel_shift; 34 u32 eq1_mask; 35 u32 eq2_mask; 36 u32 xscale_sel_mask; 37 u32 xscale_sel_shift; 38 u32 yscale_sel_mask; 39 u32 yscale_sel_shift; 40 u32 enable_bit; 41}; 42 43struct aux_rate_tbl { 44 u16 xscale; 45 u16 yscale; 46 u8 eq; 47}; 48 49struct clk_aux { 50 struct clk_hw hw; 51 void __iomem *reg; 52 const struct aux_clk_masks *masks; 53 struct aux_rate_tbl *rtbl; 54 u8 rtbl_cnt; 55 spinlock_t *lock; 56}; 57 58/* Fractional Synth clk */ 59struct frac_rate_tbl { 60 u32 div; 61}; 62 63struct clk_frac { 64 struct clk_hw hw; 65 void __iomem *reg; 66 struct frac_rate_tbl *rtbl; 67 u8 rtbl_cnt; 68 spinlock_t *lock; 69}; 70 71/* GPT clk */ 72struct gpt_rate_tbl { 73 u16 mscale; 74 u16 nscale; 75}; 76 77struct clk_gpt { 78 struct clk_hw hw; 79 void __iomem *reg; 80 struct gpt_rate_tbl *rtbl; 81 u8 rtbl_cnt; 82 spinlock_t *lock; 83}; 84 85/* VCO-PLL clk */ 86struct pll_rate_tbl { 87 u8 mode; 88 u16 m; 89 u8 n; 90 u8 p; 91}; 92 93struct clk_vco { 94 struct clk_hw hw; 95 void __iomem *mode_reg; 96 void __iomem *cfg_reg; 97 struct pll_rate_tbl *rtbl; 98 u8 rtbl_cnt; 99 spinlock_t *lock; 100}; 101 102struct clk_pll { 103 struct clk_hw hw; 104 struct clk_vco *vco; 105 const char *parent[1]; 106 spinlock_t *lock; 107}; 108 109typedef unsigned long (*clk_calc_rate)(struct clk_hw *hw, unsigned long prate, 110 int index); 111 112/* clk register routines */ 113struct clk *clk_register_aux(const char *aux_name, const char *gate_name, 114 const char *parent_name, unsigned long flags, void __iomem *reg, 115 const struct aux_clk_masks *masks, struct aux_rate_tbl *rtbl, 116 u8 rtbl_cnt, spinlock_t *lock, struct clk **gate_clk); 117struct clk *clk_register_frac(const char *name, const char *parent_name, 118 unsigned long flags, void __iomem *reg, 119 struct frac_rate_tbl *rtbl, u8 rtbl_cnt, spinlock_t *lock); 120struct clk *clk_register_gpt(const char *name, const char *parent_name, unsigned 121 long flags, void __iomem *reg, struct gpt_rate_tbl *rtbl, u8 122 rtbl_cnt, spinlock_t *lock); 123struct clk *clk_register_vco_pll(const char *vco_name, const char *pll_name, 124 const char *vco_gate_name, const char *parent_name, 125 unsigned long flags, void __iomem *mode_reg, void __iomem 126 *cfg_reg, struct pll_rate_tbl *rtbl, u8 rtbl_cnt, 127 spinlock_t *lock, struct clk **pll_clk, 128 struct clk **vco_gate_clk); 129 130long clk_round_rate_index(struct clk_hw *hw, unsigned long drate, 131 unsigned long parent_rate, clk_calc_rate calc_rate, u8 rtbl_cnt, 132 int *index); 133 134#endif /* __SPEAR_CLK_H */ 135