1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * common clks module for all SiRF SoCs 4 * 5 * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group 6 * company. 7 */ 8 9#include <linux/clk.h> 10 11#define KHZ 1000 12#define MHZ (KHZ * KHZ) 13 14static void __iomem *sirfsoc_clk_vbase; 15static void __iomem *sirfsoc_rsc_vbase; 16static struct clk_onecell_data clk_data; 17 18/* 19 * SiRFprimaII clock controller 20 * - 2 oscillators: osc-26MHz, rtc-32.768KHz 21 * - 3 standard configurable plls: pll1, pll2 & pll3 22 * - 2 exclusive plls: usb phy pll and sata phy pll 23 * - 8 clock domains: cpu/cpudiv, mem/memdiv, sys/io, dsp, graphic, multimedia, 24 * display and sdphy. 25 * Each clock domain can select its own clock source from five clock sources, 26 * X_XIN, X_XINW, PLL1, PLL2 and PLL3. The domain clock is used as the source 27 * clock of the group clock. 28 * - dsp domain: gps, mf 29 * - io domain: dmac, nand, audio, uart, i2c, spi, usp, pwm, pulse 30 * - sys domain: security 31 */ 32 33struct clk_pll { 34 struct clk_hw hw; 35 unsigned short regofs; /* register offset */ 36}; 37 38#define to_pllclk(_hw) container_of(_hw, struct clk_pll, hw) 39 40struct clk_dmn { 41 struct clk_hw hw; 42 signed char enable_bit; /* enable bit: 0 ~ 63 */ 43 unsigned short regofs; /* register offset */ 44}; 45 46#define to_dmnclk(_hw) container_of(_hw, struct clk_dmn, hw) 47 48struct clk_std { 49 struct clk_hw hw; 50 signed char enable_bit; /* enable bit: 0 ~ 63 */ 51}; 52 53#define to_stdclk(_hw) container_of(_hw, struct clk_std, hw) 54 55static int std_clk_is_enabled(struct clk_hw *hw); 56static int std_clk_enable(struct clk_hw *hw); 57static void std_clk_disable(struct clk_hw *hw); 58 59static inline unsigned long clkc_readl(unsigned reg) 60{ 61 return readl(sirfsoc_clk_vbase + reg); 62} 63 64static inline void clkc_writel(u32 val, unsigned reg) 65{ 66 writel(val, sirfsoc_clk_vbase + reg); 67} 68 69/* 70 * std pll 71 */ 72 73static unsigned long pll_clk_recalc_rate(struct clk_hw *hw, 74 unsigned long parent_rate) 75{ 76 unsigned long fin = parent_rate; 77 struct clk_pll *clk = to_pllclk(hw); 78 u32 regcfg2 = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 - 79 SIRFSOC_CLKC_PLL1_CFG0; 80 81 if (clkc_readl(regcfg2) & BIT(2)) { 82 /* pll bypass mode */ 83 return fin; 84 } else { 85 /* fout = fin * nf / nr / od */ 86 u32 cfg0 = clkc_readl(clk->regofs); 87 u32 nf = (cfg0 & (BIT(13) - 1)) + 1; 88 u32 nr = ((cfg0 >> 13) & (BIT(6) - 1)) + 1; 89 u32 od = ((cfg0 >> 19) & (BIT(4) - 1)) + 1; 90 WARN_ON(fin % MHZ); 91 return fin / MHZ * nf / nr / od * MHZ; 92 } 93} 94 95static long pll_clk_round_rate(struct clk_hw *hw, unsigned long rate, 96 unsigned long *parent_rate) 97{ 98 unsigned long fin, nf, nr, od; 99 u64 dividend; 100 101 /* 102 * fout = fin * nf / (nr * od); 103 * set od = 1, nr = fin/MHz, so fout = nf * MHz 104 */ 105 rate = rate - rate % MHZ; 106 107 nf = rate / MHZ; 108 if (nf > BIT(13)) 109 nf = BIT(13); 110 if (nf < 1) 111 nf = 1; 112 113 fin = *parent_rate; 114 115 nr = fin / MHZ; 116 if (nr > BIT(6)) 117 nr = BIT(6); 118 od = 1; 119 120 dividend = (u64)fin * nf; 121 do_div(dividend, nr * od); 122 123 return (long)dividend; 124} 125 126static int pll_clk_set_rate(struct clk_hw *hw, unsigned long rate, 127 unsigned long parent_rate) 128{ 129 struct clk_pll *clk = to_pllclk(hw); 130 unsigned long fin, nf, nr, od, reg; 131 132 /* 133 * fout = fin * nf / (nr * od); 134 * set od = 1, nr = fin/MHz, so fout = nf * MHz 135 */ 136 137 nf = rate / MHZ; 138 if (unlikely((rate % MHZ) || nf > BIT(13) || nf < 1)) 139 return -EINVAL; 140 141 fin = parent_rate; 142 BUG_ON(fin < MHZ); 143 144 nr = fin / MHZ; 145 BUG_ON((fin % MHZ) || nr > BIT(6)); 146 147 od = 1; 148 149 reg = (nf - 1) | ((nr - 1) << 13) | ((od - 1) << 19); 150 clkc_writel(reg, clk->regofs); 151 152 reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG1 - SIRFSOC_CLKC_PLL1_CFG0; 153 clkc_writel((nf >> 1) - 1, reg); 154 155 reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 - SIRFSOC_CLKC_PLL1_CFG0; 156 while (!(clkc_readl(reg) & BIT(6))) 157 cpu_relax(); 158 159 return 0; 160} 161 162static long cpu_clk_round_rate(struct clk_hw *hw, unsigned long rate, 163 unsigned long *parent_rate) 164{ 165 /* 166 * SiRF SoC has not cpu clock control, 167 * So bypass to it's parent pll. 168 */ 169 struct clk_hw *parent_clk = clk_hw_get_parent(hw); 170 struct clk_hw *pll_parent_clk = clk_hw_get_parent(parent_clk); 171 unsigned long pll_parent_rate = clk_hw_get_rate(pll_parent_clk); 172 return pll_clk_round_rate(parent_clk, rate, &pll_parent_rate); 173} 174 175static unsigned long cpu_clk_recalc_rate(struct clk_hw *hw, 176 unsigned long parent_rate) 177{ 178 /* 179 * SiRF SoC has not cpu clock control, 180 * So return the parent pll rate. 181 */ 182 struct clk_hw *parent_clk = clk_hw_get_parent(hw); 183 return clk_hw_get_rate(parent_clk); 184} 185 186static const struct clk_ops std_pll_ops = { 187 .recalc_rate = pll_clk_recalc_rate, 188 .round_rate = pll_clk_round_rate, 189 .set_rate = pll_clk_set_rate, 190}; 191 192static const char * const pll_clk_parents[] = { 193 "osc", 194}; 195 196static const struct clk_init_data clk_pll1_init = { 197 .name = "pll1", 198 .ops = &std_pll_ops, 199 .parent_names = pll_clk_parents, 200 .num_parents = ARRAY_SIZE(pll_clk_parents), 201}; 202 203static const struct clk_init_data clk_pll2_init = { 204 .name = "pll2", 205 .ops = &std_pll_ops, 206 .parent_names = pll_clk_parents, 207 .num_parents = ARRAY_SIZE(pll_clk_parents), 208}; 209 210static const struct clk_init_data clk_pll3_init = { 211 .name = "pll3", 212 .ops = &std_pll_ops, 213 .parent_names = pll_clk_parents, 214 .num_parents = ARRAY_SIZE(pll_clk_parents), 215}; 216 217static struct clk_pll clk_pll1 = { 218 .regofs = SIRFSOC_CLKC_PLL1_CFG0, 219 .hw = { 220 .init = &clk_pll1_init, 221 }, 222}; 223 224static struct clk_pll clk_pll2 = { 225 .regofs = SIRFSOC_CLKC_PLL2_CFG0, 226 .hw = { 227 .init = &clk_pll2_init, 228 }, 229}; 230 231static struct clk_pll clk_pll3 = { 232 .regofs = SIRFSOC_CLKC_PLL3_CFG0, 233 .hw = { 234 .init = &clk_pll3_init, 235 }, 236}; 237 238/* 239 * usb uses specified pll 240 */ 241 242static int usb_pll_clk_enable(struct clk_hw *hw) 243{ 244 u32 reg = readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL); 245 reg &= ~(SIRFSOC_USBPHY_PLL_POWERDOWN | SIRFSOC_USBPHY_PLL_BYPASS); 246 writel(reg, sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL); 247 while (!(readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL) & 248 SIRFSOC_USBPHY_PLL_LOCK)) 249 cpu_relax(); 250 251 return 0; 252} 253 254static void usb_pll_clk_disable(struct clk_hw *clk) 255{ 256 u32 reg = readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL); 257 reg |= (SIRFSOC_USBPHY_PLL_POWERDOWN | SIRFSOC_USBPHY_PLL_BYPASS); 258 writel(reg, sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL); 259} 260 261static unsigned long usb_pll_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 262{ 263 u32 reg = readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL); 264 return (reg & SIRFSOC_USBPHY_PLL_BYPASS) ? parent_rate : 48*MHZ; 265} 266 267static const struct clk_ops usb_pll_ops = { 268 .enable = usb_pll_clk_enable, 269 .disable = usb_pll_clk_disable, 270 .recalc_rate = usb_pll_clk_recalc_rate, 271}; 272 273static const struct clk_init_data clk_usb_pll_init = { 274 .name = "usb_pll", 275 .ops = &usb_pll_ops, 276 .parent_names = pll_clk_parents, 277 .num_parents = ARRAY_SIZE(pll_clk_parents), 278}; 279 280static struct clk_hw usb_pll_clk_hw = { 281 .init = &clk_usb_pll_init, 282}; 283 284/* 285 * clock domains - cpu, mem, sys/io, dsp, gfx 286 */ 287 288static const char * const dmn_clk_parents[] = { 289 "rtc", 290 "osc", 291 "pll1", 292 "pll2", 293 "pll3", 294}; 295 296static u8 dmn_clk_get_parent(struct clk_hw *hw) 297{ 298 struct clk_dmn *clk = to_dmnclk(hw); 299 u32 cfg = clkc_readl(clk->regofs); 300 const char *name = clk_hw_get_name(hw); 301 302 /* parent of io domain can only be pll3 */ 303 if (strcmp(name, "io") == 0) 304 return 4; 305 306 WARN_ON((cfg & (BIT(3) - 1)) > 4); 307 308 return cfg & (BIT(3) - 1); 309} 310 311static int dmn_clk_set_parent(struct clk_hw *hw, u8 parent) 312{ 313 struct clk_dmn *clk = to_dmnclk(hw); 314 u32 cfg = clkc_readl(clk->regofs); 315 const char *name = clk_hw_get_name(hw); 316 317 /* parent of io domain can only be pll3 */ 318 if (strcmp(name, "io") == 0) 319 return -EINVAL; 320 321 cfg &= ~(BIT(3) - 1); 322 clkc_writel(cfg | parent, clk->regofs); 323 /* BIT(3) - switching status: 1 - busy, 0 - done */ 324 while (clkc_readl(clk->regofs) & BIT(3)) 325 cpu_relax(); 326 327 return 0; 328} 329 330static unsigned long dmn_clk_recalc_rate(struct clk_hw *hw, 331 unsigned long parent_rate) 332 333{ 334 unsigned long fin = parent_rate; 335 struct clk_dmn *clk = to_dmnclk(hw); 336 337 u32 cfg = clkc_readl(clk->regofs); 338 339 if (cfg & BIT(24)) { 340 /* fcd bypass mode */ 341 return fin; 342 } else { 343 /* 344 * wait count: bit[19:16], hold count: bit[23:20] 345 */ 346 u32 wait = (cfg >> 16) & (BIT(4) - 1); 347 u32 hold = (cfg >> 20) & (BIT(4) - 1); 348 349 return fin / (wait + hold + 2); 350 } 351} 352 353static long dmn_clk_round_rate(struct clk_hw *hw, unsigned long rate, 354 unsigned long *parent_rate) 355{ 356 unsigned long fin; 357 unsigned ratio, wait, hold; 358 const char *name = clk_hw_get_name(hw); 359 unsigned bits = (strcmp(name, "mem") == 0) ? 3 : 4; 360 361 fin = *parent_rate; 362 ratio = fin / rate; 363 364 if (ratio < 2) 365 ratio = 2; 366 if (ratio > BIT(bits + 1)) 367 ratio = BIT(bits + 1); 368 369 wait = (ratio >> 1) - 1; 370 hold = ratio - wait - 2; 371 372 return fin / (wait + hold + 2); 373} 374 375static int dmn_clk_set_rate(struct clk_hw *hw, unsigned long rate, 376 unsigned long parent_rate) 377{ 378 struct clk_dmn *clk = to_dmnclk(hw); 379 unsigned long fin; 380 unsigned ratio, wait, hold, reg; 381 const char *name = clk_hw_get_name(hw); 382 unsigned bits = (strcmp(name, "mem") == 0) ? 3 : 4; 383 384 fin = parent_rate; 385 ratio = fin / rate; 386 387 if (unlikely(ratio < 2 || ratio > BIT(bits + 1))) 388 return -EINVAL; 389 390 WARN_ON(fin % rate); 391 392 wait = (ratio >> 1) - 1; 393 hold = ratio - wait - 2; 394 395 reg = clkc_readl(clk->regofs); 396 reg &= ~(((BIT(bits) - 1) << 16) | ((BIT(bits) - 1) << 20)); 397 reg |= (wait << 16) | (hold << 20) | BIT(25); 398 clkc_writel(reg, clk->regofs); 399 400 /* waiting FCD been effective */ 401 while (clkc_readl(clk->regofs) & BIT(25)) 402 cpu_relax(); 403 404 return 0; 405} 406 407static int cpu_clk_set_rate(struct clk_hw *hw, unsigned long rate, 408 unsigned long parent_rate) 409{ 410 int ret1, ret2; 411 struct clk *cur_parent; 412 413 if (rate == clk_get_rate(clk_pll1.hw.clk)) { 414 ret1 = clk_set_parent(hw->clk, clk_pll1.hw.clk); 415 return ret1; 416 } 417 418 if (rate == clk_get_rate(clk_pll2.hw.clk)) { 419 ret1 = clk_set_parent(hw->clk, clk_pll2.hw.clk); 420 return ret1; 421 } 422 423 if (rate == clk_get_rate(clk_pll3.hw.clk)) { 424 ret1 = clk_set_parent(hw->clk, clk_pll3.hw.clk); 425 return ret1; 426 } 427 428 cur_parent = clk_get_parent(hw->clk); 429 430 /* switch to tmp pll before setting parent clock's rate */ 431 if (cur_parent == clk_pll1.hw.clk) { 432 ret1 = clk_set_parent(hw->clk, clk_pll2.hw.clk); 433 BUG_ON(ret1); 434 } 435 436 ret2 = clk_set_rate(clk_pll1.hw.clk, rate); 437 438 ret1 = clk_set_parent(hw->clk, clk_pll1.hw.clk); 439 440 return ret2 ? ret2 : ret1; 441} 442 443static const struct clk_ops msi_ops = { 444 .set_rate = dmn_clk_set_rate, 445 .round_rate = dmn_clk_round_rate, 446 .recalc_rate = dmn_clk_recalc_rate, 447 .set_parent = dmn_clk_set_parent, 448 .get_parent = dmn_clk_get_parent, 449}; 450 451static const struct clk_init_data clk_mem_init = { 452 .name = "mem", 453 .ops = &msi_ops, 454 .parent_names = dmn_clk_parents, 455 .num_parents = ARRAY_SIZE(dmn_clk_parents), 456}; 457 458static struct clk_dmn clk_mem = { 459 .regofs = SIRFSOC_CLKC_MEM_CFG, 460 .hw = { 461 .init = &clk_mem_init, 462 }, 463}; 464 465static const struct clk_init_data clk_sys_init = { 466 .name = "sys", 467 .ops = &msi_ops, 468 .parent_names = dmn_clk_parents, 469 .num_parents = ARRAY_SIZE(dmn_clk_parents), 470 .flags = CLK_SET_RATE_GATE, 471}; 472 473static struct clk_dmn clk_sys = { 474 .regofs = SIRFSOC_CLKC_SYS_CFG, 475 .hw = { 476 .init = &clk_sys_init, 477 }, 478}; 479 480static const struct clk_init_data clk_io_init = { 481 .name = "io", 482 .ops = &msi_ops, 483 .parent_names = dmn_clk_parents, 484 .num_parents = ARRAY_SIZE(dmn_clk_parents), 485}; 486 487static struct clk_dmn clk_io = { 488 .regofs = SIRFSOC_CLKC_IO_CFG, 489 .hw = { 490 .init = &clk_io_init, 491 }, 492}; 493 494static const struct clk_ops cpu_ops = { 495 .set_parent = dmn_clk_set_parent, 496 .get_parent = dmn_clk_get_parent, 497 .set_rate = cpu_clk_set_rate, 498 .round_rate = cpu_clk_round_rate, 499 .recalc_rate = cpu_clk_recalc_rate, 500}; 501 502static const struct clk_init_data clk_cpu_init = { 503 .name = "cpu", 504 .ops = &cpu_ops, 505 .parent_names = dmn_clk_parents, 506 .num_parents = ARRAY_SIZE(dmn_clk_parents), 507 .flags = CLK_SET_RATE_PARENT, 508}; 509 510static struct clk_dmn clk_cpu = { 511 .regofs = SIRFSOC_CLKC_CPU_CFG, 512 .hw = { 513 .init = &clk_cpu_init, 514 }, 515}; 516 517static const struct clk_ops dmn_ops = { 518 .is_enabled = std_clk_is_enabled, 519 .enable = std_clk_enable, 520 .disable = std_clk_disable, 521 .set_rate = dmn_clk_set_rate, 522 .round_rate = dmn_clk_round_rate, 523 .recalc_rate = dmn_clk_recalc_rate, 524 .set_parent = dmn_clk_set_parent, 525 .get_parent = dmn_clk_get_parent, 526}; 527 528/* dsp, gfx, mm, lcd and vpp domain */ 529 530static const struct clk_init_data clk_dsp_init = { 531 .name = "dsp", 532 .ops = &dmn_ops, 533 .parent_names = dmn_clk_parents, 534 .num_parents = ARRAY_SIZE(dmn_clk_parents), 535}; 536 537static struct clk_dmn clk_dsp = { 538 .regofs = SIRFSOC_CLKC_DSP_CFG, 539 .enable_bit = 0, 540 .hw = { 541 .init = &clk_dsp_init, 542 }, 543}; 544 545static const struct clk_init_data clk_gfx_init = { 546 .name = "gfx", 547 .ops = &dmn_ops, 548 .parent_names = dmn_clk_parents, 549 .num_parents = ARRAY_SIZE(dmn_clk_parents), 550}; 551 552static struct clk_dmn clk_gfx = { 553 .regofs = SIRFSOC_CLKC_GFX_CFG, 554 .enable_bit = 8, 555 .hw = { 556 .init = &clk_gfx_init, 557 }, 558}; 559 560static const struct clk_init_data clk_mm_init = { 561 .name = "mm", 562 .ops = &dmn_ops, 563 .parent_names = dmn_clk_parents, 564 .num_parents = ARRAY_SIZE(dmn_clk_parents), 565}; 566 567static struct clk_dmn clk_mm = { 568 .regofs = SIRFSOC_CLKC_MM_CFG, 569 .enable_bit = 9, 570 .hw = { 571 .init = &clk_mm_init, 572 }, 573}; 574 575/* 576 * for atlas6, gfx2d holds the bit of prima2's clk_mm 577 */ 578#define clk_gfx2d clk_mm 579 580static const struct clk_init_data clk_lcd_init = { 581 .name = "lcd", 582 .ops = &dmn_ops, 583 .parent_names = dmn_clk_parents, 584 .num_parents = ARRAY_SIZE(dmn_clk_parents), 585}; 586 587static struct clk_dmn clk_lcd = { 588 .regofs = SIRFSOC_CLKC_LCD_CFG, 589 .enable_bit = 10, 590 .hw = { 591 .init = &clk_lcd_init, 592 }, 593}; 594 595static const struct clk_init_data clk_vpp_init = { 596 .name = "vpp", 597 .ops = &dmn_ops, 598 .parent_names = dmn_clk_parents, 599 .num_parents = ARRAY_SIZE(dmn_clk_parents), 600}; 601 602static struct clk_dmn clk_vpp = { 603 .regofs = SIRFSOC_CLKC_LCD_CFG, 604 .enable_bit = 11, 605 .hw = { 606 .init = &clk_vpp_init, 607 }, 608}; 609 610static const struct clk_init_data clk_mmc01_init = { 611 .name = "mmc01", 612 .ops = &dmn_ops, 613 .parent_names = dmn_clk_parents, 614 .num_parents = ARRAY_SIZE(dmn_clk_parents), 615}; 616 617static const struct clk_init_data clk_mmc23_init = { 618 .name = "mmc23", 619 .ops = &dmn_ops, 620 .parent_names = dmn_clk_parents, 621 .num_parents = ARRAY_SIZE(dmn_clk_parents), 622}; 623 624static const struct clk_init_data clk_mmc45_init = { 625 .name = "mmc45", 626 .ops = &dmn_ops, 627 .parent_names = dmn_clk_parents, 628 .num_parents = ARRAY_SIZE(dmn_clk_parents), 629}; 630 631/* 632 * peripheral controllers in io domain 633 */ 634 635static int std_clk_is_enabled(struct clk_hw *hw) 636{ 637 u32 reg; 638 int bit; 639 struct clk_std *clk = to_stdclk(hw); 640 641 bit = clk->enable_bit % 32; 642 reg = clk->enable_bit / 32; 643 reg = SIRFSOC_CLKC_CLK_EN0 + reg * sizeof(reg); 644 645 return !!(clkc_readl(reg) & BIT(bit)); 646} 647 648static int std_clk_enable(struct clk_hw *hw) 649{ 650 u32 val, reg; 651 int bit; 652 struct clk_std *clk = to_stdclk(hw); 653 654 BUG_ON(clk->enable_bit < 0 || clk->enable_bit > 63); 655 656 bit = clk->enable_bit % 32; 657 reg = clk->enable_bit / 32; 658 reg = SIRFSOC_CLKC_CLK_EN0 + reg * sizeof(reg); 659 660 val = clkc_readl(reg) | BIT(bit); 661 clkc_writel(val, reg); 662 return 0; 663} 664 665static void std_clk_disable(struct clk_hw *hw) 666{ 667 u32 val, reg; 668 int bit; 669 struct clk_std *clk = to_stdclk(hw); 670 671 BUG_ON(clk->enable_bit < 0 || clk->enable_bit > 63); 672 673 bit = clk->enable_bit % 32; 674 reg = clk->enable_bit / 32; 675 reg = SIRFSOC_CLKC_CLK_EN0 + reg * sizeof(reg); 676 677 val = clkc_readl(reg) & ~BIT(bit); 678 clkc_writel(val, reg); 679} 680 681static const char * const std_clk_io_parents[] = { 682 "io", 683}; 684 685static const struct clk_ops ios_ops = { 686 .is_enabled = std_clk_is_enabled, 687 .enable = std_clk_enable, 688 .disable = std_clk_disable, 689}; 690 691static const struct clk_init_data clk_cphif_init = { 692 .name = "cphif", 693 .ops = &ios_ops, 694 .parent_names = std_clk_io_parents, 695 .num_parents = ARRAY_SIZE(std_clk_io_parents), 696}; 697 698static struct clk_std clk_cphif = { 699 .enable_bit = 20, 700 .hw = { 701 .init = &clk_cphif_init, 702 }, 703}; 704 705static const struct clk_init_data clk_dmac0_init = { 706 .name = "dmac0", 707 .ops = &ios_ops, 708 .parent_names = std_clk_io_parents, 709 .num_parents = ARRAY_SIZE(std_clk_io_parents), 710}; 711 712static struct clk_std clk_dmac0 = { 713 .enable_bit = 32, 714 .hw = { 715 .init = &clk_dmac0_init, 716 }, 717}; 718 719static const struct clk_init_data clk_dmac1_init = { 720 .name = "dmac1", 721 .ops = &ios_ops, 722 .parent_names = std_clk_io_parents, 723 .num_parents = ARRAY_SIZE(std_clk_io_parents), 724}; 725 726static struct clk_std clk_dmac1 = { 727 .enable_bit = 33, 728 .hw = { 729 .init = &clk_dmac1_init, 730 }, 731}; 732 733static const struct clk_init_data clk_audio_init = { 734 .name = "audio", 735 .ops = &ios_ops, 736 .parent_names = std_clk_io_parents, 737 .num_parents = ARRAY_SIZE(std_clk_io_parents), 738}; 739 740static struct clk_std clk_audio = { 741 .enable_bit = 35, 742 .hw = { 743 .init = &clk_audio_init, 744 }, 745}; 746 747static const struct clk_init_data clk_uart0_init = { 748 .name = "uart0", 749 .ops = &ios_ops, 750 .parent_names = std_clk_io_parents, 751 .num_parents = ARRAY_SIZE(std_clk_io_parents), 752}; 753 754static struct clk_std clk_uart0 = { 755 .enable_bit = 36, 756 .hw = { 757 .init = &clk_uart0_init, 758 }, 759}; 760 761static const struct clk_init_data clk_uart1_init = { 762 .name = "uart1", 763 .ops = &ios_ops, 764 .parent_names = std_clk_io_parents, 765 .num_parents = ARRAY_SIZE(std_clk_io_parents), 766}; 767 768static struct clk_std clk_uart1 = { 769 .enable_bit = 37, 770 .hw = { 771 .init = &clk_uart1_init, 772 }, 773}; 774 775static const struct clk_init_data clk_uart2_init = { 776 .name = "uart2", 777 .ops = &ios_ops, 778 .parent_names = std_clk_io_parents, 779 .num_parents = ARRAY_SIZE(std_clk_io_parents), 780}; 781 782static struct clk_std clk_uart2 = { 783 .enable_bit = 38, 784 .hw = { 785 .init = &clk_uart2_init, 786 }, 787}; 788 789static const struct clk_init_data clk_usp0_init = { 790 .name = "usp0", 791 .ops = &ios_ops, 792 .parent_names = std_clk_io_parents, 793 .num_parents = ARRAY_SIZE(std_clk_io_parents), 794}; 795 796static struct clk_std clk_usp0 = { 797 .enable_bit = 39, 798 .hw = { 799 .init = &clk_usp0_init, 800 }, 801}; 802 803static const struct clk_init_data clk_usp1_init = { 804 .name = "usp1", 805 .ops = &ios_ops, 806 .parent_names = std_clk_io_parents, 807 .num_parents = ARRAY_SIZE(std_clk_io_parents), 808}; 809 810static struct clk_std clk_usp1 = { 811 .enable_bit = 40, 812 .hw = { 813 .init = &clk_usp1_init, 814 }, 815}; 816 817static const struct clk_init_data clk_usp2_init = { 818 .name = "usp2", 819 .ops = &ios_ops, 820 .parent_names = std_clk_io_parents, 821 .num_parents = ARRAY_SIZE(std_clk_io_parents), 822}; 823 824static struct clk_std clk_usp2 = { 825 .enable_bit = 41, 826 .hw = { 827 .init = &clk_usp2_init, 828 }, 829}; 830 831static const struct clk_init_data clk_vip_init = { 832 .name = "vip", 833 .ops = &ios_ops, 834 .parent_names = std_clk_io_parents, 835 .num_parents = ARRAY_SIZE(std_clk_io_parents), 836}; 837 838static struct clk_std clk_vip = { 839 .enable_bit = 42, 840 .hw = { 841 .init = &clk_vip_init, 842 }, 843}; 844 845static const struct clk_init_data clk_spi0_init = { 846 .name = "spi0", 847 .ops = &ios_ops, 848 .parent_names = std_clk_io_parents, 849 .num_parents = ARRAY_SIZE(std_clk_io_parents), 850}; 851 852static struct clk_std clk_spi0 = { 853 .enable_bit = 43, 854 .hw = { 855 .init = &clk_spi0_init, 856 }, 857}; 858 859static const struct clk_init_data clk_spi1_init = { 860 .name = "spi1", 861 .ops = &ios_ops, 862 .parent_names = std_clk_io_parents, 863 .num_parents = ARRAY_SIZE(std_clk_io_parents), 864}; 865 866static struct clk_std clk_spi1 = { 867 .enable_bit = 44, 868 .hw = { 869 .init = &clk_spi1_init, 870 }, 871}; 872 873static const struct clk_init_data clk_tsc_init = { 874 .name = "tsc", 875 .ops = &ios_ops, 876 .parent_names = std_clk_io_parents, 877 .num_parents = ARRAY_SIZE(std_clk_io_parents), 878}; 879 880static struct clk_std clk_tsc = { 881 .enable_bit = 45, 882 .hw = { 883 .init = &clk_tsc_init, 884 }, 885}; 886 887static const struct clk_init_data clk_i2c0_init = { 888 .name = "i2c0", 889 .ops = &ios_ops, 890 .parent_names = std_clk_io_parents, 891 .num_parents = ARRAY_SIZE(std_clk_io_parents), 892}; 893 894static struct clk_std clk_i2c0 = { 895 .enable_bit = 46, 896 .hw = { 897 .init = &clk_i2c0_init, 898 }, 899}; 900 901static const struct clk_init_data clk_i2c1_init = { 902 .name = "i2c1", 903 .ops = &ios_ops, 904 .parent_names = std_clk_io_parents, 905 .num_parents = ARRAY_SIZE(std_clk_io_parents), 906}; 907 908static struct clk_std clk_i2c1 = { 909 .enable_bit = 47, 910 .hw = { 911 .init = &clk_i2c1_init, 912 }, 913}; 914 915static const struct clk_init_data clk_pwmc_init = { 916 .name = "pwmc", 917 .ops = &ios_ops, 918 .parent_names = std_clk_io_parents, 919 .num_parents = ARRAY_SIZE(std_clk_io_parents), 920}; 921 922static struct clk_std clk_pwmc = { 923 .enable_bit = 48, 924 .hw = { 925 .init = &clk_pwmc_init, 926 }, 927}; 928 929static const struct clk_init_data clk_efuse_init = { 930 .name = "efuse", 931 .ops = &ios_ops, 932 .parent_names = std_clk_io_parents, 933 .num_parents = ARRAY_SIZE(std_clk_io_parents), 934}; 935 936static struct clk_std clk_efuse = { 937 .enable_bit = 49, 938 .hw = { 939 .init = &clk_efuse_init, 940 }, 941}; 942 943static const struct clk_init_data clk_pulse_init = { 944 .name = "pulse", 945 .ops = &ios_ops, 946 .parent_names = std_clk_io_parents, 947 .num_parents = ARRAY_SIZE(std_clk_io_parents), 948}; 949 950static struct clk_std clk_pulse = { 951 .enable_bit = 50, 952 .hw = { 953 .init = &clk_pulse_init, 954 }, 955}; 956 957static const char * const std_clk_dsp_parents[] = { 958 "dsp", 959}; 960 961static const struct clk_init_data clk_gps_init = { 962 .name = "gps", 963 .ops = &ios_ops, 964 .parent_names = std_clk_dsp_parents, 965 .num_parents = ARRAY_SIZE(std_clk_dsp_parents), 966}; 967 968static struct clk_std clk_gps = { 969 .enable_bit = 1, 970 .hw = { 971 .init = &clk_gps_init, 972 }, 973}; 974 975static const struct clk_init_data clk_mf_init = { 976 .name = "mf", 977 .ops = &ios_ops, 978 .parent_names = std_clk_io_parents, 979 .num_parents = ARRAY_SIZE(std_clk_io_parents), 980}; 981 982static struct clk_std clk_mf = { 983 .enable_bit = 2, 984 .hw = { 985 .init = &clk_mf_init, 986 }, 987}; 988 989static const char * const std_clk_sys_parents[] = { 990 "sys", 991}; 992 993static const struct clk_init_data clk_security_init = { 994 .name = "security", 995 .ops = &ios_ops, 996 .parent_names = std_clk_sys_parents, 997 .num_parents = ARRAY_SIZE(std_clk_sys_parents), 998}; 999 1000static struct clk_std clk_security = { 1001 .enable_bit = 19, 1002 .hw = { 1003 .init = &clk_security_init, 1004 }, 1005}; 1006 1007static const char * const std_clk_usb_parents[] = { 1008 "usb_pll", 1009}; 1010 1011static const struct clk_init_data clk_usb0_init = { 1012 .name = "usb0", 1013 .ops = &ios_ops, 1014 .parent_names = std_clk_usb_parents, 1015 .num_parents = ARRAY_SIZE(std_clk_usb_parents), 1016}; 1017 1018static struct clk_std clk_usb0 = { 1019 .enable_bit = 16, 1020 .hw = { 1021 .init = &clk_usb0_init, 1022 }, 1023}; 1024 1025static const struct clk_init_data clk_usb1_init = { 1026 .name = "usb1", 1027 .ops = &ios_ops, 1028 .parent_names = std_clk_usb_parents, 1029 .num_parents = ARRAY_SIZE(std_clk_usb_parents), 1030}; 1031 1032static struct clk_std clk_usb1 = { 1033 .enable_bit = 17, 1034 .hw = { 1035 .init = &clk_usb1_init, 1036 }, 1037}; 1038