1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de> 4 * 5 * Common Clock Framework support for S3C2443 and following SoCs. 6 */ 7 8#include <linux/clk-provider.h> 9#include <linux/clk/samsung.h> 10#include <linux/io.h> 11#include <linux/of.h> 12#include <linux/of_address.h> 13#include <linux/reboot.h> 14 15#include <dt-bindings/clock/s3c2443.h> 16 17#include "clk.h" 18#include "clk-pll.h" 19 20/* S3C2416 clock controller register offsets */ 21#define LOCKCON0 0x00 22#define LOCKCON1 0x04 23#define MPLLCON 0x10 24#define EPLLCON 0x18 25#define EPLLCON_K 0x1C 26#define CLKSRC 0x20 27#define CLKDIV0 0x24 28#define CLKDIV1 0x28 29#define CLKDIV2 0x2C 30#define HCLKCON 0x30 31#define PCLKCON 0x34 32#define SCLKCON 0x38 33#define SWRST 0x44 34 35/* the soc types */ 36enum supported_socs { 37 S3C2416, 38 S3C2443, 39 S3C2450, 40}; 41 42static void __iomem *reg_base; 43 44/* 45 * list of controller registers to be saved and restored during a 46 * suspend/resume cycle. 47 */ 48static unsigned long s3c2443_clk_regs[] __initdata = { 49 LOCKCON0, 50 LOCKCON1, 51 MPLLCON, 52 EPLLCON, 53 EPLLCON_K, 54 CLKSRC, 55 CLKDIV0, 56 CLKDIV1, 57 CLKDIV2, 58 PCLKCON, 59 HCLKCON, 60 SCLKCON, 61}; 62 63PNAME(epllref_p) = { "mpllref", "mpllref", "xti", "ext" }; 64PNAME(esysclk_p) = { "epllref", "epll" }; 65PNAME(mpllref_p) = { "xti", "mdivclk" }; 66PNAME(msysclk_p) = { "mpllref", "mpll" }; 67PNAME(armclk_p) = { "armdiv" , "hclk" }; 68PNAME(i2s0_p) = { "div_i2s0", "ext_i2s", "epllref", "epllref" }; 69 70static struct samsung_mux_clock s3c2443_common_muxes[] __initdata = { 71 MUX(0, "epllref", epllref_p, CLKSRC, 7, 2), 72 MUX(ESYSCLK, "esysclk", esysclk_p, CLKSRC, 6, 1), 73 MUX(0, "mpllref", mpllref_p, CLKSRC, 3, 1), 74 MUX(MSYSCLK, "msysclk", msysclk_p, CLKSRC, 4, 1), 75 MUX(ARMCLK, "armclk", armclk_p, CLKDIV0, 13, 1), 76 MUX(0, "mux_i2s0", i2s0_p, CLKSRC, 14, 2), 77}; 78 79static struct clk_div_table hclk_d[] = { 80 { .val = 0, .div = 1 }, 81 { .val = 1, .div = 2 }, 82 { .val = 3, .div = 4 }, 83 { /* sentinel */ }, 84}; 85 86static struct clk_div_table mdivclk_d[] = { 87 { .val = 0, .div = 1 }, 88 { .val = 1, .div = 3 }, 89 { .val = 2, .div = 5 }, 90 { .val = 3, .div = 7 }, 91 { .val = 4, .div = 9 }, 92 { .val = 5, .div = 11 }, 93 { .val = 6, .div = 13 }, 94 { .val = 7, .div = 15 }, 95 { /* sentinel */ }, 96}; 97 98static struct samsung_div_clock s3c2443_common_dividers[] __initdata = { 99 DIV_T(0, "mdivclk", "xti", CLKDIV0, 6, 3, mdivclk_d), 100 DIV(0, "prediv", "msysclk", CLKDIV0, 4, 2), 101 DIV_T(HCLK, "hclk", "prediv", CLKDIV0, 0, 2, hclk_d), 102 DIV(PCLK, "pclk", "hclk", CLKDIV0, 2, 1), 103 DIV(0, "div_hsspi0_epll", "esysclk", CLKDIV1, 24, 2), 104 DIV(0, "div_fimd", "esysclk", CLKDIV1, 16, 8), 105 DIV(0, "div_i2s0", "esysclk", CLKDIV1, 12, 4), 106 DIV(0, "div_uart", "esysclk", CLKDIV1, 8, 4), 107 DIV(0, "div_hsmmc1", "esysclk", CLKDIV1, 6, 2), 108 DIV(0, "div_usbhost", "esysclk", CLKDIV1, 4, 2), 109}; 110 111static struct samsung_gate_clock s3c2443_common_gates[] __initdata = { 112 GATE(SCLK_HSMMC_EXT, "sclk_hsmmcext", "ext", SCLKCON, 13, 0, 0), 113 GATE(SCLK_HSMMC1, "sclk_hsmmc1", "div_hsmmc1", SCLKCON, 12, 0, 0), 114 GATE(SCLK_FIMD, "sclk_fimd", "div_fimd", SCLKCON, 10, 0, 0), 115 GATE(SCLK_I2S0, "sclk_i2s0", "mux_i2s0", SCLKCON, 9, 0, 0), 116 GATE(SCLK_UART, "sclk_uart", "div_uart", SCLKCON, 8, 0, 0), 117 GATE(SCLK_USBH, "sclk_usbhost", "div_usbhost", SCLKCON, 1, 0, 0), 118 GATE(HCLK_DRAM, "dram", "hclk", HCLKCON, 19, CLK_IGNORE_UNUSED, 0), 119 GATE(HCLK_SSMC, "ssmc", "hclk", HCLKCON, 18, CLK_IGNORE_UNUSED, 0), 120 GATE(HCLK_HSMMC1, "hsmmc1", "hclk", HCLKCON, 16, 0, 0), 121 GATE(HCLK_USBD, "usb-device", "hclk", HCLKCON, 12, 0, 0), 122 GATE(HCLK_USBH, "usb-host", "hclk", HCLKCON, 11, 0, 0), 123 GATE(HCLK_LCD, "lcd", "hclk", HCLKCON, 9, 0, 0), 124 GATE(HCLK_DMA5, "dma5", "hclk", HCLKCON, 5, CLK_IGNORE_UNUSED, 0), 125 GATE(HCLK_DMA4, "dma4", "hclk", HCLKCON, 4, CLK_IGNORE_UNUSED, 0), 126 GATE(HCLK_DMA3, "dma3", "hclk", HCLKCON, 3, CLK_IGNORE_UNUSED, 0), 127 GATE(HCLK_DMA2, "dma2", "hclk", HCLKCON, 2, CLK_IGNORE_UNUSED, 0), 128 GATE(HCLK_DMA1, "dma1", "hclk", HCLKCON, 1, CLK_IGNORE_UNUSED, 0), 129 GATE(HCLK_DMA0, "dma0", "hclk", HCLKCON, 0, CLK_IGNORE_UNUSED, 0), 130 GATE(PCLK_GPIO, "gpio", "pclk", PCLKCON, 13, CLK_IGNORE_UNUSED, 0), 131 GATE(PCLK_RTC, "rtc", "pclk", PCLKCON, 12, 0, 0), 132 GATE(PCLK_WDT, "wdt", "pclk", PCLKCON, 11, 0, 0), 133 GATE(PCLK_PWM, "pwm", "pclk", PCLKCON, 10, 0, 0), 134 GATE(PCLK_I2S0, "i2s0", "pclk", PCLKCON, 9, 0, 0), 135 GATE(PCLK_AC97, "ac97", "pclk", PCLKCON, 8, 0, 0), 136 GATE(PCLK_ADC, "adc", "pclk", PCLKCON, 7, 0, 0), 137 GATE(PCLK_SPI0, "spi0", "pclk", PCLKCON, 6, 0, 0), 138 GATE(PCLK_I2C0, "i2c0", "pclk", PCLKCON, 4, 0, 0), 139 GATE(PCLK_UART3, "uart3", "pclk", PCLKCON, 3, 0, 0), 140 GATE(PCLK_UART2, "uart2", "pclk", PCLKCON, 2, 0, 0), 141 GATE(PCLK_UART1, "uart1", "pclk", PCLKCON, 1, 0, 0), 142 GATE(PCLK_UART0, "uart0", "pclk", PCLKCON, 0, 0, 0), 143}; 144 145static struct samsung_clock_alias s3c2443_common_aliases[] __initdata = { 146 ALIAS(MSYSCLK, NULL, "msysclk"), 147 ALIAS(ARMCLK, NULL, "armclk"), 148 ALIAS(MPLL, NULL, "mpll"), 149 ALIAS(EPLL, NULL, "epll"), 150 ALIAS(HCLK, NULL, "hclk"), 151 ALIAS(HCLK_SSMC, NULL, "nand"), 152 ALIAS(PCLK_UART0, "s3c2440-uart.0", "uart"), 153 ALIAS(PCLK_UART1, "s3c2440-uart.1", "uart"), 154 ALIAS(PCLK_UART2, "s3c2440-uart.2", "uart"), 155 ALIAS(PCLK_UART3, "s3c2440-uart.3", "uart"), 156 ALIAS(PCLK_UART0, "s3c2440-uart.0", "clk_uart_baud2"), 157 ALIAS(PCLK_UART1, "s3c2440-uart.1", "clk_uart_baud2"), 158 ALIAS(PCLK_UART2, "s3c2440-uart.2", "clk_uart_baud2"), 159 ALIAS(PCLK_UART3, "s3c2440-uart.3", "clk_uart_baud2"), 160 ALIAS(SCLK_UART, NULL, "clk_uart_baud3"), 161 ALIAS(PCLK_PWM, NULL, "timers"), 162 ALIAS(PCLK_RTC, NULL, "rtc"), 163 ALIAS(PCLK_WDT, NULL, "watchdog"), 164 ALIAS(PCLK_ADC, NULL, "adc"), 165 ALIAS(PCLK_I2C0, "s3c2410-i2c.0", "i2c"), 166 ALIAS(HCLK_USBD, NULL, "usb-device"), 167 ALIAS(HCLK_USBH, NULL, "usb-host"), 168 ALIAS(SCLK_USBH, NULL, "usb-bus-host"), 169 ALIAS(PCLK_SPI0, "s3c2443-spi.0", "spi"), 170 ALIAS(PCLK_SPI0, "s3c2443-spi.0", "spi_busclk0"), 171 ALIAS(HCLK_HSMMC1, "s3c-sdhci.1", "hsmmc"), 172 ALIAS(HCLK_HSMMC1, "s3c-sdhci.1", "mmc_busclk.0"), 173 ALIAS(PCLK_I2S0, "samsung-i2s.0", "iis"), 174 ALIAS(SCLK_I2S0, NULL, "i2s-if"), 175 ALIAS(HCLK_LCD, NULL, "lcd"), 176 ALIAS(SCLK_FIMD, NULL, "sclk_fimd"), 177}; 178 179/* S3C2416 specific clocks */ 180 181static struct samsung_pll_clock s3c2416_pll_clks[] __initdata = { 182 PLL(pll_6552_s3c2416, MPLL, "mpll", "mpllref", LOCKCON0, MPLLCON, NULL), 183 PLL(pll_6553, EPLL, "epll", "epllref", LOCKCON1, EPLLCON, NULL), 184}; 185 186PNAME(s3c2416_hsmmc0_p) = { "sclk_hsmmc0", "sclk_hsmmcext" }; 187PNAME(s3c2416_hsmmc1_p) = { "sclk_hsmmc1", "sclk_hsmmcext" }; 188PNAME(s3c2416_hsspi0_p) = { "hsspi0_epll", "hsspi0_mpll" }; 189 190static struct clk_div_table armdiv_s3c2416_d[] = { 191 { .val = 0, .div = 1 }, 192 { .val = 1, .div = 2 }, 193 { .val = 2, .div = 3 }, 194 { .val = 3, .div = 4 }, 195 { .val = 5, .div = 6 }, 196 { .val = 7, .div = 8 }, 197 { /* sentinel */ }, 198}; 199 200static struct samsung_div_clock s3c2416_dividers[] __initdata = { 201 DIV_T(ARMDIV, "armdiv", "msysclk", CLKDIV0, 9, 3, armdiv_s3c2416_d), 202 DIV(0, "div_hsspi0_mpll", "msysclk", CLKDIV2, 0, 4), 203 DIV(0, "div_hsmmc0", "esysclk", CLKDIV2, 6, 2), 204}; 205 206static struct samsung_mux_clock s3c2416_muxes[] __initdata = { 207 MUX(MUX_HSMMC0, "mux_hsmmc0", s3c2416_hsmmc0_p, CLKSRC, 16, 1), 208 MUX(MUX_HSMMC1, "mux_hsmmc1", s3c2416_hsmmc1_p, CLKSRC, 17, 1), 209 MUX(MUX_HSSPI0, "mux_hsspi0", s3c2416_hsspi0_p, CLKSRC, 18, 1), 210}; 211 212static struct samsung_gate_clock s3c2416_gates[] __initdata = { 213 GATE(0, "hsspi0_mpll", "div_hsspi0_mpll", SCLKCON, 19, 0, 0), 214 GATE(0, "hsspi0_epll", "div_hsspi0_epll", SCLKCON, 14, 0, 0), 215 GATE(0, "sclk_hsmmc0", "div_hsmmc0", SCLKCON, 6, 0, 0), 216 GATE(HCLK_2D, "2d", "hclk", HCLKCON, 20, 0, 0), 217 GATE(HCLK_HSMMC0, "hsmmc0", "hclk", HCLKCON, 15, 0, 0), 218 GATE(HCLK_IROM, "irom", "hclk", HCLKCON, 13, CLK_IGNORE_UNUSED, 0), 219 GATE(PCLK_PCM, "pcm", "pclk", PCLKCON, 19, 0, 0), 220}; 221 222static struct samsung_clock_alias s3c2416_aliases[] __initdata = { 223 ALIAS(HCLK_HSMMC0, "s3c-sdhci.0", "hsmmc"), 224 ALIAS(HCLK_HSMMC0, "s3c-sdhci.0", "mmc_busclk.0"), 225 ALIAS(MUX_HSMMC0, "s3c-sdhci.0", "mmc_busclk.2"), 226 ALIAS(MUX_HSMMC1, "s3c-sdhci.1", "mmc_busclk.2"), 227 ALIAS(MUX_HSSPI0, "s3c2443-spi.0", "spi_busclk2"), 228 ALIAS(ARMDIV, NULL, "armdiv"), 229}; 230 231/* S3C2443 specific clocks */ 232 233static struct samsung_pll_clock s3c2443_pll_clks[] __initdata = { 234 PLL(pll_3000, MPLL, "mpll", "mpllref", LOCKCON0, MPLLCON, NULL), 235 PLL(pll_2126, EPLL, "epll", "epllref", LOCKCON1, EPLLCON, NULL), 236}; 237 238static struct clk_div_table armdiv_s3c2443_d[] = { 239 { .val = 0, .div = 1 }, 240 { .val = 8, .div = 2 }, 241 { .val = 2, .div = 3 }, 242 { .val = 9, .div = 4 }, 243 { .val = 10, .div = 6 }, 244 { .val = 11, .div = 8 }, 245 { .val = 13, .div = 12 }, 246 { .val = 15, .div = 16 }, 247 { /* sentinel */ }, 248}; 249 250static struct samsung_div_clock s3c2443_dividers[] __initdata = { 251 DIV_T(ARMDIV, "armdiv", "msysclk", CLKDIV0, 9, 4, armdiv_s3c2443_d), 252 DIV(0, "div_cam", "esysclk", CLKDIV1, 26, 4), 253}; 254 255static struct samsung_gate_clock s3c2443_gates[] __initdata = { 256 GATE(SCLK_HSSPI0, "sclk_hsspi0", "div_hsspi0_epll", SCLKCON, 14, 0, 0), 257 GATE(SCLK_CAM, "sclk_cam", "div_cam", SCLKCON, 11, 0, 0), 258 GATE(HCLK_CFC, "cfc", "hclk", HCLKCON, 17, CLK_IGNORE_UNUSED, 0), 259 GATE(HCLK_CAM, "cam", "hclk", HCLKCON, 8, 0, 0), 260 GATE(PCLK_SPI1, "spi1", "pclk", PCLKCON, 15, 0, 0), 261 GATE(PCLK_SDI, "sdi", "pclk", PCLKCON, 5, 0, 0), 262}; 263 264static struct samsung_clock_alias s3c2443_aliases[] __initdata = { 265 ALIAS(SCLK_HSSPI0, "s3c2443-spi.0", "spi_busclk2"), 266 ALIAS(SCLK_HSMMC1, "s3c-sdhci.1", "mmc_busclk.2"), 267 ALIAS(SCLK_CAM, NULL, "camif-upll"), 268 ALIAS(PCLK_SPI1, "s3c2410-spi.0", "spi"), 269 ALIAS(PCLK_SDI, NULL, "sdi"), 270 ALIAS(HCLK_CFC, NULL, "cfc"), 271 ALIAS(ARMDIV, NULL, "armdiv"), 272}; 273 274/* S3C2450 specific clocks */ 275 276PNAME(s3c2450_cam_p) = { "div_cam", "hclk" }; 277PNAME(s3c2450_hsspi1_p) = { "hsspi1_epll", "hsspi1_mpll" }; 278PNAME(i2s1_p) = { "div_i2s1", "ext_i2s", "epllref", "epllref" }; 279 280static struct samsung_div_clock s3c2450_dividers[] __initdata = { 281 DIV(0, "div_cam", "esysclk", CLKDIV1, 26, 4), 282 DIV(0, "div_hsspi1_epll", "esysclk", CLKDIV2, 24, 2), 283 DIV(0, "div_hsspi1_mpll", "msysclk", CLKDIV2, 16, 4), 284 DIV(0, "div_i2s1", "esysclk", CLKDIV2, 12, 4), 285}; 286 287static struct samsung_mux_clock s3c2450_muxes[] __initdata = { 288 MUX(0, "mux_cam", s3c2450_cam_p, CLKSRC, 20, 1), 289 MUX(MUX_HSSPI1, "mux_hsspi1", s3c2450_hsspi1_p, CLKSRC, 19, 1), 290 MUX(0, "mux_i2s1", i2s1_p, CLKSRC, 12, 2), 291}; 292 293static struct samsung_gate_clock s3c2450_gates[] __initdata = { 294 GATE(SCLK_I2S1, "sclk_i2s1", "div_i2s1", SCLKCON, 5, 0, 0), 295 GATE(HCLK_CFC, "cfc", "hclk", HCLKCON, 17, 0, 0), 296 GATE(HCLK_CAM, "cam", "hclk", HCLKCON, 8, 0, 0), 297 GATE(HCLK_DMA7, "dma7", "hclk", HCLKCON, 7, CLK_IGNORE_UNUSED, 0), 298 GATE(HCLK_DMA6, "dma6", "hclk", HCLKCON, 6, CLK_IGNORE_UNUSED, 0), 299 GATE(PCLK_I2S1, "i2s1", "pclk", PCLKCON, 17, 0, 0), 300 GATE(PCLK_I2C1, "i2c1", "pclk", PCLKCON, 16, 0, 0), 301 GATE(PCLK_SPI1, "spi1", "pclk", PCLKCON, 14, 0, 0), 302}; 303 304static struct samsung_clock_alias s3c2450_aliases[] __initdata = { 305 ALIAS(PCLK_SPI1, "s3c2443-spi.1", "spi"), 306 ALIAS(PCLK_SPI1, "s3c2443-spi.1", "spi_busclk0"), 307 ALIAS(MUX_HSSPI1, "s3c2443-spi.1", "spi_busclk2"), 308 ALIAS(PCLK_I2C1, "s3c2410-i2c.1", "i2c"), 309}; 310 311static int s3c2443_restart(struct notifier_block *this, 312 unsigned long mode, void *cmd) 313{ 314 __raw_writel(0x533c2443, reg_base + SWRST); 315 return NOTIFY_DONE; 316} 317 318static struct notifier_block s3c2443_restart_handler = { 319 .notifier_call = s3c2443_restart, 320 .priority = 129, 321}; 322 323/* 324 * fixed rate clocks generated outside the soc 325 * Only necessary until the devicetree-move is complete 326 */ 327static struct samsung_fixed_rate_clock s3c2443_common_frate_clks[] __initdata = { 328 FRATE(0, "xti", NULL, 0, 0), 329 FRATE(0, "ext", NULL, 0, 0), 330 FRATE(0, "ext_i2s", NULL, 0, 0), 331 FRATE(0, "ext_uart", NULL, 0, 0), 332}; 333 334static void __init s3c2443_common_clk_register_fixed_ext( 335 struct samsung_clk_provider *ctx, unsigned long xti_f) 336{ 337 s3c2443_common_frate_clks[0].fixed_rate = xti_f; 338 samsung_clk_register_fixed_rate(ctx, s3c2443_common_frate_clks, 339 ARRAY_SIZE(s3c2443_common_frate_clks)); 340} 341 342void __init s3c2443_common_clk_init(struct device_node *np, unsigned long xti_f, 343 int current_soc, 344 void __iomem *base) 345{ 346 struct samsung_clk_provider *ctx; 347 int ret; 348 reg_base = base; 349 350 if (np) { 351 reg_base = of_iomap(np, 0); 352 if (!reg_base) 353 panic("%s: failed to map registers\n", __func__); 354 } 355 356 ctx = samsung_clk_init(np, reg_base, NR_CLKS); 357 358 /* Register external clocks only in non-dt cases */ 359 if (!np) 360 s3c2443_common_clk_register_fixed_ext(ctx, xti_f); 361 362 /* Register PLLs. */ 363 if (current_soc == S3C2416 || current_soc == S3C2450) 364 samsung_clk_register_pll(ctx, s3c2416_pll_clks, 365 ARRAY_SIZE(s3c2416_pll_clks), reg_base); 366 else 367 samsung_clk_register_pll(ctx, s3c2443_pll_clks, 368 ARRAY_SIZE(s3c2443_pll_clks), reg_base); 369 370 /* Register common internal clocks. */ 371 samsung_clk_register_mux(ctx, s3c2443_common_muxes, 372 ARRAY_SIZE(s3c2443_common_muxes)); 373 samsung_clk_register_div(ctx, s3c2443_common_dividers, 374 ARRAY_SIZE(s3c2443_common_dividers)); 375 samsung_clk_register_gate(ctx, s3c2443_common_gates, 376 ARRAY_SIZE(s3c2443_common_gates)); 377 samsung_clk_register_alias(ctx, s3c2443_common_aliases, 378 ARRAY_SIZE(s3c2443_common_aliases)); 379 380 /* Register SoC-specific clocks. */ 381 switch (current_soc) { 382 case S3C2450: 383 samsung_clk_register_div(ctx, s3c2450_dividers, 384 ARRAY_SIZE(s3c2450_dividers)); 385 samsung_clk_register_mux(ctx, s3c2450_muxes, 386 ARRAY_SIZE(s3c2450_muxes)); 387 samsung_clk_register_gate(ctx, s3c2450_gates, 388 ARRAY_SIZE(s3c2450_gates)); 389 samsung_clk_register_alias(ctx, s3c2450_aliases, 390 ARRAY_SIZE(s3c2450_aliases)); 391 fallthrough; /* as s3c2450 extends the s3c2416 clocks */ 392 case S3C2416: 393 samsung_clk_register_div(ctx, s3c2416_dividers, 394 ARRAY_SIZE(s3c2416_dividers)); 395 samsung_clk_register_mux(ctx, s3c2416_muxes, 396 ARRAY_SIZE(s3c2416_muxes)); 397 samsung_clk_register_gate(ctx, s3c2416_gates, 398 ARRAY_SIZE(s3c2416_gates)); 399 samsung_clk_register_alias(ctx, s3c2416_aliases, 400 ARRAY_SIZE(s3c2416_aliases)); 401 break; 402 case S3C2443: 403 samsung_clk_register_div(ctx, s3c2443_dividers, 404 ARRAY_SIZE(s3c2443_dividers)); 405 samsung_clk_register_gate(ctx, s3c2443_gates, 406 ARRAY_SIZE(s3c2443_gates)); 407 samsung_clk_register_alias(ctx, s3c2443_aliases, 408 ARRAY_SIZE(s3c2443_aliases)); 409 break; 410 } 411 412 samsung_clk_sleep_init(reg_base, s3c2443_clk_regs, 413 ARRAY_SIZE(s3c2443_clk_regs)); 414 415 samsung_clk_of_add_provider(np, ctx); 416 417 ret = register_restart_handler(&s3c2443_restart_handler); 418 if (ret) 419 pr_warn("cannot register restart handler, %d\n", ret); 420} 421 422static void __init s3c2416_clk_init(struct device_node *np) 423{ 424 s3c2443_common_clk_init(np, 0, S3C2416, NULL); 425} 426CLK_OF_DECLARE(s3c2416_clk, "samsung,s3c2416-clock", s3c2416_clk_init); 427 428static void __init s3c2443_clk_init(struct device_node *np) 429{ 430 s3c2443_common_clk_init(np, 0, S3C2443, NULL); 431} 432CLK_OF_DECLARE(s3c2443_clk, "samsung,s3c2443-clock", s3c2443_clk_init); 433 434static void __init s3c2450_clk_init(struct device_node *np) 435{ 436 s3c2443_common_clk_init(np, 0, S3C2450, NULL); 437} 438CLK_OF_DECLARE(s3c2450_clk, "samsung,s3c2450-clock", s3c2450_clk_init); 439