1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de> 4 * 5 * Common Clock Framework support for S3C2412 and S3C2413. 6 */ 7 8#include <linux/clk-provider.h> 9#include <linux/clk/samsung.h> 10#include <linux/io.h> 11#include <linux/of.h> 12#include <linux/of_address.h> 13#include <linux/reboot.h> 14 15#include <dt-bindings/clock/s3c2412.h> 16 17#include "clk.h" 18#include "clk-pll.h" 19 20#define LOCKTIME 0x00 21#define MPLLCON 0x04 22#define UPLLCON 0x08 23#define CLKCON 0x0c 24#define CLKDIVN 0x14 25#define CLKSRC 0x1c 26#define SWRST 0x30 27 28static void __iomem *reg_base; 29 30/* 31 * list of controller registers to be saved and restored during a 32 * suspend/resume cycle. 33 */ 34static unsigned long s3c2412_clk_regs[] __initdata = { 35 LOCKTIME, 36 MPLLCON, 37 UPLLCON, 38 CLKCON, 39 CLKDIVN, 40 CLKSRC, 41}; 42 43static struct clk_div_table divxti_d[] = { 44 { .val = 0, .div = 1 }, 45 { .val = 1, .div = 2 }, 46 { .val = 2, .div = 4 }, 47 { .val = 3, .div = 6 }, 48 { .val = 4, .div = 8 }, 49 { .val = 5, .div = 10 }, 50 { .val = 6, .div = 12 }, 51 { .val = 7, .div = 14 }, 52 { /* sentinel */ }, 53}; 54 55static struct samsung_div_clock s3c2412_dividers[] __initdata = { 56 DIV_T(0, "div_xti", "xti", CLKSRC, 0, 3, divxti_d), 57 DIV(0, "div_cam", "mux_cam", CLKDIVN, 16, 4), 58 DIV(0, "div_i2s", "mux_i2s", CLKDIVN, 12, 4), 59 DIV(0, "div_uart", "mux_uart", CLKDIVN, 8, 4), 60 DIV(0, "div_usb", "mux_usb", CLKDIVN, 6, 1), 61 DIV(0, "div_hclk_half", "hclk", CLKDIVN, 5, 1), 62 DIV(ARMDIV, "armdiv", "msysclk", CLKDIVN, 3, 1), 63 DIV(PCLK, "pclk", "hclk", CLKDIVN, 2, 1), 64 DIV(HCLK, "hclk", "armdiv", CLKDIVN, 0, 2), 65}; 66 67static struct samsung_fixed_factor_clock s3c2412_ffactor[] __initdata = { 68 FFACTOR(0, "ff_hclk", "hclk", 2, 1, CLK_SET_RATE_PARENT), 69}; 70 71/* 72 * The first two use the OM[4] setting, which is not readable from 73 * software, so assume it is set to xti. 74 */ 75PNAME(erefclk_p) = { "xti", "xti", "xti", "ext" }; 76PNAME(urefclk_p) = { "xti", "xti", "xti", "ext" }; 77 78PNAME(camclk_p) = { "usysclk", "hclk" }; 79PNAME(usbclk_p) = { "usysclk", "hclk" }; 80PNAME(i2sclk_p) = { "erefclk", "mpll" }; 81PNAME(uartclk_p) = { "erefclk", "mpll" }; 82PNAME(usysclk_p) = { "urefclk", "upll" }; 83PNAME(msysclk_p) = { "mdivclk", "mpll" }; 84PNAME(mdivclk_p) = { "xti", "div_xti" }; 85PNAME(armclk_p) = { "armdiv", "hclk" }; 86 87static struct samsung_mux_clock s3c2412_muxes[] __initdata = { 88 MUX(0, "erefclk", erefclk_p, CLKSRC, 14, 2), 89 MUX(0, "urefclk", urefclk_p, CLKSRC, 12, 2), 90 MUX(0, "mux_cam", camclk_p, CLKSRC, 11, 1), 91 MUX(0, "mux_usb", usbclk_p, CLKSRC, 10, 1), 92 MUX(0, "mux_i2s", i2sclk_p, CLKSRC, 9, 1), 93 MUX(0, "mux_uart", uartclk_p, CLKSRC, 8, 1), 94 MUX(USYSCLK, "usysclk", usysclk_p, CLKSRC, 5, 1), 95 MUX(MSYSCLK, "msysclk", msysclk_p, CLKSRC, 4, 1), 96 MUX(MDIVCLK, "mdivclk", mdivclk_p, CLKSRC, 3, 1), 97 MUX(ARMCLK, "armclk", armclk_p, CLKDIVN, 4, 1), 98}; 99 100static struct samsung_pll_clock s3c2412_plls[] __initdata = { 101 PLL(pll_s3c2440_mpll, MPLL, "mpll", "xti", LOCKTIME, MPLLCON, NULL), 102 PLL(pll_s3c2410_upll, UPLL, "upll", "urefclk", LOCKTIME, UPLLCON, NULL), 103}; 104 105static struct samsung_gate_clock s3c2412_gates[] __initdata = { 106 GATE(PCLK_WDT, "wdt", "pclk", CLKCON, 28, 0, 0), 107 GATE(PCLK_SPI, "spi", "pclk", CLKCON, 27, 0, 0), 108 GATE(PCLK_I2S, "i2s", "pclk", CLKCON, 26, 0, 0), 109 GATE(PCLK_I2C, "i2c", "pclk", CLKCON, 25, 0, 0), 110 GATE(PCLK_ADC, "adc", "pclk", CLKCON, 24, 0, 0), 111 GATE(PCLK_RTC, "rtc", "pclk", CLKCON, 23, 0, 0), 112 GATE(PCLK_GPIO, "gpio", "pclk", CLKCON, 22, CLK_IGNORE_UNUSED, 0), 113 GATE(PCLK_UART2, "uart2", "pclk", CLKCON, 21, 0, 0), 114 GATE(PCLK_UART1, "uart1", "pclk", CLKCON, 20, 0, 0), 115 GATE(PCLK_UART0, "uart0", "pclk", CLKCON, 19, 0, 0), 116 GATE(PCLK_SDI, "sdi", "pclk", CLKCON, 18, 0, 0), 117 GATE(PCLK_PWM, "pwm", "pclk", CLKCON, 17, 0, 0), 118 GATE(PCLK_USBD, "usb-device", "pclk", CLKCON, 16, 0, 0), 119 GATE(SCLK_CAM, "sclk_cam", "div_cam", CLKCON, 15, 0, 0), 120 GATE(SCLK_UART, "sclk_uart", "div_uart", CLKCON, 14, 0, 0), 121 GATE(SCLK_I2S, "sclk_i2s", "div_i2s", CLKCON, 13, 0, 0), 122 GATE(SCLK_USBH, "sclk_usbh", "div_usb", CLKCON, 12, 0, 0), 123 GATE(SCLK_USBD, "sclk_usbd", "div_usb", CLKCON, 11, 0, 0), 124 GATE(HCLK_HALF, "hclk_half", "div_hclk_half", CLKCON, 10, CLK_IGNORE_UNUSED, 0), 125 GATE(HCLK_X2, "hclkx2", "ff_hclk", CLKCON, 9, CLK_IGNORE_UNUSED, 0), 126 GATE(HCLK_SDRAM, "sdram", "hclk", CLKCON, 8, CLK_IGNORE_UNUSED, 0), 127 GATE(HCLK_USBH, "usb-host", "hclk", CLKCON, 6, 0, 0), 128 GATE(HCLK_LCD, "lcd", "hclk", CLKCON, 5, 0, 0), 129 GATE(HCLK_NAND, "nand", "hclk", CLKCON, 4, 0, 0), 130 GATE(HCLK_DMA3, "dma3", "hclk", CLKCON, 3, CLK_IGNORE_UNUSED, 0), 131 GATE(HCLK_DMA2, "dma2", "hclk", CLKCON, 2, CLK_IGNORE_UNUSED, 0), 132 GATE(HCLK_DMA1, "dma1", "hclk", CLKCON, 1, CLK_IGNORE_UNUSED, 0), 133 GATE(HCLK_DMA0, "dma0", "hclk", CLKCON, 0, CLK_IGNORE_UNUSED, 0), 134}; 135 136static struct samsung_clock_alias s3c2412_aliases[] __initdata = { 137 ALIAS(PCLK_UART0, "s3c2412-uart.0", "uart"), 138 ALIAS(PCLK_UART1, "s3c2412-uart.1", "uart"), 139 ALIAS(PCLK_UART2, "s3c2412-uart.2", "uart"), 140 ALIAS(PCLK_UART0, "s3c2412-uart.0", "clk_uart_baud2"), 141 ALIAS(PCLK_UART1, "s3c2412-uart.1", "clk_uart_baud2"), 142 ALIAS(PCLK_UART2, "s3c2412-uart.2", "clk_uart_baud2"), 143 ALIAS(SCLK_UART, NULL, "clk_uart_baud3"), 144 ALIAS(PCLK_I2C, "s3c2410-i2c.0", "i2c"), 145 ALIAS(PCLK_ADC, NULL, "adc"), 146 ALIAS(PCLK_RTC, NULL, "rtc"), 147 ALIAS(PCLK_PWM, NULL, "timers"), 148 ALIAS(HCLK_LCD, NULL, "lcd"), 149 ALIAS(PCLK_USBD, NULL, "usb-device"), 150 ALIAS(SCLK_USBD, NULL, "usb-bus-gadget"), 151 ALIAS(HCLK_USBH, NULL, "usb-host"), 152 ALIAS(SCLK_USBH, NULL, "usb-bus-host"), 153 ALIAS(ARMCLK, NULL, "armclk"), 154 ALIAS(HCLK, NULL, "hclk"), 155 ALIAS(MPLL, NULL, "mpll"), 156 ALIAS(MSYSCLK, NULL, "fclk"), 157}; 158 159static int s3c2412_restart(struct notifier_block *this, 160 unsigned long mode, void *cmd) 161{ 162 /* errata "Watch-dog/Software Reset Problem" specifies that 163 * this reset must be done with the SYSCLK sourced from 164 * EXTCLK instead of FOUT to avoid a glitch in the reset 165 * mechanism. 166 * 167 * See the watchdog section of the S3C2412 manual for more 168 * information on this fix. 169 */ 170 171 __raw_writel(0x00, reg_base + CLKSRC); 172 __raw_writel(0x533C2412, reg_base + SWRST); 173 return NOTIFY_DONE; 174} 175 176static struct notifier_block s3c2412_restart_handler = { 177 .notifier_call = s3c2412_restart, 178 .priority = 129, 179}; 180 181/* 182 * fixed rate clocks generated outside the soc 183 * Only necessary until the devicetree-move is complete 184 */ 185#define XTI 1 186static struct samsung_fixed_rate_clock s3c2412_common_frate_clks[] __initdata = { 187 FRATE(XTI, "xti", NULL, 0, 0), 188 FRATE(0, "ext", NULL, 0, 0), 189}; 190 191static void __init s3c2412_common_clk_register_fixed_ext( 192 struct samsung_clk_provider *ctx, 193 unsigned long xti_f, unsigned long ext_f) 194{ 195 /* xtal alias is necessary for the current cpufreq driver */ 196 struct samsung_clock_alias xti_alias = ALIAS(XTI, NULL, "xtal"); 197 198 s3c2412_common_frate_clks[0].fixed_rate = xti_f; 199 s3c2412_common_frate_clks[1].fixed_rate = ext_f; 200 samsung_clk_register_fixed_rate(ctx, s3c2412_common_frate_clks, 201 ARRAY_SIZE(s3c2412_common_frate_clks)); 202 203 samsung_clk_register_alias(ctx, &xti_alias, 1); 204} 205 206void __init s3c2412_common_clk_init(struct device_node *np, unsigned long xti_f, 207 unsigned long ext_f, void __iomem *base) 208{ 209 struct samsung_clk_provider *ctx; 210 int ret; 211 reg_base = base; 212 213 if (np) { 214 reg_base = of_iomap(np, 0); 215 if (!reg_base) 216 panic("%s: failed to map registers\n", __func__); 217 } 218 219 ctx = samsung_clk_init(np, reg_base, NR_CLKS); 220 221 /* Register external clocks only in non-dt cases */ 222 if (!np) 223 s3c2412_common_clk_register_fixed_ext(ctx, xti_f, ext_f); 224 225 /* Register PLLs. */ 226 samsung_clk_register_pll(ctx, s3c2412_plls, ARRAY_SIZE(s3c2412_plls), 227 reg_base); 228 229 /* Register common internal clocks. */ 230 samsung_clk_register_mux(ctx, s3c2412_muxes, ARRAY_SIZE(s3c2412_muxes)); 231 samsung_clk_register_div(ctx, s3c2412_dividers, 232 ARRAY_SIZE(s3c2412_dividers)); 233 samsung_clk_register_gate(ctx, s3c2412_gates, 234 ARRAY_SIZE(s3c2412_gates)); 235 samsung_clk_register_fixed_factor(ctx, s3c2412_ffactor, 236 ARRAY_SIZE(s3c2412_ffactor)); 237 samsung_clk_register_alias(ctx, s3c2412_aliases, 238 ARRAY_SIZE(s3c2412_aliases)); 239 240 samsung_clk_sleep_init(reg_base, s3c2412_clk_regs, 241 ARRAY_SIZE(s3c2412_clk_regs)); 242 243 samsung_clk_of_add_provider(np, ctx); 244 245 ret = register_restart_handler(&s3c2412_restart_handler); 246 if (ret) 247 pr_warn("cannot register restart handler, %d\n", ret); 248} 249 250static void __init s3c2412_clk_init(struct device_node *np) 251{ 252 s3c2412_common_clk_init(np, 0, 0, NULL); 253} 254CLK_OF_DECLARE(s3c2412_clk, "samsung,s3c2412-clock", s3c2412_clk_init); 255