1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de> 4 * 5 * Common Clock Framework support for s3c24xx external clock output. 6 */ 7 8#include <linux/clkdev.h> 9#include <linux/slab.h> 10#include <linux/clk.h> 11#include <linux/clk-provider.h> 12#include <linux/io.h> 13#include <linux/platform_device.h> 14#include <linux/platform_data/clk-s3c2410.h> 15#include <linux/module.h> 16#include "clk.h" 17 18#define MUX_DCLK0 0 19#define MUX_DCLK1 1 20#define DIV_DCLK0 2 21#define DIV_DCLK1 3 22#define GATE_DCLK0 4 23#define GATE_DCLK1 5 24#define MUX_CLKOUT0 6 25#define MUX_CLKOUT1 7 26#define DCLK_MAX_CLKS (MUX_CLKOUT1 + 1) 27 28enum supported_socs { 29 S3C2410, 30 S3C2412, 31 S3C2440, 32 S3C2443, 33}; 34 35struct s3c24xx_dclk_drv_data { 36 const char **clkout0_parent_names; 37 int clkout0_num_parents; 38 const char **clkout1_parent_names; 39 int clkout1_num_parents; 40 const char **mux_parent_names; 41 int mux_num_parents; 42}; 43 44/* 45 * Clock for output-parent selection in misccr 46 */ 47 48struct s3c24xx_clkout { 49 struct clk_hw hw; 50 u32 mask; 51 u8 shift; 52 unsigned int (*modify_misccr)(unsigned int clr, unsigned int chg); 53}; 54 55#define to_s3c24xx_clkout(_hw) container_of(_hw, struct s3c24xx_clkout, hw) 56 57static u8 s3c24xx_clkout_get_parent(struct clk_hw *hw) 58{ 59 struct s3c24xx_clkout *clkout = to_s3c24xx_clkout(hw); 60 int num_parents = clk_hw_get_num_parents(hw); 61 u32 val; 62 63 val = clkout->modify_misccr(0, 0) >> clkout->shift; 64 val >>= clkout->shift; 65 val &= clkout->mask; 66 67 if (val >= num_parents) 68 return -EINVAL; 69 70 return val; 71} 72 73static int s3c24xx_clkout_set_parent(struct clk_hw *hw, u8 index) 74{ 75 struct s3c24xx_clkout *clkout = to_s3c24xx_clkout(hw); 76 77 clkout->modify_misccr((clkout->mask << clkout->shift), 78 (index << clkout->shift)); 79 80 return 0; 81} 82 83static const struct clk_ops s3c24xx_clkout_ops = { 84 .get_parent = s3c24xx_clkout_get_parent, 85 .set_parent = s3c24xx_clkout_set_parent, 86 .determine_rate = __clk_mux_determine_rate, 87}; 88 89static struct clk_hw *s3c24xx_register_clkout(struct device *dev, 90 const char *name, const char **parent_names, u8 num_parents, 91 u8 shift, u32 mask) 92{ 93 struct s3c2410_clk_platform_data *pdata = dev_get_platdata(dev); 94 struct s3c24xx_clkout *clkout; 95 struct clk_init_data init; 96 int ret; 97 98 if (!pdata) 99 return ERR_PTR(-EINVAL); 100 101 /* allocate the clkout */ 102 clkout = kzalloc(sizeof(*clkout), GFP_KERNEL); 103 if (!clkout) 104 return ERR_PTR(-ENOMEM); 105 106 init.name = name; 107 init.ops = &s3c24xx_clkout_ops; 108 init.flags = 0; 109 init.parent_names = parent_names; 110 init.num_parents = num_parents; 111 112 clkout->shift = shift; 113 clkout->mask = mask; 114 clkout->hw.init = &init; 115 clkout->modify_misccr = pdata->modify_misccr; 116 117 ret = clk_hw_register(dev, &clkout->hw); 118 if (ret) 119 return ERR_PTR(ret); 120 121 return &clkout->hw; 122} 123 124/* 125 * dclk and clkout init 126 */ 127 128struct s3c24xx_dclk { 129 struct device *dev; 130 void __iomem *base; 131 struct notifier_block dclk0_div_change_nb; 132 struct notifier_block dclk1_div_change_nb; 133 spinlock_t dclk_lock; 134 unsigned long reg_save; 135 /* clk_data must be the last entry in the structure */ 136 struct clk_hw_onecell_data clk_data; 137}; 138 139#define to_s3c24xx_dclk0(x) \ 140 container_of(x, struct s3c24xx_dclk, dclk0_div_change_nb) 141 142#define to_s3c24xx_dclk1(x) \ 143 container_of(x, struct s3c24xx_dclk, dclk1_div_change_nb) 144 145static const char *dclk_s3c2410_p[] = { "pclk", "uclk" }; 146static const char *clkout0_s3c2410_p[] = { "mpll", "upll", "fclk", "hclk", "pclk", 147 "gate_dclk0" }; 148static const char *clkout1_s3c2410_p[] = { "mpll", "upll", "fclk", "hclk", "pclk", 149 "gate_dclk1" }; 150 151static const char *clkout0_s3c2412_p[] = { "mpll", "upll", "rtc_clkout", 152 "hclk", "pclk", "gate_dclk0" }; 153static const char *clkout1_s3c2412_p[] = { "xti", "upll", "fclk", "hclk", "pclk", 154 "gate_dclk1" }; 155 156static const char *clkout0_s3c2440_p[] = { "xti", "upll", "fclk", "hclk", "pclk", 157 "gate_dclk0" }; 158static const char *clkout1_s3c2440_p[] = { "mpll", "upll", "rtc_clkout", 159 "hclk", "pclk", "gate_dclk1" }; 160 161static const char *dclk_s3c2443_p[] = { "pclk", "epll" }; 162static const char *clkout0_s3c2443_p[] = { "xti", "epll", "armclk", "hclk", "pclk", 163 "gate_dclk0" }; 164static const char *clkout1_s3c2443_p[] = { "dummy", "epll", "rtc_clkout", 165 "hclk", "pclk", "gate_dclk1" }; 166 167#define DCLKCON_DCLK_DIV_MASK 0xf 168#define DCLKCON_DCLK0_DIV_SHIFT 4 169#define DCLKCON_DCLK0_CMP_SHIFT 8 170#define DCLKCON_DCLK1_DIV_SHIFT 20 171#define DCLKCON_DCLK1_CMP_SHIFT 24 172 173static void s3c24xx_dclk_update_cmp(struct s3c24xx_dclk *s3c24xx_dclk, 174 int div_shift, int cmp_shift) 175{ 176 unsigned long flags = 0; 177 u32 dclk_con, div, cmp; 178 179 spin_lock_irqsave(&s3c24xx_dclk->dclk_lock, flags); 180 181 dclk_con = readl_relaxed(s3c24xx_dclk->base); 182 183 div = ((dclk_con >> div_shift) & DCLKCON_DCLK_DIV_MASK) + 1; 184 cmp = ((div + 1) / 2) - 1; 185 186 dclk_con &= ~(DCLKCON_DCLK_DIV_MASK << cmp_shift); 187 dclk_con |= (cmp << cmp_shift); 188 189 writel_relaxed(dclk_con, s3c24xx_dclk->base); 190 191 spin_unlock_irqrestore(&s3c24xx_dclk->dclk_lock, flags); 192} 193 194static int s3c24xx_dclk0_div_notify(struct notifier_block *nb, 195 unsigned long event, void *data) 196{ 197 struct s3c24xx_dclk *s3c24xx_dclk = to_s3c24xx_dclk0(nb); 198 199 if (event == POST_RATE_CHANGE) { 200 s3c24xx_dclk_update_cmp(s3c24xx_dclk, 201 DCLKCON_DCLK0_DIV_SHIFT, DCLKCON_DCLK0_CMP_SHIFT); 202 } 203 204 return NOTIFY_DONE; 205} 206 207static int s3c24xx_dclk1_div_notify(struct notifier_block *nb, 208 unsigned long event, void *data) 209{ 210 struct s3c24xx_dclk *s3c24xx_dclk = to_s3c24xx_dclk1(nb); 211 212 if (event == POST_RATE_CHANGE) { 213 s3c24xx_dclk_update_cmp(s3c24xx_dclk, 214 DCLKCON_DCLK1_DIV_SHIFT, DCLKCON_DCLK1_CMP_SHIFT); 215 } 216 217 return NOTIFY_DONE; 218} 219 220#ifdef CONFIG_PM_SLEEP 221static int s3c24xx_dclk_suspend(struct device *dev) 222{ 223 struct s3c24xx_dclk *s3c24xx_dclk = dev_get_drvdata(dev); 224 225 s3c24xx_dclk->reg_save = readl_relaxed(s3c24xx_dclk->base); 226 return 0; 227} 228 229static int s3c24xx_dclk_resume(struct device *dev) 230{ 231 struct s3c24xx_dclk *s3c24xx_dclk = dev_get_drvdata(dev); 232 233 writel_relaxed(s3c24xx_dclk->reg_save, s3c24xx_dclk->base); 234 return 0; 235} 236#endif 237 238static SIMPLE_DEV_PM_OPS(s3c24xx_dclk_pm_ops, 239 s3c24xx_dclk_suspend, s3c24xx_dclk_resume); 240 241static int s3c24xx_dclk_probe(struct platform_device *pdev) 242{ 243 struct s3c24xx_dclk *s3c24xx_dclk; 244 struct s3c24xx_dclk_drv_data *dclk_variant; 245 struct clk_hw **clk_table; 246 int ret, i; 247 248 s3c24xx_dclk = devm_kzalloc(&pdev->dev, 249 struct_size(s3c24xx_dclk, clk_data.hws, 250 DCLK_MAX_CLKS), 251 GFP_KERNEL); 252 if (!s3c24xx_dclk) 253 return -ENOMEM; 254 255 clk_table = s3c24xx_dclk->clk_data.hws; 256 257 s3c24xx_dclk->dev = &pdev->dev; 258 s3c24xx_dclk->clk_data.num = DCLK_MAX_CLKS; 259 platform_set_drvdata(pdev, s3c24xx_dclk); 260 spin_lock_init(&s3c24xx_dclk->dclk_lock); 261 262 s3c24xx_dclk->base = devm_platform_ioremap_resource(pdev, 0); 263 if (IS_ERR(s3c24xx_dclk->base)) 264 return PTR_ERR(s3c24xx_dclk->base); 265 266 dclk_variant = (struct s3c24xx_dclk_drv_data *) 267 platform_get_device_id(pdev)->driver_data; 268 269 270 clk_table[MUX_DCLK0] = clk_hw_register_mux(&pdev->dev, "mux_dclk0", 271 dclk_variant->mux_parent_names, 272 dclk_variant->mux_num_parents, 0, 273 s3c24xx_dclk->base, 1, 1, 0, 274 &s3c24xx_dclk->dclk_lock); 275 clk_table[MUX_DCLK1] = clk_hw_register_mux(&pdev->dev, "mux_dclk1", 276 dclk_variant->mux_parent_names, 277 dclk_variant->mux_num_parents, 0, 278 s3c24xx_dclk->base, 17, 1, 0, 279 &s3c24xx_dclk->dclk_lock); 280 281 clk_table[DIV_DCLK0] = clk_hw_register_divider(&pdev->dev, "div_dclk0", 282 "mux_dclk0", 0, s3c24xx_dclk->base, 283 4, 4, 0, &s3c24xx_dclk->dclk_lock); 284 clk_table[DIV_DCLK1] = clk_hw_register_divider(&pdev->dev, "div_dclk1", 285 "mux_dclk1", 0, s3c24xx_dclk->base, 286 20, 4, 0, &s3c24xx_dclk->dclk_lock); 287 288 clk_table[GATE_DCLK0] = clk_hw_register_gate(&pdev->dev, "gate_dclk0", 289 "div_dclk0", CLK_SET_RATE_PARENT, 290 s3c24xx_dclk->base, 0, 0, 291 &s3c24xx_dclk->dclk_lock); 292 clk_table[GATE_DCLK1] = clk_hw_register_gate(&pdev->dev, "gate_dclk1", 293 "div_dclk1", CLK_SET_RATE_PARENT, 294 s3c24xx_dclk->base, 16, 0, 295 &s3c24xx_dclk->dclk_lock); 296 297 clk_table[MUX_CLKOUT0] = s3c24xx_register_clkout(&pdev->dev, 298 "clkout0", dclk_variant->clkout0_parent_names, 299 dclk_variant->clkout0_num_parents, 4, 7); 300 clk_table[MUX_CLKOUT1] = s3c24xx_register_clkout(&pdev->dev, 301 "clkout1", dclk_variant->clkout1_parent_names, 302 dclk_variant->clkout1_num_parents, 8, 7); 303 304 for (i = 0; i < DCLK_MAX_CLKS; i++) 305 if (IS_ERR(clk_table[i])) { 306 dev_err(&pdev->dev, "clock %d failed to register\n", i); 307 ret = PTR_ERR(clk_table[i]); 308 goto err_clk_register; 309 } 310 311 ret = clk_hw_register_clkdev(clk_table[MUX_DCLK0], "dclk0", NULL); 312 if (!ret) 313 ret = clk_hw_register_clkdev(clk_table[MUX_DCLK1], "dclk1", 314 NULL); 315 if (!ret) 316 ret = clk_hw_register_clkdev(clk_table[MUX_CLKOUT0], 317 "clkout0", NULL); 318 if (!ret) 319 ret = clk_hw_register_clkdev(clk_table[MUX_CLKOUT1], 320 "clkout1", NULL); 321 if (ret) { 322 dev_err(&pdev->dev, "failed to register aliases, %d\n", ret); 323 goto err_clk_register; 324 } 325 326 s3c24xx_dclk->dclk0_div_change_nb.notifier_call = 327 s3c24xx_dclk0_div_notify; 328 329 s3c24xx_dclk->dclk1_div_change_nb.notifier_call = 330 s3c24xx_dclk1_div_notify; 331 332 ret = clk_notifier_register(clk_table[DIV_DCLK0]->clk, 333 &s3c24xx_dclk->dclk0_div_change_nb); 334 if (ret) 335 goto err_clk_register; 336 337 ret = clk_notifier_register(clk_table[DIV_DCLK1]->clk, 338 &s3c24xx_dclk->dclk1_div_change_nb); 339 if (ret) 340 goto err_dclk_notify; 341 342 return 0; 343 344err_dclk_notify: 345 clk_notifier_unregister(clk_table[DIV_DCLK0]->clk, 346 &s3c24xx_dclk->dclk0_div_change_nb); 347err_clk_register: 348 for (i = 0; i < DCLK_MAX_CLKS; i++) 349 if (clk_table[i] && !IS_ERR(clk_table[i])) 350 clk_hw_unregister(clk_table[i]); 351 352 return ret; 353} 354 355static int s3c24xx_dclk_remove(struct platform_device *pdev) 356{ 357 struct s3c24xx_dclk *s3c24xx_dclk = platform_get_drvdata(pdev); 358 struct clk_hw **clk_table = s3c24xx_dclk->clk_data.hws; 359 int i; 360 361 clk_notifier_unregister(clk_table[DIV_DCLK1]->clk, 362 &s3c24xx_dclk->dclk1_div_change_nb); 363 clk_notifier_unregister(clk_table[DIV_DCLK0]->clk, 364 &s3c24xx_dclk->dclk0_div_change_nb); 365 366 for (i = 0; i < DCLK_MAX_CLKS; i++) 367 clk_hw_unregister(clk_table[i]); 368 369 return 0; 370} 371 372static struct s3c24xx_dclk_drv_data dclk_variants[] = { 373 [S3C2410] = { 374 .clkout0_parent_names = clkout0_s3c2410_p, 375 .clkout0_num_parents = ARRAY_SIZE(clkout0_s3c2410_p), 376 .clkout1_parent_names = clkout1_s3c2410_p, 377 .clkout1_num_parents = ARRAY_SIZE(clkout1_s3c2410_p), 378 .mux_parent_names = dclk_s3c2410_p, 379 .mux_num_parents = ARRAY_SIZE(dclk_s3c2410_p), 380 }, 381 [S3C2412] = { 382 .clkout0_parent_names = clkout0_s3c2412_p, 383 .clkout0_num_parents = ARRAY_SIZE(clkout0_s3c2412_p), 384 .clkout1_parent_names = clkout1_s3c2412_p, 385 .clkout1_num_parents = ARRAY_SIZE(clkout1_s3c2412_p), 386 .mux_parent_names = dclk_s3c2410_p, 387 .mux_num_parents = ARRAY_SIZE(dclk_s3c2410_p), 388 }, 389 [S3C2440] = { 390 .clkout0_parent_names = clkout0_s3c2440_p, 391 .clkout0_num_parents = ARRAY_SIZE(clkout0_s3c2440_p), 392 .clkout1_parent_names = clkout1_s3c2440_p, 393 .clkout1_num_parents = ARRAY_SIZE(clkout1_s3c2440_p), 394 .mux_parent_names = dclk_s3c2410_p, 395 .mux_num_parents = ARRAY_SIZE(dclk_s3c2410_p), 396 }, 397 [S3C2443] = { 398 .clkout0_parent_names = clkout0_s3c2443_p, 399 .clkout0_num_parents = ARRAY_SIZE(clkout0_s3c2443_p), 400 .clkout1_parent_names = clkout1_s3c2443_p, 401 .clkout1_num_parents = ARRAY_SIZE(clkout1_s3c2443_p), 402 .mux_parent_names = dclk_s3c2443_p, 403 .mux_num_parents = ARRAY_SIZE(dclk_s3c2443_p), 404 }, 405}; 406 407static const struct platform_device_id s3c24xx_dclk_driver_ids[] = { 408 { 409 .name = "s3c2410-dclk", 410 .driver_data = (kernel_ulong_t)&dclk_variants[S3C2410], 411 }, { 412 .name = "s3c2412-dclk", 413 .driver_data = (kernel_ulong_t)&dclk_variants[S3C2412], 414 }, { 415 .name = "s3c2440-dclk", 416 .driver_data = (kernel_ulong_t)&dclk_variants[S3C2440], 417 }, { 418 .name = "s3c2443-dclk", 419 .driver_data = (kernel_ulong_t)&dclk_variants[S3C2443], 420 }, 421 { } 422}; 423 424MODULE_DEVICE_TABLE(platform, s3c24xx_dclk_driver_ids); 425 426static struct platform_driver s3c24xx_dclk_driver = { 427 .driver = { 428 .name = "s3c24xx-dclk", 429 .pm = &s3c24xx_dclk_pm_ops, 430 .suppress_bind_attrs = true, 431 }, 432 .probe = s3c24xx_dclk_probe, 433 .remove = s3c24xx_dclk_remove, 434 .id_table = s3c24xx_dclk_driver_ids, 435}; 436module_platform_driver(s3c24xx_dclk_driver); 437 438MODULE_LICENSE("GPL v2"); 439MODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>"); 440MODULE_DESCRIPTION("Driver for the S3C24XX external clock outputs"); 441