1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
4 * Copyright (c) 2013 Linaro Ltd.
5 *
6 * Common Clock Framework support for all PLL's in Samsung platforms
7*/
8
9#ifndef __SAMSUNG_CLK_PLL_H
10#define __SAMSUNG_CLK_PLL_H
11
12enum samsung_pll_type {
13	pll_2126,
14	pll_3000,
15	pll_35xx,
16	pll_36xx,
17	pll_2550,
18	pll_2650,
19	pll_4500,
20	pll_4502,
21	pll_4508,
22	pll_4600,
23	pll_4650,
24	pll_4650c,
25	pll_6552,
26	pll_6552_s3c2416,
27	pll_6553,
28	pll_s3c2410_mpll,
29	pll_s3c2410_upll,
30	pll_s3c2440_mpll,
31	pll_2550x,
32	pll_2550xx,
33	pll_2650x,
34	pll_2650xx,
35	pll_1450x,
36	pll_1451x,
37	pll_1452x,
38	pll_1460x,
39};
40
41#define PLL_RATE(_fin, _m, _p, _s, _k, _ks) \
42	((u64)(_fin) * (BIT(_ks) * (_m) + (_k)) / BIT(_ks) / ((_p) << (_s)))
43#define PLL_VALID_RATE(_fin, _fout, _m, _p, _s, _k, _ks) ((_fout) + \
44	BUILD_BUG_ON_ZERO(PLL_RATE(_fin, _m, _p, _s, _k, _ks) != (_fout)))
45
46#define PLL_35XX_RATE(_fin, _rate, _m, _p, _s)			\
47	{							\
48		.rate	=	PLL_VALID_RATE(_fin, _rate,	\
49				_m, _p, _s, 0, 16),		\
50		.mdiv	=	(_m),				\
51		.pdiv	=	(_p),				\
52		.sdiv	=	(_s),				\
53	}
54
55#define PLL_S3C2410_MPLL_RATE(_fin, _rate, _m, _p, _s)		\
56	{							\
57		.rate	=	PLL_VALID_RATE(_fin, _rate,	\
58				_m + 8, _p + 2, _s, 0, 16),	\
59		.mdiv	=	(_m),				\
60		.pdiv	=	(_p),				\
61		.sdiv	=	(_s),				\
62	}
63
64#define PLL_S3C2440_MPLL_RATE(_fin, _rate, _m, _p, _s)		\
65	{							\
66		.rate	=	PLL_VALID_RATE(_fin, _rate,	\
67				2 * (_m + 8), _p + 2, _s, 0, 16), \
68		.mdiv	=	(_m),				\
69		.pdiv	=	(_p),				\
70		.sdiv	=	(_s),				\
71	}
72
73#define PLL_36XX_RATE(_fin, _rate, _m, _p, _s, _k)		\
74	{							\
75		.rate	=	PLL_VALID_RATE(_fin, _rate,	\
76				_m, _p, _s, _k, 16),		\
77		.mdiv	=	(_m),				\
78		.pdiv	=	(_p),				\
79		.sdiv	=	(_s),				\
80		.kdiv	=	(_k),				\
81	}
82
83#define PLL_4508_RATE(_fin, _rate, _m, _p, _s, _afc)		\
84	{							\
85		.rate	=	PLL_VALID_RATE(_fin, _rate,	\
86				_m, _p, _s - 1, 0, 16),		\
87		.mdiv	=	(_m),				\
88		.pdiv	=	(_p),				\
89		.sdiv	=	(_s),				\
90		.afc	=	(_afc),				\
91	}
92
93#define PLL_4600_RATE(_fin, _rate, _m, _p, _s, _k, _vsel)	\
94	{							\
95		.rate	=	PLL_VALID_RATE(_fin, _rate,	\
96				_m, _p, _s, _k, 16),		\
97		.mdiv	=	(_m),				\
98		.pdiv	=	(_p),				\
99		.sdiv	=	(_s),				\
100		.kdiv	=	(_k),				\
101		.vsel	=	(_vsel),			\
102	}
103
104#define PLL_4650_RATE(_fin, _rate, _m, _p, _s, _k, _mfr, _mrr, _vsel) \
105	{							\
106		.rate	=	PLL_VALID_RATE(_fin, _rate,	\
107				_m, _p, _s, _k, 10),		\
108		.mdiv	=	(_m),				\
109		.pdiv	=	(_p),				\
110		.sdiv	=	(_s),				\
111		.kdiv	=	(_k),				\
112		.mfr	=	(_mfr),				\
113		.mrr	=	(_mrr),				\
114		.vsel	=	(_vsel),			\
115	}
116
117/* NOTE: Rate table should be kept sorted in descending order. */
118
119struct samsung_pll_rate_table {
120	unsigned int rate;
121	unsigned int pdiv;
122	unsigned int mdiv;
123	unsigned int sdiv;
124	unsigned int kdiv;
125	unsigned int afc;
126	unsigned int mfr;
127	unsigned int mrr;
128	unsigned int vsel;
129};
130
131#endif /* __SAMSUNG_CLK_PLL_H */
132