1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2017 Samsung Electronics Co., Ltd. 4 * Author: Marek Szyprowski <m.szyprowski@samsung.com> 5 * 6 * Common Clock Framework support for Exynos4412 ISP module. 7*/ 8 9#include <dt-bindings/clock/exynos4.h> 10#include <linux/slab.h> 11#include <linux/clk.h> 12#include <linux/clk-provider.h> 13#include <linux/of.h> 14#include <linux/platform_device.h> 15#include <linux/pm_runtime.h> 16 17#include "clk.h" 18 19/* Exynos4x12 specific registers, which belong to ISP power domain */ 20#define E4X12_DIV_ISP0 0x0300 21#define E4X12_DIV_ISP1 0x0304 22#define E4X12_GATE_ISP0 0x0800 23#define E4X12_GATE_ISP1 0x0804 24 25/* 26 * Support for CMU save/restore across system suspends 27 */ 28static struct samsung_clk_reg_dump *exynos4x12_save_isp; 29 30static const unsigned long exynos4x12_clk_isp_save[] __initconst = { 31 E4X12_DIV_ISP0, 32 E4X12_DIV_ISP1, 33 E4X12_GATE_ISP0, 34 E4X12_GATE_ISP1, 35}; 36 37static struct samsung_div_clock exynos4x12_isp_div_clks[] = { 38 DIV(CLK_ISP_DIV_ISP0, "div_isp0", "aclk200", E4X12_DIV_ISP0, 0, 3), 39 DIV(CLK_ISP_DIV_ISP1, "div_isp1", "aclk200", E4X12_DIV_ISP0, 4, 3), 40 DIV(CLK_ISP_DIV_MCUISP0, "div_mcuisp0", "aclk400_mcuisp", 41 E4X12_DIV_ISP1, 4, 3), 42 DIV(CLK_ISP_DIV_MCUISP1, "div_mcuisp1", "div_mcuisp0", 43 E4X12_DIV_ISP1, 8, 3), 44 DIV(0, "div_mpwm", "div_isp1", E4X12_DIV_ISP1, 0, 3), 45}; 46 47static struct samsung_gate_clock exynos4x12_isp_gate_clks[] = { 48 GATE(CLK_ISP_FIMC_ISP, "isp", "aclk200", E4X12_GATE_ISP0, 0, 0, 0), 49 GATE(CLK_ISP_FIMC_DRC, "drc", "aclk200", E4X12_GATE_ISP0, 1, 0, 0), 50 GATE(CLK_ISP_FIMC_FD, "fd", "aclk200", E4X12_GATE_ISP0, 2, 0, 0), 51 GATE(CLK_ISP_FIMC_LITE0, "lite0", "aclk200", E4X12_GATE_ISP0, 3, 0, 0), 52 GATE(CLK_ISP_FIMC_LITE1, "lite1", "aclk200", E4X12_GATE_ISP0, 4, 0, 0), 53 GATE(CLK_ISP_MCUISP, "mcuisp", "aclk200", E4X12_GATE_ISP0, 5, 0, 0), 54 GATE(CLK_ISP_GICISP, "gicisp", "aclk200", E4X12_GATE_ISP0, 7, 0, 0), 55 GATE(CLK_ISP_SMMU_ISP, "smmu_isp", "aclk200", E4X12_GATE_ISP0, 8, 0, 0), 56 GATE(CLK_ISP_SMMU_DRC, "smmu_drc", "aclk200", E4X12_GATE_ISP0, 9, 0, 0), 57 GATE(CLK_ISP_SMMU_FD, "smmu_fd", "aclk200", E4X12_GATE_ISP0, 10, 0, 0), 58 GATE(CLK_ISP_SMMU_LITE0, "smmu_lite0", "aclk200", E4X12_GATE_ISP0, 11, 59 0, 0), 60 GATE(CLK_ISP_SMMU_LITE1, "smmu_lite1", "aclk200", E4X12_GATE_ISP0, 12, 61 0, 0), 62 GATE(CLK_ISP_PPMUISPMX, "ppmuispmx", "aclk200", E4X12_GATE_ISP0, 20, 63 0, 0), 64 GATE(CLK_ISP_PPMUISPX, "ppmuispx", "aclk200", E4X12_GATE_ISP0, 21, 65 0, 0), 66 GATE(CLK_ISP_MCUCTL_ISP, "mcuctl_isp", "aclk200", E4X12_GATE_ISP0, 23, 67 0, 0), 68 GATE(CLK_ISP_MPWM_ISP, "mpwm_isp", "aclk200", E4X12_GATE_ISP0, 24, 69 0, 0), 70 GATE(CLK_ISP_I2C0_ISP, "i2c0_isp", "aclk200", E4X12_GATE_ISP0, 25, 71 0, 0), 72 GATE(CLK_ISP_I2C1_ISP, "i2c1_isp", "aclk200", E4X12_GATE_ISP0, 26, 73 0, 0), 74 GATE(CLK_ISP_MTCADC_ISP, "mtcadc_isp", "aclk200", E4X12_GATE_ISP0, 27, 75 0, 0), 76 GATE(CLK_ISP_PWM_ISP, "pwm_isp", "aclk200", E4X12_GATE_ISP0, 28, 0, 0), 77 GATE(CLK_ISP_WDT_ISP, "wdt_isp", "aclk200", E4X12_GATE_ISP0, 30, 0, 0), 78 GATE(CLK_ISP_UART_ISP, "uart_isp", "aclk200", E4X12_GATE_ISP0, 31, 79 0, 0), 80 GATE(CLK_ISP_ASYNCAXIM, "asyncaxim", "aclk200", E4X12_GATE_ISP1, 0, 81 0, 0), 82 GATE(CLK_ISP_SMMU_ISPCX, "smmu_ispcx", "aclk200", E4X12_GATE_ISP1, 4, 83 0, 0), 84 GATE(CLK_ISP_SPI0_ISP, "spi0_isp", "aclk200", E4X12_GATE_ISP1, 12, 85 0, 0), 86 GATE(CLK_ISP_SPI1_ISP, "spi1_isp", "aclk200", E4X12_GATE_ISP1, 13, 87 0, 0), 88}; 89 90static int __maybe_unused exynos4x12_isp_clk_suspend(struct device *dev) 91{ 92 struct samsung_clk_provider *ctx = dev_get_drvdata(dev); 93 94 samsung_clk_save(ctx->reg_base, exynos4x12_save_isp, 95 ARRAY_SIZE(exynos4x12_clk_isp_save)); 96 return 0; 97} 98 99static int __maybe_unused exynos4x12_isp_clk_resume(struct device *dev) 100{ 101 struct samsung_clk_provider *ctx = dev_get_drvdata(dev); 102 103 samsung_clk_restore(ctx->reg_base, exynos4x12_save_isp, 104 ARRAY_SIZE(exynos4x12_clk_isp_save)); 105 return 0; 106} 107 108static int __init exynos4x12_isp_clk_probe(struct platform_device *pdev) 109{ 110 struct samsung_clk_provider *ctx; 111 struct device *dev = &pdev->dev; 112 struct device_node *np = dev->of_node; 113 struct resource *res; 114 void __iomem *reg_base; 115 116 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 117 reg_base = devm_ioremap_resource(dev, res); 118 if (IS_ERR(reg_base)) { 119 dev_err(dev, "failed to map registers\n"); 120 return PTR_ERR(reg_base); 121 } 122 123 exynos4x12_save_isp = samsung_clk_alloc_reg_dump(exynos4x12_clk_isp_save, 124 ARRAY_SIZE(exynos4x12_clk_isp_save)); 125 if (!exynos4x12_save_isp) 126 return -ENOMEM; 127 128 ctx = samsung_clk_init(np, reg_base, CLK_NR_ISP_CLKS); 129 ctx->dev = dev; 130 131 platform_set_drvdata(pdev, ctx); 132 133 pm_runtime_set_active(dev); 134 pm_runtime_enable(dev); 135 pm_runtime_get_sync(dev); 136 137 samsung_clk_register_div(ctx, exynos4x12_isp_div_clks, 138 ARRAY_SIZE(exynos4x12_isp_div_clks)); 139 samsung_clk_register_gate(ctx, exynos4x12_isp_gate_clks, 140 ARRAY_SIZE(exynos4x12_isp_gate_clks)); 141 142 samsung_clk_of_add_provider(np, ctx); 143 pm_runtime_put(dev); 144 145 return 0; 146} 147 148static const struct of_device_id exynos4x12_isp_clk_of_match[] = { 149 { .compatible = "samsung,exynos4412-isp-clock", }, 150 { }, 151}; 152 153static const struct dev_pm_ops exynos4x12_isp_pm_ops = { 154 SET_RUNTIME_PM_OPS(exynos4x12_isp_clk_suspend, 155 exynos4x12_isp_clk_resume, NULL) 156 SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 157 pm_runtime_force_resume) 158}; 159 160static struct platform_driver exynos4x12_isp_clk_driver __refdata = { 161 .driver = { 162 .name = "exynos4x12-isp-clk", 163 .of_match_table = exynos4x12_isp_clk_of_match, 164 .suppress_bind_attrs = true, 165 .pm = &exynos4x12_isp_pm_ops, 166 }, 167 .probe = exynos4x12_isp_clk_probe, 168}; 169 170static int __init exynos4x12_isp_clk_init(void) 171{ 172 return platform_driver_register(&exynos4x12_isp_clk_driver); 173} 174core_initcall(exynos4x12_isp_clk_init); 175