1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * Copyright (c) 2016 Rockchip Electronics Co. Ltd. 4 * Author: Shawn Lin <shawn.lin@rock-chips.com> 5 * Andy Yan <andy.yan@rock-chips.com> 6 */ 7 8#include <linux/clk-provider.h> 9#include <linux/io.h> 10#include <linux/of.h> 11#include <linux/of_address.h> 12#include <linux/syscore_ops.h> 13#include <dt-bindings/clock/rv1108-cru.h> 14#include "clk.h" 15 16#define RV1108_GRF_SOC_STATUS0 0x480 17 18enum rv1108_plls { 19 apll, dpll, gpll, 20}; 21 22static struct rockchip_pll_rate_table rv1108_pll_rates[] = { 23 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ 24 RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0), 25 RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0), 26 RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0), 27 RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0), 28 RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0), 29 RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0), 30 RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0), 31 RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0), 32 RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0), 33 RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0), 34 RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0), 35 RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0), 36 RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0), 37 RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0), 38 RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0), 39 RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0), 40 RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0), 41 RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0), 42 RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0), 43 RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0), 44 RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0), 45 RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0), 46 RK3036_PLL_RATE( 984000000, 1, 82, 2, 1, 1, 0), 47 RK3036_PLL_RATE( 960000000, 1, 80, 2, 1, 1, 0), 48 RK3036_PLL_RATE( 936000000, 1, 78, 2, 1, 1, 0), 49 RK3036_PLL_RATE( 912000000, 1, 76, 2, 1, 1, 0), 50 RK3036_PLL_RATE( 900000000, 4, 300, 2, 1, 1, 0), 51 RK3036_PLL_RATE( 888000000, 1, 74, 2, 1, 1, 0), 52 RK3036_PLL_RATE( 864000000, 1, 72, 2, 1, 1, 0), 53 RK3036_PLL_RATE( 840000000, 1, 70, 2, 1, 1, 0), 54 RK3036_PLL_RATE( 816000000, 1, 68, 2, 1, 1, 0), 55 RK3036_PLL_RATE( 800000000, 6, 400, 2, 1, 1, 0), 56 RK3036_PLL_RATE( 700000000, 6, 350, 2, 1, 1, 0), 57 RK3036_PLL_RATE( 696000000, 1, 58, 2, 1, 1, 0), 58 RK3036_PLL_RATE( 600000000, 1, 75, 3, 1, 1, 0), 59 RK3036_PLL_RATE( 594000000, 2, 99, 2, 1, 1, 0), 60 RK3036_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0), 61 RK3036_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0), 62 RK3036_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0), 63 RK3036_PLL_RATE( 312000000, 1, 52, 2, 2, 1, 0), 64 RK3036_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0), 65 RK3036_PLL_RATE( 96000000, 1, 64, 4, 4, 1, 0), 66 { /* sentinel */ }, 67}; 68 69#define RV1108_DIV_CORE_MASK 0xf 70#define RV1108_DIV_CORE_SHIFT 4 71 72#define RV1108_CLKSEL0(_core_peri_div) \ 73 { \ 74 .reg = RV1108_CLKSEL_CON(1), \ 75 .val = HIWORD_UPDATE(_core_peri_div, RV1108_DIV_CORE_MASK,\ 76 RV1108_DIV_CORE_SHIFT) \ 77 } 78 79#define RV1108_CPUCLK_RATE(_prate, _core_peri_div) \ 80 { \ 81 .prate = _prate, \ 82 .divs = { \ 83 RV1108_CLKSEL0(_core_peri_div), \ 84 }, \ 85 } 86 87static struct rockchip_cpuclk_rate_table rv1108_cpuclk_rates[] __initdata = { 88 RV1108_CPUCLK_RATE(1608000000, 7), 89 RV1108_CPUCLK_RATE(1512000000, 7), 90 RV1108_CPUCLK_RATE(1488000000, 5), 91 RV1108_CPUCLK_RATE(1416000000, 5), 92 RV1108_CPUCLK_RATE(1392000000, 5), 93 RV1108_CPUCLK_RATE(1296000000, 5), 94 RV1108_CPUCLK_RATE(1200000000, 5), 95 RV1108_CPUCLK_RATE(1104000000, 5), 96 RV1108_CPUCLK_RATE(1008000000, 5), 97 RV1108_CPUCLK_RATE(912000000, 5), 98 RV1108_CPUCLK_RATE(816000000, 3), 99 RV1108_CPUCLK_RATE(696000000, 3), 100 RV1108_CPUCLK_RATE(600000000, 3), 101 RV1108_CPUCLK_RATE(500000000, 3), 102 RV1108_CPUCLK_RATE(408000000, 1), 103 RV1108_CPUCLK_RATE(312000000, 1), 104 RV1108_CPUCLK_RATE(216000000, 1), 105 RV1108_CPUCLK_RATE(96000000, 1), 106}; 107 108static const struct rockchip_cpuclk_reg_data rv1108_cpuclk_data = { 109 .core_reg = RV1108_CLKSEL_CON(0), 110 .div_core_shift = 0, 111 .div_core_mask = 0x1f, 112 .mux_core_alt = 1, 113 .mux_core_main = 0, 114 .mux_core_shift = 8, 115 .mux_core_mask = 0x3, 116}; 117 118PNAME(mux_pll_p) = { "xin24m", "xin24m"}; 119PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr", "apll_ddr" }; 120PNAME(mux_armclk_p) = { "apll_core", "gpll_core", "dpll_core" }; 121PNAME(mux_usb480m_pre_p) = { "usbphy", "xin24m" }; 122PNAME(mux_hdmiphy_phy_p) = { "hdmiphy", "xin24m" }; 123PNAME(mux_dclk_hdmiphy_pre_p) = { "dclk_hdmiphy_src_gpll", "dclk_hdmiphy_src_dpll" }; 124PNAME(mux_pll_src_4plls_p) = { "dpll", "gpll", "hdmiphy", "usb480m" }; 125PNAME(mux_pll_src_2plls_p) = { "dpll", "gpll" }; 126PNAME(mux_pll_src_apll_gpll_p) = { "apll", "gpll" }; 127PNAME(mux_aclk_peri_src_p) = { "aclk_peri_src_gpll", "aclk_peri_src_dpll" }; 128PNAME(mux_aclk_bus_src_p) = { "aclk_bus_src_gpll", "aclk_bus_src_apll", "aclk_bus_src_dpll" }; 129PNAME(mux_mmc_src_p) = { "dpll", "gpll", "xin24m", "usb480m" }; 130PNAME(mux_pll_src_dpll_gpll_usb480m_p) = { "dpll", "gpll", "usb480m" }; 131PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" }; 132PNAME(mux_uart1_p) = { "uart1_src", "uart1_frac", "xin24m" }; 133PNAME(mux_uart2_p) = { "uart2_src", "uart2_frac", "xin24m" }; 134PNAME(mux_sclk_mac_p) = { "sclk_mac_pre", "ext_gmac" }; 135PNAME(mux_i2s0_pre_p) = { "i2s0_src", "i2s0_frac", "ext_i2s", "xin12m" }; 136PNAME(mux_i2s_out_p) = { "i2s0_pre", "xin12m" }; 137PNAME(mux_i2s1_p) = { "i2s1_src", "i2s1_frac", "dummy", "xin12m" }; 138PNAME(mux_i2s2_p) = { "i2s2_src", "i2s2_frac", "dummy", "xin12m" }; 139PNAME(mux_wifi_src_p) = { "gpll", "xin24m" }; 140PNAME(mux_cifout_src_p) = { "hdmiphy", "gpll" }; 141PNAME(mux_cifout_p) = { "sclk_cifout_src", "xin24m" }; 142PNAME(mux_sclk_cif0_src_p) = { "pclk_vip", "clk_cif0_chn_out", "pclkin_cvbs2cif" }; 143PNAME(mux_sclk_cif1_src_p) = { "pclk_vip", "clk_cif1_chn_out", "pclkin_cvbs2cif" }; 144PNAME(mux_sclk_cif2_src_p) = { "pclk_vip", "clk_cif2_chn_out", "pclkin_cvbs2cif" }; 145PNAME(mux_sclk_cif3_src_p) = { "pclk_vip", "clk_cif3_chn_out", "pclkin_cvbs2cif" }; 146PNAME(mux_dsp_src_p) = { "dpll", "gpll", "apll", "usb480m" }; 147PNAME(mux_dclk_hdmiphy_p) = { "hdmiphy", "xin24m" }; 148PNAME(mux_dclk_vop_p) = { "dclk_hdmiphy", "dclk_vop_src" }; 149PNAME(mux_hdmi_cec_src_p) = { "dpll", "gpll", "xin24m" }; 150PNAME(mux_cvbs_src_p) = { "apll", "io_cvbs_clkin", "hdmiphy", "gpll" }; 151 152static struct rockchip_pll_clock rv1108_pll_clks[] __initdata = { 153 [apll] = PLL(pll_rk3399, PLL_APLL, "apll", mux_pll_p, 0, RV1108_PLL_CON(0), 154 RV1108_PLL_CON(3), 8, 0, 0, rv1108_pll_rates), 155 [dpll] = PLL(pll_rk3399, PLL_DPLL, "dpll", mux_pll_p, 0, RV1108_PLL_CON(8), 156 RV1108_PLL_CON(11), 8, 1, 0, NULL), 157 [gpll] = PLL(pll_rk3399, PLL_GPLL, "gpll", mux_pll_p, 0, RV1108_PLL_CON(16), 158 RV1108_PLL_CON(19), 8, 2, 0, rv1108_pll_rates), 159}; 160 161#define MFLAGS CLK_MUX_HIWORD_MASK 162#define DFLAGS CLK_DIVIDER_HIWORD_MASK 163#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE) 164#define IFLAGS ROCKCHIP_INVERTER_HIWORD_MASK 165 166static struct rockchip_clk_branch rv1108_uart0_fracmux __initdata = 167 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT, 168 RV1108_CLKSEL_CON(13), 8, 2, MFLAGS); 169 170static struct rockchip_clk_branch rv1108_uart1_fracmux __initdata = 171 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT, 172 RV1108_CLKSEL_CON(14), 8, 2, MFLAGS); 173 174static struct rockchip_clk_branch rv1108_uart2_fracmux __initdata = 175 MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT, 176 RV1108_CLKSEL_CON(15), 8, 2, MFLAGS); 177 178static struct rockchip_clk_branch rv1108_i2s0_fracmux __initdata = 179 MUX(0, "i2s0_pre", mux_i2s0_pre_p, CLK_SET_RATE_PARENT, 180 RV1108_CLKSEL_CON(5), 12, 2, MFLAGS); 181 182static struct rockchip_clk_branch rv1108_i2s1_fracmux __initdata = 183 MUX(0, "i2s1_pre", mux_i2s1_p, CLK_SET_RATE_PARENT, 184 RV1108_CLKSEL_CON(6), 12, 2, MFLAGS); 185 186static struct rockchip_clk_branch rv1108_i2s2_fracmux __initdata = 187 MUX(0, "i2s2_pre", mux_i2s2_p, CLK_SET_RATE_PARENT, 188 RV1108_CLKSEL_CON(7), 12, 2, MFLAGS); 189 190static struct rockchip_clk_branch rv1108_clk_branches[] __initdata = { 191 MUX(0, "hdmiphy", mux_hdmiphy_phy_p, CLK_SET_RATE_PARENT, 192 RV1108_MISC_CON, 13, 1, MFLAGS), 193 MUX(0, "usb480m", mux_usb480m_pre_p, CLK_SET_RATE_PARENT, 194 RV1108_MISC_CON, 15, 1, MFLAGS), 195 /* 196 * Clock-Architecture Diagram 2 197 */ 198 199 /* PD_CORE */ 200 GATE(0, "dpll_core", "dpll", CLK_IGNORE_UNUSED, 201 RV1108_CLKGATE_CON(0), 1, GFLAGS), 202 GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED, 203 RV1108_CLKGATE_CON(0), 0, GFLAGS), 204 GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED, 205 RV1108_CLKGATE_CON(0), 2, GFLAGS), 206 COMPOSITE_NOMUX(0, "pclken_dbg", "armclk", CLK_IGNORE_UNUSED, 207 RV1108_CLKSEL_CON(1), 4, 4, DFLAGS | CLK_DIVIDER_READ_ONLY, 208 RV1108_CLKGATE_CON(0), 5, GFLAGS), 209 COMPOSITE_NOMUX(ACLK_ENMCORE, "aclkenm_core", "armclk", CLK_IGNORE_UNUSED, 210 RV1108_CLKSEL_CON(1), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY, 211 RV1108_CLKGATE_CON(0), 4, GFLAGS), 212 GATE(ACLK_CORE, "aclk_core", "aclkenm_core", CLK_IGNORE_UNUSED, 213 RV1108_CLKGATE_CON(11), 0, GFLAGS), 214 GATE(0, "pclk_dbg", "pclken_dbg", CLK_IGNORE_UNUSED, 215 RV1108_CLKGATE_CON(11), 1, GFLAGS), 216 217 /* PD_RKVENC */ 218 COMPOSITE(0, "aclk_rkvenc_pre", mux_pll_src_4plls_p, 0, 219 RV1108_CLKSEL_CON(37), 6, 2, MFLAGS, 0, 5, DFLAGS, 220 RV1108_CLKGATE_CON(8), 8, GFLAGS), 221 FACTOR_GATE(0, "hclk_rkvenc_pre", "aclk_rkvenc_pre", 0, 1, 4, 222 RV1108_CLKGATE_CON(8), 10, GFLAGS), 223 COMPOSITE(SCLK_VENC_CORE, "clk_venc_core", mux_pll_src_4plls_p, 0, 224 RV1108_CLKSEL_CON(37), 14, 2, MFLAGS, 8, 5, DFLAGS, 225 RV1108_CLKGATE_CON(8), 9, GFLAGS), 226 GATE(ACLK_RKVENC, "aclk_rkvenc", "aclk_rkvenc_pre", 0, 227 RV1108_CLKGATE_CON(19), 8, GFLAGS), 228 GATE(HCLK_RKVENC, "hclk_rkvenc", "hclk_rkvenc_pre", 0, 229 RV1108_CLKGATE_CON(19), 9, GFLAGS), 230 GATE(0, "aclk_rkvenc_niu", "aclk_rkvenc_pre", CLK_IGNORE_UNUSED, 231 RV1108_CLKGATE_CON(19), 11, GFLAGS), 232 GATE(0, "hclk_rkvenc_niu", "hclk_rkvenc_pre", CLK_IGNORE_UNUSED, 233 RV1108_CLKGATE_CON(19), 10, GFLAGS), 234 235 /* PD_RKVDEC */ 236 COMPOSITE(SCLK_HEVC_CORE, "sclk_hevc_core", mux_pll_src_4plls_p, 0, 237 RV1108_CLKSEL_CON(36), 6, 2, MFLAGS, 0, 5, DFLAGS, 238 RV1108_CLKGATE_CON(8), 2, GFLAGS), 239 FACTOR_GATE(0, "hclk_rkvdec_pre", "sclk_hevc_core", 0, 1, 4, 240 RV1108_CLKGATE_CON(8), 10, GFLAGS), 241 COMPOSITE(SCLK_HEVC_CABAC, "clk_hevc_cabac", mux_pll_src_4plls_p, 0, 242 RV1108_CLKSEL_CON(35), 14, 2, MFLAGS, 8, 5, DFLAGS, 243 RV1108_CLKGATE_CON(8), 1, GFLAGS), 244 245 COMPOSITE(0, "aclk_rkvdec_pre", mux_pll_src_4plls_p, 0, 246 RV1108_CLKSEL_CON(35), 6, 2, MFLAGS, 0, 5, DFLAGS, 247 RV1108_CLKGATE_CON(8), 0, GFLAGS), 248 COMPOSITE(0, "aclk_vpu_pre", mux_pll_src_4plls_p, 0, 249 RV1108_CLKSEL_CON(36), 14, 2, MFLAGS, 8, 5, DFLAGS, 250 RV1108_CLKGATE_CON(8), 3, GFLAGS), 251 GATE(ACLK_RKVDEC, "aclk_rkvdec", "aclk_rkvdec_pre", 0, 252 RV1108_CLKGATE_CON(19), 0, GFLAGS), 253 GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_pre", 0, 254 RV1108_CLKGATE_CON(19), 1, GFLAGS), 255 GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_rkvdec_pre", 0, 256 RV1108_CLKGATE_CON(19), 2, GFLAGS), 257 GATE(HCLK_VPU, "hclk_vpu", "hclk_rkvdec_pre", 0, 258 RV1108_CLKGATE_CON(19), 3, GFLAGS), 259 GATE(0, "aclk_rkvdec_niu", "aclk_rkvdec_pre", CLK_IGNORE_UNUSED, 260 RV1108_CLKGATE_CON(19), 4, GFLAGS), 261 GATE(0, "hclk_rkvdec_niu", "hclk_rkvdec_pre", CLK_IGNORE_UNUSED, 262 RV1108_CLKGATE_CON(19), 5, GFLAGS), 263 GATE(0, "aclk_vpu_niu", "aclk_vpu_pre", CLK_IGNORE_UNUSED, 264 RV1108_CLKGATE_CON(19), 6, GFLAGS), 265 266 /* PD_PMU_wrapper */ 267 COMPOSITE_NOMUX(0, "pmu_24m_ena", "gpll", CLK_IGNORE_UNUSED, 268 RV1108_CLKSEL_CON(38), 0, 5, DFLAGS, 269 RV1108_CLKGATE_CON(8), 12, GFLAGS), 270 GATE(0, "pclk_pmu", "pmu_24m_ena", CLK_IGNORE_UNUSED, 271 RV1108_CLKGATE_CON(10), 0, GFLAGS), 272 GATE(0, "pclk_intmem1", "pmu_24m_ena", CLK_IGNORE_UNUSED, 273 RV1108_CLKGATE_CON(10), 1, GFLAGS), 274 GATE(PCLK_GPIO0_PMU, "pclk_gpio0_pmu", "pmu_24m_ena", 0, 275 RV1108_CLKGATE_CON(10), 2, GFLAGS), 276 GATE(0, "pclk_pmugrf", "pmu_24m_ena", CLK_IGNORE_UNUSED, 277 RV1108_CLKGATE_CON(10), 3, GFLAGS), 278 GATE(0, "pclk_pmu_niu", "pmu_24m_ena", CLK_IGNORE_UNUSED, 279 RV1108_CLKGATE_CON(10), 4, GFLAGS), 280 GATE(PCLK_I2C0_PMU, "pclk_i2c0_pmu", "pmu_24m_ena", 0, 281 RV1108_CLKGATE_CON(10), 5, GFLAGS), 282 GATE(PCLK_PWM0_PMU, "pclk_pwm0_pmu", "pmu_24m_ena", 0, 283 RV1108_CLKGATE_CON(10), 6, GFLAGS), 284 COMPOSITE(SCLK_PWM0_PMU, "sclk_pwm0_pmu", mux_pll_src_2plls_p, 0, 285 RV1108_CLKSEL_CON(12), 7, 1, MFLAGS, 0, 7, DFLAGS, 286 RV1108_CLKGATE_CON(8), 15, GFLAGS), 287 COMPOSITE(SCLK_I2C0_PMU, "sclk_i2c0_pmu", mux_pll_src_2plls_p, 0, 288 RV1108_CLKSEL_CON(19), 7, 1, MFLAGS, 0, 7, DFLAGS, 289 RV1108_CLKGATE_CON(8), 14, GFLAGS), 290 GATE(0, "pvtm_pmu", "xin24m", CLK_IGNORE_UNUSED, 291 RV1108_CLKGATE_CON(8), 13, GFLAGS), 292 293 /* 294 * Clock-Architecture Diagram 3 295 */ 296 COMPOSITE(SCLK_WIFI, "sclk_wifi", mux_wifi_src_p, 0, 297 RV1108_CLKSEL_CON(28), 15, 1, MFLAGS, 8, 6, DFLAGS, 298 RV1108_CLKGATE_CON(9), 8, GFLAGS), 299 COMPOSITE_NODIV(0, "sclk_cifout_src", mux_cifout_src_p, 0, 300 RV1108_CLKSEL_CON(40), 8, 1, MFLAGS, 301 RV1108_CLKGATE_CON(9), 11, GFLAGS), 302 COMPOSITE_NOGATE(SCLK_CIFOUT, "sclk_cifout", mux_cifout_p, 0, 303 RV1108_CLKSEL_CON(40), 12, 1, MFLAGS, 0, 5, DFLAGS), 304 COMPOSITE_NOMUX(SCLK_MIPI_CSI_OUT, "sclk_mipi_csi_out", "xin24m", 0, 305 RV1108_CLKSEL_CON(41), 0, 5, DFLAGS, 306 RV1108_CLKGATE_CON(9), 12, GFLAGS), 307 308 GATE(0, "pclk_acodecphy", "pclk_top_pre", CLK_IGNORE_UNUSED, 309 RV1108_CLKGATE_CON(14), 6, GFLAGS), 310 GATE(0, "pclk_usbgrf", "pclk_top_pre", CLK_IGNORE_UNUSED, 311 RV1108_CLKGATE_CON(14), 14, GFLAGS), 312 313 GATE(ACLK_CIF0, "aclk_cif0", "aclk_vio1_pre", 0, 314 RV1108_CLKGATE_CON(18), 10, GFLAGS), 315 GATE(HCLK_CIF0, "hclk_cif0", "hclk_vio_pre", 0, 316 RV1108_CLKGATE_CON(18), 10, GFLAGS), 317 COMPOSITE_NODIV(SCLK_CIF0, "sclk_cif0", mux_sclk_cif0_src_p, 0, 318 RV1108_CLKSEL_CON(31), 0, 2, MFLAGS, 319 RV1108_CLKGATE_CON(7), 9, GFLAGS), 320 GATE(ACLK_CIF1, "aclk_cif1", "aclk_vio1_pre", 0, 321 RV1108_CLKGATE_CON(17), 6, GFLAGS), 322 GATE(HCLK_CIF1, "hclk_cif1", "hclk_vio_pre", 0, 323 RV1108_CLKGATE_CON(17), 7, GFLAGS), 324 COMPOSITE_NODIV(SCLK_CIF1, "sclk_cif1", mux_sclk_cif1_src_p, 0, 325 RV1108_CLKSEL_CON(31), 2, 2, MFLAGS, 326 RV1108_CLKGATE_CON(7), 10, GFLAGS), 327 GATE(ACLK_CIF2, "aclk_cif2", "aclk_vio1_pre", 0, 328 RV1108_CLKGATE_CON(17), 8, GFLAGS), 329 GATE(HCLK_CIF2, "hclk_cif2", "hclk_vio_pre", 0, 330 RV1108_CLKGATE_CON(17), 9, GFLAGS), 331 COMPOSITE_NODIV(SCLK_CIF2, "sclk_cif2", mux_sclk_cif2_src_p, 0, 332 RV1108_CLKSEL_CON(31), 4, 2, MFLAGS, 333 RV1108_CLKGATE_CON(7), 11, GFLAGS), 334 GATE(ACLK_CIF3, "aclk_cif3", "aclk_vio1_pre", 0, 335 RV1108_CLKGATE_CON(17), 10, GFLAGS), 336 GATE(HCLK_CIF3, "hclk_cif3", "hclk_vio_pre", 0, 337 RV1108_CLKGATE_CON(17), 11, GFLAGS), 338 COMPOSITE_NODIV(SCLK_CIF3, "sclk_cif3", mux_sclk_cif3_src_p, 0, 339 RV1108_CLKSEL_CON(31), 6, 2, MFLAGS, 340 RV1108_CLKGATE_CON(7), 12, GFLAGS), 341 GATE(0, "pclk_cif1to4", "pclk_vip", CLK_IGNORE_UNUSED, 342 RV1108_CLKGATE_CON(7), 8, GFLAGS), 343 344 /* PD_DSP_wrapper */ 345 COMPOSITE(SCLK_DSP, "sclk_dsp", mux_dsp_src_p, 0, 346 RV1108_CLKSEL_CON(42), 8, 2, MFLAGS, 0, 5, DFLAGS, 347 RV1108_CLKGATE_CON(9), 0, GFLAGS), 348 GATE(0, "clk_dsp_sys_wd", "sclk_dsp", CLK_IGNORE_UNUSED, 349 RV1108_CLKGATE_CON(16), 0, GFLAGS), 350 GATE(0, "clk_dsp_epp_wd", "sclk_dsp", CLK_IGNORE_UNUSED, 351 RV1108_CLKGATE_CON(16), 1, GFLAGS), 352 GATE(0, "clk_dsp_edp_wd", "sclk_dsp", CLK_IGNORE_UNUSED, 353 RV1108_CLKGATE_CON(16), 2, GFLAGS), 354 GATE(0, "clk_dsp_iop_wd", "sclk_dsp", CLK_IGNORE_UNUSED, 355 RV1108_CLKGATE_CON(16), 3, GFLAGS), 356 GATE(0, "clk_dsp_free", "sclk_dsp", CLK_IGNORE_UNUSED, 357 RV1108_CLKGATE_CON(16), 13, GFLAGS), 358 COMPOSITE_NOMUX(SCLK_DSP_IOP, "sclk_dsp_iop", "sclk_dsp", 0, 359 RV1108_CLKSEL_CON(44), 0, 5, DFLAGS, 360 RV1108_CLKGATE_CON(9), 1, GFLAGS), 361 COMPOSITE_NOMUX(SCLK_DSP_EPP, "sclk_dsp_epp", "sclk_dsp", 0, 362 RV1108_CLKSEL_CON(44), 8, 5, DFLAGS, 363 RV1108_CLKGATE_CON(9), 2, GFLAGS), 364 COMPOSITE_NOMUX(SCLK_DSP_EDP, "sclk_dsp_edp", "sclk_dsp", 0, 365 RV1108_CLKSEL_CON(45), 0, 5, DFLAGS, 366 RV1108_CLKGATE_CON(9), 3, GFLAGS), 367 COMPOSITE_NOMUX(SCLK_DSP_EDAP, "sclk_dsp_edap", "sclk_dsp", 0, 368 RV1108_CLKSEL_CON(45), 8, 5, DFLAGS, 369 RV1108_CLKGATE_CON(9), 4, GFLAGS), 370 GATE(0, "pclk_dsp_iop_niu", "sclk_dsp_iop", CLK_IGNORE_UNUSED, 371 RV1108_CLKGATE_CON(16), 4, GFLAGS), 372 GATE(0, "aclk_dsp_epp_niu", "sclk_dsp_epp", CLK_IGNORE_UNUSED, 373 RV1108_CLKGATE_CON(16), 5, GFLAGS), 374 GATE(0, "aclk_dsp_edp_niu", "sclk_dsp_edp", CLK_IGNORE_UNUSED, 375 RV1108_CLKGATE_CON(16), 6, GFLAGS), 376 GATE(0, "pclk_dsp_dbg_niu", "sclk_dsp", CLK_IGNORE_UNUSED, 377 RV1108_CLKGATE_CON(16), 7, GFLAGS), 378 GATE(0, "aclk_dsp_edap_niu", "sclk_dsp_edap", CLK_IGNORE_UNUSED, 379 RV1108_CLKGATE_CON(16), 14, GFLAGS), 380 COMPOSITE_NOMUX(SCLK_DSP_PFM, "sclk_dsp_pfm", "sclk_dsp", 0, 381 RV1108_CLKSEL_CON(43), 0, 5, DFLAGS, 382 RV1108_CLKGATE_CON(9), 5, GFLAGS), 383 COMPOSITE_NOMUX(PCLK_DSP_CFG, "pclk_dsp_cfg", "sclk_dsp", 0, 384 RV1108_CLKSEL_CON(43), 8, 5, DFLAGS, 385 RV1108_CLKGATE_CON(9), 6, GFLAGS), 386 GATE(0, "pclk_dsp_cfg_niu", "pclk_dsp_cfg", CLK_IGNORE_UNUSED, 387 RV1108_CLKGATE_CON(16), 8, GFLAGS), 388 GATE(0, "pclk_dsp_pfm_mon", "pclk_dsp_cfg", CLK_IGNORE_UNUSED, 389 RV1108_CLKGATE_CON(16), 9, GFLAGS), 390 GATE(0, "pclk_intc", "pclk_dsp_cfg", CLK_IGNORE_UNUSED, 391 RV1108_CLKGATE_CON(16), 10, GFLAGS), 392 GATE(0, "pclk_dsp_grf", "pclk_dsp_cfg", CLK_IGNORE_UNUSED, 393 RV1108_CLKGATE_CON(16), 11, GFLAGS), 394 GATE(0, "pclk_mailbox", "pclk_dsp_cfg", CLK_IGNORE_UNUSED, 395 RV1108_CLKGATE_CON(16), 12, GFLAGS), 396 GATE(0, "aclk_dsp_epp_perf", "sclk_dsp_epp", CLK_IGNORE_UNUSED, 397 RV1108_CLKGATE_CON(16), 15, GFLAGS), 398 GATE(0, "aclk_dsp_edp_perf", "sclk_dsp_edp", CLK_IGNORE_UNUSED, 399 RV1108_CLKGATE_CON(11), 8, GFLAGS), 400 401 /* 402 * Clock-Architecture Diagram 4 403 */ 404 COMPOSITE(0, "aclk_vio0_pre", mux_pll_src_4plls_p, CLK_IGNORE_UNUSED, 405 RV1108_CLKSEL_CON(28), 6, 2, MFLAGS, 0, 5, DFLAGS, 406 RV1108_CLKGATE_CON(6), 0, GFLAGS), 407 GATE(ACLK_VIO0, "aclk_vio0", "aclk_vio0_pre", 0, 408 RV1108_CLKGATE_CON(17), 0, GFLAGS), 409 COMPOSITE_NOMUX(0, "hclk_vio_pre", "aclk_vio0_pre", 0, 410 RV1108_CLKSEL_CON(29), 0, 5, DFLAGS, 411 RV1108_CLKGATE_CON(7), 2, GFLAGS), 412 GATE(HCLK_VIO, "hclk_vio", "hclk_vio_pre", 0, 413 RV1108_CLKGATE_CON(17), 2, GFLAGS), 414 COMPOSITE_NOMUX(0, "pclk_vio_pre", "aclk_vio0_pre", 0, 415 RV1108_CLKSEL_CON(29), 8, 5, DFLAGS, 416 RV1108_CLKGATE_CON(7), 3, GFLAGS), 417 GATE(PCLK_VIO, "pclk_vio", "pclk_vio_pre", 0, 418 RV1108_CLKGATE_CON(17), 3, GFLAGS), 419 COMPOSITE(0, "aclk_vio1_pre", mux_pll_src_4plls_p, CLK_IGNORE_UNUSED, 420 RV1108_CLKSEL_CON(28), 14, 2, MFLAGS, 8, 5, DFLAGS, 421 RV1108_CLKGATE_CON(6), 1, GFLAGS), 422 GATE(ACLK_VIO1, "aclk_vio1", "aclk_vio1_pre", 0, 423 RV1108_CLKGATE_CON(17), 1, GFLAGS), 424 425 INVERTER(0, "pclk_vip", "ext_vip", 426 RV1108_CLKSEL_CON(31), 8, IFLAGS), 427 GATE(0, "pclk_isp_pre", "pclk_vip", CLK_IGNORE_UNUSED, 428 RV1108_CLKGATE_CON(7), 6, GFLAGS), 429 GATE(0, "pclk_isp", "pclk_isp_pre", CLK_IGNORE_UNUSED, 430 RV1108_CLKGATE_CON(18), 10, GFLAGS), 431 GATE(0, "dclk_hdmiphy_src_gpll", "gpll", CLK_IGNORE_UNUSED, 432 RV1108_CLKGATE_CON(6), 5, GFLAGS), 433 GATE(0, "dclk_hdmiphy_src_dpll", "dpll", CLK_IGNORE_UNUSED, 434 RV1108_CLKGATE_CON(6), 4, GFLAGS), 435 COMPOSITE_NOGATE(0, "dclk_hdmiphy_pre", mux_dclk_hdmiphy_pre_p, 0, 436 RV1108_CLKSEL_CON(32), 6, 1, MFLAGS, 8, 6, DFLAGS), 437 COMPOSITE_NOGATE(DCLK_VOP_SRC, "dclk_vop_src", mux_dclk_hdmiphy_pre_p, 0, 438 RV1108_CLKSEL_CON(32), 6, 1, MFLAGS, 0, 6, DFLAGS), 439 MUX(DCLK_HDMIPHY, "dclk_hdmiphy", mux_dclk_hdmiphy_p, CLK_SET_RATE_PARENT, 440 RV1108_CLKSEL_CON(32), 15, 1, MFLAGS), 441 MUX(DCLK_VOP, "dclk_vop", mux_dclk_vop_p, CLK_SET_RATE_PARENT, 442 RV1108_CLKSEL_CON(32), 7, 1, MFLAGS), 443 GATE(ACLK_VOP, "aclk_vop", "aclk_vio0_pre", 0, 444 RV1108_CLKGATE_CON(18), 0, GFLAGS), 445 GATE(HCLK_VOP, "hclk_vop", "hclk_vio_pre", 0, 446 RV1108_CLKGATE_CON(18), 1, GFLAGS), 447 GATE(ACLK_IEP, "aclk_iep", "aclk_vio0_pre", 0, 448 RV1108_CLKGATE_CON(18), 2, GFLAGS), 449 GATE(HCLK_IEP, "hclk_iep", "hclk_vio_pre", 0, 450 RV1108_CLKGATE_CON(18), 3, GFLAGS), 451 452 GATE(ACLK_RGA, "aclk_rga", "aclk_vio1_pre", 0, 453 RV1108_CLKGATE_CON(18), 4, GFLAGS), 454 GATE(HCLK_RGA, "hclk_rga", "hclk_vio_pre", 0, 455 RV1108_CLKGATE_CON(18), 5, GFLAGS), 456 COMPOSITE(SCLK_RGA, "sclk_rga", mux_pll_src_4plls_p, 0, 457 RV1108_CLKSEL_CON(33), 6, 2, MFLAGS, 0, 5, DFLAGS, 458 RV1108_CLKGATE_CON(6), 6, GFLAGS), 459 460 COMPOSITE(SCLK_CVBS_HOST, "sclk_cvbs_host", mux_cvbs_src_p, 0, 461 RV1108_CLKSEL_CON(33), 13, 2, MFLAGS, 8, 5, DFLAGS, 462 RV1108_CLKGATE_CON(6), 7, GFLAGS), 463 FACTOR(0, "sclk_cvbs_27m", "sclk_cvbs_host", 0, 1, 2), 464 465 GATE(SCLK_HDMI_SFR, "sclk_hdmi_sfr", "xin24m", 0, 466 RV1108_CLKGATE_CON(6), 8, GFLAGS), 467 468 COMPOSITE(SCLK_HDMI_CEC, "sclk_hdmi_cec", mux_hdmi_cec_src_p, 0, 469 RV1108_CLKSEL_CON(34), 14, 2, MFLAGS, 0, 14, DFLAGS, 470 RV1108_CLKGATE_CON(6), 9, GFLAGS), 471 GATE(PCLK_MIPI_DSI, "pclk_mipi_dsi", "pclk_vio_pre", 0, 472 RV1108_CLKGATE_CON(18), 8, GFLAGS), 473 GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "pclk_vio_pre", 0, 474 RV1108_CLKGATE_CON(18), 9, GFLAGS), 475 476 GATE(ACLK_ISP, "aclk_isp", "aclk_vio1_pre", 0, 477 RV1108_CLKGATE_CON(18), 12, GFLAGS), 478 GATE(HCLK_ISP, "hclk_isp", "hclk_vio_pre", 0, 479 RV1108_CLKGATE_CON(18), 11, GFLAGS), 480 COMPOSITE(SCLK_ISP, "sclk_isp", mux_pll_src_4plls_p, 0, 481 RV1108_CLKSEL_CON(30), 14, 2, MFLAGS, 8, 5, DFLAGS, 482 RV1108_CLKGATE_CON(6), 3, GFLAGS), 483 484 GATE(0, "clk_dsiphy24m", "xin24m", CLK_IGNORE_UNUSED, 485 RV1108_CLKGATE_CON(9), 10, GFLAGS), 486 GATE(0, "pclk_vdacphy", "pclk_top_pre", CLK_IGNORE_UNUSED, 487 RV1108_CLKGATE_CON(14), 9, GFLAGS), 488 GATE(0, "pclk_mipi_dsiphy", "pclk_top_pre", CLK_IGNORE_UNUSED, 489 RV1108_CLKGATE_CON(14), 11, GFLAGS), 490 GATE(0, "pclk_mipi_csiphy", "pclk_top_pre", CLK_IGNORE_UNUSED, 491 RV1108_CLKGATE_CON(14), 12, GFLAGS), 492 493 /* 494 * Clock-Architecture Diagram 5 495 */ 496 497 FACTOR(0, "xin12m", "xin24m", 0, 1, 2), 498 499 500 COMPOSITE(SCLK_I2S0_SRC, "i2s0_src", mux_pll_src_2plls_p, 0, 501 RV1108_CLKSEL_CON(5), 8, 1, MFLAGS, 0, 7, DFLAGS, 502 RV1108_CLKGATE_CON(2), 0, GFLAGS), 503 COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_src", CLK_SET_RATE_PARENT, 504 RV1108_CLKSEL_CON(8), 0, 505 RV1108_CLKGATE_CON(2), 1, GFLAGS, 506 &rv1108_i2s0_fracmux), 507 GATE(SCLK_I2S0, "sclk_i2s0", "i2s0_pre", CLK_SET_RATE_PARENT, 508 RV1108_CLKGATE_CON(2), 2, GFLAGS), 509 COMPOSITE_NODIV(0, "i2s_out", mux_i2s_out_p, 0, 510 RV1108_CLKSEL_CON(5), 15, 1, MFLAGS, 511 RV1108_CLKGATE_CON(2), 3, GFLAGS), 512 513 COMPOSITE(SCLK_I2S1_SRC, "i2s1_src", mux_pll_src_2plls_p, 0, 514 RV1108_CLKSEL_CON(6), 8, 1, MFLAGS, 0, 7, DFLAGS, 515 RV1108_CLKGATE_CON(2), 4, GFLAGS), 516 COMPOSITE_FRACMUX(0, "i2s1_frac", "i2s1_src", CLK_SET_RATE_PARENT, 517 RK2928_CLKSEL_CON(9), 0, 518 RK2928_CLKGATE_CON(2), 5, GFLAGS, 519 &rv1108_i2s1_fracmux), 520 GATE(SCLK_I2S1, "sclk_i2s1", "i2s1_pre", CLK_SET_RATE_PARENT, 521 RV1108_CLKGATE_CON(2), 6, GFLAGS), 522 523 COMPOSITE(SCLK_I2S2_SRC, "i2s2_src", mux_pll_src_2plls_p, 0, 524 RV1108_CLKSEL_CON(7), 8, 1, MFLAGS, 0, 7, DFLAGS, 525 RV1108_CLKGATE_CON(3), 8, GFLAGS), 526 COMPOSITE_FRACMUX(0, "i2s2_frac", "i2s2_src", CLK_SET_RATE_PARENT, 527 RV1108_CLKSEL_CON(10), 0, 528 RV1108_CLKGATE_CON(2), 9, GFLAGS, 529 &rv1108_i2s2_fracmux), 530 GATE(SCLK_I2S2, "sclk_i2s2", "i2s2_pre", CLK_SET_RATE_PARENT, 531 RV1108_CLKGATE_CON(2), 10, GFLAGS), 532 533 /* PD_BUS */ 534 GATE(0, "aclk_bus_src_gpll", "gpll", CLK_IGNORE_UNUSED, 535 RV1108_CLKGATE_CON(1), 0, GFLAGS), 536 GATE(0, "aclk_bus_src_apll", "apll", CLK_IGNORE_UNUSED, 537 RV1108_CLKGATE_CON(1), 1, GFLAGS), 538 GATE(0, "aclk_bus_src_dpll", "dpll", CLK_IGNORE_UNUSED, 539 RV1108_CLKGATE_CON(1), 2, GFLAGS), 540 COMPOSITE_NOGATE(ACLK_PRE, "aclk_bus_pre", mux_aclk_bus_src_p, 0, 541 RV1108_CLKSEL_CON(2), 8, 2, MFLAGS, 0, 5, DFLAGS), 542 COMPOSITE_NOMUX(HCLK_BUS, "hclk_bus_pre", "aclk_bus_pre", 0, 543 RV1108_CLKSEL_CON(3), 0, 5, DFLAGS, 544 RV1108_CLKGATE_CON(1), 4, GFLAGS), 545 COMPOSITE_NOMUX(0, "pclk_bus_pre", "aclk_bus_pre", 0, 546 RV1108_CLKSEL_CON(3), 8, 5, DFLAGS, 547 RV1108_CLKGATE_CON(1), 5, GFLAGS), 548 GATE(PCLK_BUS, "pclk_bus", "pclk_bus_pre", 0, 549 RV1108_CLKGATE_CON(1), 6, GFLAGS), 550 GATE(0, "pclk_top_pre", "pclk_bus_pre", CLK_IGNORE_UNUSED, 551 RV1108_CLKGATE_CON(1), 7, GFLAGS), 552 GATE(0, "pclk_ddr_pre", "pclk_bus_pre", CLK_IGNORE_UNUSED, 553 RV1108_CLKGATE_CON(1), 8, GFLAGS), 554 GATE(SCLK_TIMER0, "clk_timer0", "xin24m", 0, 555 RV1108_CLKGATE_CON(1), 9, GFLAGS), 556 GATE(SCLK_TIMER1, "clk_timer1", "xin24m", CLK_IGNORE_UNUSED, 557 RV1108_CLKGATE_CON(1), 10, GFLAGS), 558 GATE(PCLK_TIMER, "pclk_timer", "pclk_bus_pre", CLK_IGNORE_UNUSED, 559 RV1108_CLKGATE_CON(13), 4, GFLAGS), 560 561 GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_bus_pre", 0, 562 RV1108_CLKGATE_CON(12), 7, GFLAGS), 563 GATE(HCLK_I2S1_2CH, "hclk_i2s1_2ch", "hclk_bus_pre", 0, 564 RV1108_CLKGATE_CON(12), 8, GFLAGS), 565 GATE(HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_bus_pre", 0, 566 RV1108_CLKGATE_CON(12), 9, GFLAGS), 567 568 GATE(HCLK_CRYPTO_MST, "hclk_crypto_mst", "hclk_bus_pre", 0, 569 RV1108_CLKGATE_CON(12), 10, GFLAGS), 570 GATE(HCLK_CRYPTO_SLV, "hclk_crypto_slv", "hclk_bus_pre", 0, 571 RV1108_CLKGATE_CON(12), 11, GFLAGS), 572 COMPOSITE(SCLK_CRYPTO, "sclk_crypto", mux_pll_src_2plls_p, 0, 573 RV1108_CLKSEL_CON(11), 7, 1, MFLAGS, 0, 5, DFLAGS, 574 RV1108_CLKGATE_CON(2), 12, GFLAGS), 575 576 COMPOSITE(SCLK_SPI, "sclk_spi", mux_pll_src_2plls_p, 0, 577 RV1108_CLKSEL_CON(11), 15, 1, MFLAGS, 8, 5, DFLAGS, 578 RV1108_CLKGATE_CON(3), 0, GFLAGS), 579 GATE(PCLK_SPI, "pclk_spi", "pclk_bus_pre", 0, 580 RV1108_CLKGATE_CON(13), 5, GFLAGS), 581 582 COMPOSITE(SCLK_UART0_SRC, "uart0_src", mux_pll_src_dpll_gpll_usb480m_p, CLK_IGNORE_UNUSED, 583 RV1108_CLKSEL_CON(13), 12, 2, MFLAGS, 0, 7, DFLAGS, 584 RV1108_CLKGATE_CON(3), 1, GFLAGS), 585 COMPOSITE(SCLK_UART1_SRC, "uart1_src", mux_pll_src_dpll_gpll_usb480m_p, CLK_IGNORE_UNUSED, 586 RV1108_CLKSEL_CON(14), 12, 2, MFLAGS, 0, 7, DFLAGS, 587 RV1108_CLKGATE_CON(3), 3, GFLAGS), 588 COMPOSITE(SCLK_UART2_SRC, "uart2_src", mux_pll_src_dpll_gpll_usb480m_p, CLK_IGNORE_UNUSED, 589 RV1108_CLKSEL_CON(15), 12, 2, MFLAGS, 0, 7, DFLAGS, 590 RV1108_CLKGATE_CON(3), 5, GFLAGS), 591 592 COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT, 593 RV1108_CLKSEL_CON(16), 0, 594 RV1108_CLKGATE_CON(3), 2, GFLAGS, 595 &rv1108_uart0_fracmux), 596 COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT, 597 RV1108_CLKSEL_CON(17), 0, 598 RV1108_CLKGATE_CON(3), 4, GFLAGS, 599 &rv1108_uart1_fracmux), 600 COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT, 601 RV1108_CLKSEL_CON(18), 0, 602 RV1108_CLKGATE_CON(3), 6, GFLAGS, 603 &rv1108_uart2_fracmux), 604 GATE(PCLK_UART0, "pclk_uart0", "pclk_bus_pre", 0, 605 RV1108_CLKGATE_CON(13), 10, GFLAGS), 606 GATE(PCLK_UART1, "pclk_uart1", "pclk_bus_pre", 0, 607 RV1108_CLKGATE_CON(13), 11, GFLAGS), 608 GATE(PCLK_UART2, "pclk_uart2", "pclk_bus_pre", 0, 609 RV1108_CLKGATE_CON(13), 12, GFLAGS), 610 611 COMPOSITE(SCLK_I2C1, "clk_i2c1", mux_pll_src_2plls_p, 0, 612 RV1108_CLKSEL_CON(19), 15, 1, MFLAGS, 8, 7, DFLAGS, 613 RV1108_CLKGATE_CON(3), 7, GFLAGS), 614 COMPOSITE(SCLK_I2C2, "clk_i2c2", mux_pll_src_2plls_p, 0, 615 RV1108_CLKSEL_CON(20), 7, 1, MFLAGS, 0, 7, DFLAGS, 616 RV1108_CLKGATE_CON(3), 8, GFLAGS), 617 COMPOSITE(SCLK_I2C3, "clk_i2c3", mux_pll_src_2plls_p, 0, 618 RV1108_CLKSEL_CON(20), 15, 1, MFLAGS, 8, 7, DFLAGS, 619 RV1108_CLKGATE_CON(3), 9, GFLAGS), 620 GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus_pre", 0, 621 RV1108_CLKGATE_CON(13), 0, GFLAGS), 622 GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus_pre", 0, 623 RV1108_CLKGATE_CON(13), 1, GFLAGS), 624 GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus_pre", 0, 625 RV1108_CLKGATE_CON(13), 2, GFLAGS), 626 COMPOSITE(SCLK_PWM, "clk_pwm", mux_pll_src_2plls_p, 0, 627 RV1108_CLKSEL_CON(12), 15, 2, MFLAGS, 8, 7, DFLAGS, 628 RV1108_CLKGATE_CON(3), 10, GFLAGS), 629 GATE(PCLK_PWM, "pclk_pwm", "pclk_bus_pre", 0, 630 RV1108_CLKGATE_CON(13), 6, GFLAGS), 631 GATE(PCLK_WDT, "pclk_wdt", "pclk_bus_pre", 0, 632 RV1108_CLKGATE_CON(13), 3, GFLAGS), 633 GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_bus_pre", 0, 634 RV1108_CLKGATE_CON(13), 7, GFLAGS), 635 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_bus_pre", 0, 636 RV1108_CLKGATE_CON(13), 8, GFLAGS), 637 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_bus_pre", 0, 638 RV1108_CLKGATE_CON(13), 9, GFLAGS), 639 640 GATE(0, "pclk_grf", "pclk_bus_pre", CLK_IGNORE_UNUSED, 641 RV1108_CLKGATE_CON(14), 0, GFLAGS), 642 GATE(PCLK_EFUSE0, "pclk_efuse0", "pclk_bus_pre", 0, 643 RV1108_CLKGATE_CON(12), 12, GFLAGS), 644 GATE(PCLK_EFUSE1, "pclk_efuse1", "pclk_bus_pre", 0, 645 RV1108_CLKGATE_CON(12), 13, GFLAGS), 646 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus_pre", 0, 647 RV1108_CLKGATE_CON(13), 13, GFLAGS), 648 COMPOSITE_NOMUX(SCLK_TSADC, "sclk_tsadc", "xin24m", 0, 649 RV1108_CLKSEL_CON(21), 0, 10, DFLAGS, 650 RV1108_CLKGATE_CON(3), 11, GFLAGS), 651 GATE(PCLK_SARADC, "pclk_saradc", "pclk_bus_pre", 0, 652 RV1108_CLKGATE_CON(13), 14, GFLAGS), 653 COMPOSITE_NOMUX(SCLK_SARADC, "sclk_saradc", "xin24m", 0, 654 RV1108_CLKSEL_CON(22), 0, 10, DFLAGS, 655 RV1108_CLKGATE_CON(3), 12, GFLAGS), 656 657 GATE(ACLK_DMAC, "aclk_dmac", "aclk_bus_pre", 0, 658 RV1108_CLKGATE_CON(12), 2, GFLAGS), 659 GATE(0, "hclk_rom", "hclk_bus_pre", CLK_IGNORE_UNUSED, 660 RV1108_CLKGATE_CON(12), 3, GFLAGS), 661 GATE(0, "aclk_intmem", "aclk_bus_pre", CLK_IGNORE_UNUSED, 662 RV1108_CLKGATE_CON(12), 1, GFLAGS), 663 664 /* PD_DDR */ 665 GATE(0, "apll_ddr", "apll", CLK_IGNORE_UNUSED, 666 RV1108_CLKGATE_CON(0), 8, GFLAGS), 667 GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED, 668 RV1108_CLKGATE_CON(0), 9, GFLAGS), 669 GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED, 670 RV1108_CLKGATE_CON(0), 10, GFLAGS), 671 COMPOSITE_NOGATE(0, "clk_ddrphy_src", mux_ddrphy_p, CLK_IGNORE_UNUSED, 672 RV1108_CLKSEL_CON(4), 8, 2, MFLAGS, 0, 3, 673 DFLAGS | CLK_DIVIDER_POWER_OF_TWO), 674 FACTOR(0, "clk_ddr", "clk_ddrphy_src", 0, 1, 2), 675 GATE(0, "clk_ddrphy4x", "clk_ddr", CLK_IGNORE_UNUSED, 676 RV1108_CLKGATE_CON(10), 9, GFLAGS), 677 GATE(0, "pclk_ddrupctl", "pclk_ddr_pre", CLK_IGNORE_UNUSED, 678 RV1108_CLKGATE_CON(12), 4, GFLAGS), 679 GATE(0, "nclk_ddrupctl", "clk_ddr", CLK_IGNORE_UNUSED, 680 RV1108_CLKGATE_CON(12), 5, GFLAGS), 681 GATE(0, "pclk_ddrmon", "pclk_ddr_pre", CLK_IGNORE_UNUSED, 682 RV1108_CLKGATE_CON(12), 6, GFLAGS), 683 GATE(0, "timer_clk", "xin24m", CLK_IGNORE_UNUSED, 684 RV1108_CLKGATE_CON(0), 11, GFLAGS), 685 GATE(0, "pclk_mschniu", "pclk_ddr_pre", CLK_IGNORE_UNUSED, 686 RV1108_CLKGATE_CON(14), 2, GFLAGS), 687 GATE(0, "pclk_ddrphy", "pclk_ddr_pre", CLK_IGNORE_UNUSED, 688 RV1108_CLKGATE_CON(14), 4, GFLAGS), 689 690 /* 691 * Clock-Architecture Diagram 6 692 */ 693 694 /* PD_PERI */ 695 COMPOSITE_NOMUX(0, "pclk_periph_pre", "gpll", 0, 696 RV1108_CLKSEL_CON(23), 10, 5, DFLAGS, 697 RV1108_CLKGATE_CON(4), 5, GFLAGS), 698 GATE(PCLK_PERI, "pclk_periph", "pclk_periph_pre", CLK_IGNORE_UNUSED, 699 RV1108_CLKGATE_CON(15), 13, GFLAGS), 700 COMPOSITE_NOMUX(0, "hclk_periph_pre", "gpll", 0, 701 RV1108_CLKSEL_CON(23), 5, 5, DFLAGS, 702 RV1108_CLKGATE_CON(4), 4, GFLAGS), 703 GATE(HCLK_PERI, "hclk_periph", "hclk_periph_pre", CLK_IGNORE_UNUSED, 704 RV1108_CLKGATE_CON(15), 12, GFLAGS), 705 706 GATE(0, "aclk_peri_src_dpll", "dpll", CLK_IGNORE_UNUSED, 707 RV1108_CLKGATE_CON(4), 1, GFLAGS), 708 GATE(0, "aclk_peri_src_gpll", "gpll", CLK_IGNORE_UNUSED, 709 RV1108_CLKGATE_CON(4), 2, GFLAGS), 710 COMPOSITE(ACLK_PERI, "aclk_periph", mux_aclk_peri_src_p, 0, 711 RV1108_CLKSEL_CON(23), 15, 1, MFLAGS, 0, 5, DFLAGS, 712 RV1108_CLKGATE_CON(15), 11, GFLAGS), 713 714 COMPOSITE(SCLK_SDMMC, "sclk_sdmmc", mux_mmc_src_p, 0, 715 RV1108_CLKSEL_CON(25), 8, 2, MFLAGS, 0, 8, DFLAGS, 716 RV1108_CLKGATE_CON(5), 0, GFLAGS), 717 718 COMPOSITE_NODIV(0, "sclk_sdio_src", mux_mmc_src_p, 0, 719 RV1108_CLKSEL_CON(25), 10, 2, MFLAGS, 720 RV1108_CLKGATE_CON(5), 2, GFLAGS), 721 DIV(SCLK_SDIO, "sclk_sdio", "sclk_sdio_src", 0, 722 RV1108_CLKSEL_CON(26), 0, 8, DFLAGS), 723 724 COMPOSITE_NODIV(0, "sclk_emmc_src", mux_mmc_src_p, 0, 725 RV1108_CLKSEL_CON(25), 12, 2, MFLAGS, 726 RV1108_CLKGATE_CON(5), 1, GFLAGS), 727 DIV(SCLK_EMMC, "sclk_emmc", "sclk_emmc_src", 0, 728 RK2928_CLKSEL_CON(26), 8, 8, DFLAGS), 729 GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 0, GFLAGS), 730 GATE(HCLK_SDIO, "hclk_sdio", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 1, GFLAGS), 731 GATE(HCLK_EMMC, "hclk_emmc", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 2, GFLAGS), 732 733 COMPOSITE(SCLK_NANDC, "sclk_nandc", mux_pll_src_2plls_p, 0, 734 RV1108_CLKSEL_CON(27), 14, 1, MFLAGS, 8, 5, DFLAGS, 735 RV1108_CLKGATE_CON(5), 3, GFLAGS), 736 GATE(HCLK_NANDC, "hclk_nandc", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 3, GFLAGS), 737 738 GATE(HCLK_HOST0, "hclk_host0", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 6, GFLAGS), 739 GATE(0, "hclk_host0_arb", "hclk_periph", CLK_IGNORE_UNUSED, RV1108_CLKGATE_CON(15), 7, GFLAGS), 740 GATE(HCLK_OTG, "hclk_otg", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 8, GFLAGS), 741 GATE(0, "hclk_otg_pmu", "hclk_periph", CLK_IGNORE_UNUSED, RV1108_CLKGATE_CON(15), 9, GFLAGS), 742 GATE(SCLK_USBPHY, "clk_usbphy", "xin24m", CLK_IGNORE_UNUSED, RV1108_CLKGATE_CON(5), 5, GFLAGS), 743 744 COMPOSITE(SCLK_SFC, "sclk_sfc", mux_pll_src_2plls_p, 0, 745 RV1108_CLKSEL_CON(27), 7, 1, MFLAGS, 0, 7, DFLAGS, 746 RV1108_CLKGATE_CON(5), 4, GFLAGS), 747 GATE(HCLK_SFC, "hclk_sfc", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 10, GFLAGS), 748 749 COMPOSITE(SCLK_MAC_PRE, "sclk_mac_pre", mux_pll_src_apll_gpll_p, 0, 750 RV1108_CLKSEL_CON(24), 12, 1, MFLAGS, 0, 5, DFLAGS, 751 RV1108_CLKGATE_CON(4), 10, GFLAGS), 752 MUX(SCLK_MAC, "sclk_mac", mux_sclk_mac_p, CLK_SET_RATE_PARENT, 753 RV1108_CLKSEL_CON(24), 8, 1, MFLAGS), 754 GATE(SCLK_MAC_RX, "sclk_mac_rx", "sclk_mac", 0, RV1108_CLKGATE_CON(4), 8, GFLAGS), 755 GATE(SCLK_MAC_REF, "sclk_mac_ref", "sclk_mac", 0, RV1108_CLKGATE_CON(4), 6, GFLAGS), 756 GATE(SCLK_MAC_REFOUT, "sclk_mac_refout", "sclk_mac", 0, RV1108_CLKGATE_CON(4), 7, GFLAGS), 757 GATE(ACLK_GMAC, "aclk_gmac", "aclk_periph", 0, RV1108_CLKGATE_CON(15), 4, GFLAGS), 758 GATE(PCLK_GMAC, "pclk_gmac", "pclk_periph", 0, RV1108_CLKGATE_CON(15), 5, GFLAGS), 759 760 MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "sclk_sdmmc", RV1108_SDMMC_CON0, 1), 761 MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RV1108_SDMMC_CON1, 1), 762 763 MMC(SCLK_SDIO_DRV, "sdio_drv", "sclk_sdio", RV1108_SDIO_CON0, 1), 764 MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "sclk_sdio", RV1108_SDIO_CON1, 1), 765 766 MMC(SCLK_EMMC_DRV, "emmc_drv", "sclk_emmc", RV1108_EMMC_CON0, 1), 767 MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "sclk_emmc", RV1108_EMMC_CON1, 1), 768}; 769 770static const char *const rv1108_critical_clocks[] __initconst = { 771 "aclk_core", 772 "aclk_bus", 773 "hclk_bus", 774 "pclk_bus", 775 "aclk_periph", 776 "hclk_periph", 777 "pclk_periph", 778 "nclk_ddrupctl", 779 "pclk_ddrmon", 780 "pclk_acodecphy", 781 "pclk_pmu", 782}; 783 784static void __init rv1108_clk_init(struct device_node *np) 785{ 786 struct rockchip_clk_provider *ctx; 787 void __iomem *reg_base; 788 789 reg_base = of_iomap(np, 0); 790 if (!reg_base) { 791 pr_err("%s: could not map cru region\n", __func__); 792 return; 793 } 794 795 ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS); 796 if (IS_ERR(ctx)) { 797 pr_err("%s: rockchip clk init failed\n", __func__); 798 iounmap(reg_base); 799 return; 800 } 801 802 rockchip_clk_register_plls(ctx, rv1108_pll_clks, 803 ARRAY_SIZE(rv1108_pll_clks), 804 RV1108_GRF_SOC_STATUS0); 805 rockchip_clk_register_branches(ctx, rv1108_clk_branches, 806 ARRAY_SIZE(rv1108_clk_branches)); 807 rockchip_clk_protect_critical(rv1108_critical_clocks, 808 ARRAY_SIZE(rv1108_critical_clocks)); 809 810 rockchip_clk_register_armclk(ctx, ARMCLK, "armclk", 811 mux_armclk_p, ARRAY_SIZE(mux_armclk_p), 812 &rv1108_cpuclk_data, rv1108_cpuclk_rates, 813 ARRAY_SIZE(rv1108_cpuclk_rates)); 814 815 rockchip_register_softrst(np, 13, reg_base + RV1108_SOFTRST_CON(0), 816 ROCKCHIP_SOFTRST_HIWORD_MASK); 817 818 rockchip_register_restart_notifier(ctx, RV1108_GLB_SRST_FST, NULL); 819 820 rockchip_clk_of_add_provider(np, ctx); 821} 822CLK_OF_DECLARE(rv1108_cru, "rockchip,rv1108-cru", rv1108_clk_init); 823