1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * Copyright (c) 2019 Rockchip Electronics Co. Ltd. 4 * Author: Finley Xiao <finley.xiao@rock-chips.com> 5 */ 6 7#include <linux/clk-provider.h> 8#include <linux/io.h> 9#include <linux/of.h> 10#include <linux/of_address.h> 11#include <linux/syscore_ops.h> 12#include <dt-bindings/clock/rk3308-cru.h> 13#include "clk.h" 14 15#define RK3308_GRF_SOC_STATUS0 0x380 16 17enum rk3308_plls { 18 apll, dpll, vpll0, vpll1, 19}; 20 21static struct rockchip_pll_rate_table rk3308_pll_rates[] = { 22 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ 23 RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0), 24 RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0), 25 RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0), 26 RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0), 27 RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0), 28 RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0), 29 RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0), 30 RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0), 31 RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0), 32 RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0), 33 RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0), 34 RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0), 35 RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0), 36 RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0), 37 RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0), 38 RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0), 39 RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0), 40 RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0), 41 RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0), 42 RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0), 43 RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0), 44 RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0), 45 RK3036_PLL_RATE(984000000, 1, 82, 2, 1, 1, 0), 46 RK3036_PLL_RATE(960000000, 1, 80, 2, 1, 1, 0), 47 RK3036_PLL_RATE(936000000, 1, 78, 2, 1, 1, 0), 48 RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0), 49 RK3036_PLL_RATE(900000000, 4, 300, 2, 1, 1, 0), 50 RK3036_PLL_RATE(888000000, 1, 74, 2, 1, 1, 0), 51 RK3036_PLL_RATE(864000000, 1, 72, 2, 1, 1, 0), 52 RK3036_PLL_RATE(840000000, 1, 70, 2, 1, 1, 0), 53 RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0), 54 RK3036_PLL_RATE(800000000, 6, 400, 2, 1, 1, 0), 55 RK3036_PLL_RATE(700000000, 6, 350, 2, 1, 1, 0), 56 RK3036_PLL_RATE(696000000, 1, 58, 2, 1, 1, 0), 57 RK3036_PLL_RATE(624000000, 1, 52, 2, 1, 1, 0), 58 RK3036_PLL_RATE(600000000, 1, 75, 3, 1, 1, 0), 59 RK3036_PLL_RATE(594000000, 2, 99, 2, 1, 1, 0), 60 RK3036_PLL_RATE(504000000, 1, 63, 3, 1, 1, 0), 61 RK3036_PLL_RATE(500000000, 6, 250, 2, 1, 1, 0), 62 RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0), 63 RK3036_PLL_RATE(312000000, 1, 52, 2, 2, 1, 0), 64 RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0), 65 RK3036_PLL_RATE(96000000, 1, 64, 4, 4, 1, 0), 66 { /* sentinel */ }, 67}; 68 69#define RK3308_DIV_ACLKM_MASK 0x7 70#define RK3308_DIV_ACLKM_SHIFT 12 71#define RK3308_DIV_PCLK_DBG_MASK 0xf 72#define RK3308_DIV_PCLK_DBG_SHIFT 8 73 74#define RK3308_CLKSEL0(_aclk_core, _pclk_dbg) \ 75{ \ 76 .reg = RK3308_CLKSEL_CON(0), \ 77 .val = HIWORD_UPDATE(_aclk_core, RK3308_DIV_ACLKM_MASK, \ 78 RK3308_DIV_ACLKM_SHIFT) | \ 79 HIWORD_UPDATE(_pclk_dbg, RK3308_DIV_PCLK_DBG_MASK, \ 80 RK3308_DIV_PCLK_DBG_SHIFT), \ 81} 82 83#define RK3308_CPUCLK_RATE(_prate, _aclk_core, _pclk_dbg) \ 84{ \ 85 .prate = _prate, \ 86 .divs = { \ 87 RK3308_CLKSEL0(_aclk_core, _pclk_dbg), \ 88 }, \ 89} 90 91static struct rockchip_cpuclk_rate_table rk3308_cpuclk_rates[] __initdata = { 92 RK3308_CPUCLK_RATE(1608000000, 1, 7), 93 RK3308_CPUCLK_RATE(1512000000, 1, 7), 94 RK3308_CPUCLK_RATE(1488000000, 1, 5), 95 RK3308_CPUCLK_RATE(1416000000, 1, 5), 96 RK3308_CPUCLK_RATE(1392000000, 1, 5), 97 RK3308_CPUCLK_RATE(1296000000, 1, 5), 98 RK3308_CPUCLK_RATE(1200000000, 1, 5), 99 RK3308_CPUCLK_RATE(1104000000, 1, 5), 100 RK3308_CPUCLK_RATE(1008000000, 1, 5), 101 RK3308_CPUCLK_RATE(912000000, 1, 5), 102 RK3308_CPUCLK_RATE(816000000, 1, 3), 103 RK3308_CPUCLK_RATE(696000000, 1, 3), 104 RK3308_CPUCLK_RATE(600000000, 1, 3), 105 RK3308_CPUCLK_RATE(408000000, 1, 1), 106 RK3308_CPUCLK_RATE(312000000, 1, 1), 107 RK3308_CPUCLK_RATE(216000000, 1, 1), 108 RK3308_CPUCLK_RATE(96000000, 1, 1), 109}; 110 111static const struct rockchip_cpuclk_reg_data rk3308_cpuclk_data = { 112 .core_reg = RK3308_CLKSEL_CON(0), 113 .div_core_shift = 0, 114 .div_core_mask = 0xf, 115 .mux_core_alt = 1, 116 .mux_core_main = 0, 117 .mux_core_shift = 6, 118 .mux_core_mask = 0x3, 119}; 120 121PNAME(mux_pll_p) = { "xin24m" }; 122PNAME(mux_usb480m_p) = { "xin24m", "usb480m_phy", "clk_rtc32k" }; 123PNAME(mux_armclk_p) = { "apll_core", "vpll0_core", "vpll1_core" }; 124PNAME(mux_dpll_vpll0_p) = { "dpll", "vpll0" }; 125PNAME(mux_dpll_vpll0_xin24m_p) = { "dpll", "vpll0", "xin24m" }; 126PNAME(mux_dpll_vpll0_vpll1_p) = { "dpll", "vpll0", "vpll1" }; 127PNAME(mux_dpll_vpll0_vpll1_xin24m_p) = { "dpll", "vpll0", "vpll1", "xin24m" }; 128PNAME(mux_dpll_vpll0_vpll1_usb480m_xin24m_p) = { "dpll", "vpll0", "vpll1", "usb480m", "xin24m" }; 129PNAME(mux_vpll0_vpll1_p) = { "vpll0", "vpll1" }; 130PNAME(mux_vpll0_vpll1_xin24m_p) = { "vpll0", "vpll1", "xin24m" }; 131PNAME(mux_uart0_p) = { "clk_uart0_src", "dummy", "clk_uart0_frac" }; 132PNAME(mux_uart1_p) = { "clk_uart1_src", "dummy", "clk_uart1_frac" }; 133PNAME(mux_uart2_p) = { "clk_uart2_src", "dummy", "clk_uart2_frac" }; 134PNAME(mux_uart3_p) = { "clk_uart3_src", "dummy", "clk_uart3_frac" }; 135PNAME(mux_uart4_p) = { "clk_uart4_src", "dummy", "clk_uart4_frac" }; 136PNAME(mux_dclk_vop_p) = { "dclk_vop_src", "dclk_vop_frac", "xin24m" }; 137PNAME(mux_nandc_p) = { "clk_nandc_div", "clk_nandc_div50" }; 138PNAME(mux_sdmmc_p) = { "clk_sdmmc_div", "clk_sdmmc_div50" }; 139PNAME(mux_sdio_p) = { "clk_sdio_div", "clk_sdio_div50" }; 140PNAME(mux_emmc_p) = { "clk_emmc_div", "clk_emmc_div50" }; 141PNAME(mux_mac_p) = { "clk_mac_src", "mac_clkin" }; 142PNAME(mux_mac_rmii_sel_p) = { "clk_mac_rx_tx_div20", "clk_mac_rx_tx_div2" }; 143PNAME(mux_ddrstdby_p) = { "clk_ddrphy1x_out", "clk_ddr_stdby_div4" }; 144PNAME(mux_rtc32k_p) = { "xin32k", "clk_pvtm_32k", "clk_rtc32k_frac", "clk_rtc32k_div" }; 145PNAME(mux_usbphy_ref_p) = { "xin24m", "clk_usbphy_ref_src" }; 146PNAME(mux_wifi_src_p) = { "clk_wifi_dpll", "clk_wifi_vpll0" }; 147PNAME(mux_wifi_p) = { "clk_wifi_osc", "clk_wifi_src" }; 148PNAME(mux_pdm_p) = { "clk_pdm_src", "clk_pdm_frac" }; 149PNAME(mux_i2s0_8ch_tx_p) = { "clk_i2s0_8ch_tx_src", "clk_i2s0_8ch_tx_frac", "mclk_i2s0_8ch_in" }; 150PNAME(mux_i2s0_8ch_tx_rx_p) = { "clk_i2s0_8ch_tx_mux", "clk_i2s0_8ch_rx_mux"}; 151PNAME(mux_i2s0_8ch_tx_out_p) = { "clk_i2s0_8ch_tx", "xin12m" }; 152PNAME(mux_i2s0_8ch_rx_p) = { "clk_i2s0_8ch_rx_src", "clk_i2s0_8ch_rx_frac", "mclk_i2s0_8ch_in" }; 153PNAME(mux_i2s0_8ch_rx_tx_p) = { "clk_i2s0_8ch_rx_mux", "clk_i2s0_8ch_tx_mux"}; 154PNAME(mux_i2s1_8ch_tx_p) = { "clk_i2s1_8ch_tx_src", "clk_i2s1_8ch_tx_frac", "mclk_i2s1_8ch_in" }; 155PNAME(mux_i2s1_8ch_tx_rx_p) = { "clk_i2s1_8ch_tx_mux", "clk_i2s1_8ch_rx_mux"}; 156PNAME(mux_i2s1_8ch_tx_out_p) = { "clk_i2s1_8ch_tx", "xin12m" }; 157PNAME(mux_i2s1_8ch_rx_p) = { "clk_i2s1_8ch_rx_src", "clk_i2s1_8ch_rx_frac", "mclk_i2s1_8ch_in" }; 158PNAME(mux_i2s1_8ch_rx_tx_p) = { "clk_i2s1_8ch_rx_mux", "clk_i2s1_8ch_tx_mux"}; 159PNAME(mux_i2s2_8ch_tx_p) = { "clk_i2s2_8ch_tx_src", "clk_i2s2_8ch_tx_frac", "mclk_i2s2_8ch_in" }; 160PNAME(mux_i2s2_8ch_tx_rx_p) = { "clk_i2s2_8ch_tx_mux", "clk_i2s2_8ch_rx_mux"}; 161PNAME(mux_i2s2_8ch_tx_out_p) = { "clk_i2s2_8ch_tx", "xin12m" }; 162PNAME(mux_i2s2_8ch_rx_p) = { "clk_i2s2_8ch_rx_src", "clk_i2s2_8ch_rx_frac", "mclk_i2s2_8ch_in" }; 163PNAME(mux_i2s2_8ch_rx_tx_p) = { "clk_i2s2_8ch_rx_mux", "clk_i2s2_8ch_tx_mux"}; 164PNAME(mux_i2s3_8ch_tx_p) = { "clk_i2s3_8ch_tx_src", "clk_i2s3_8ch_tx_frac", "mclk_i2s3_8ch_in" }; 165PNAME(mux_i2s3_8ch_tx_rx_p) = { "clk_i2s3_8ch_tx_mux", "clk_i2s3_8ch_rx_mux"}; 166PNAME(mux_i2s3_8ch_tx_out_p) = { "clk_i2s3_8ch_tx", "xin12m" }; 167PNAME(mux_i2s3_8ch_rx_p) = { "clk_i2s3_8ch_rx_src", "clk_i2s3_8ch_rx_frac", "mclk_i2s3_8ch_in" }; 168PNAME(mux_i2s3_8ch_rx_tx_p) = { "clk_i2s3_8ch_rx_mux", "clk_i2s3_8ch_tx_mux"}; 169PNAME(mux_i2s0_2ch_p) = { "clk_i2s0_2ch_src", "clk_i2s0_2ch_frac", "mclk_i2s0_2ch_in" }; 170PNAME(mux_i2s0_2ch_out_p) = { "clk_i2s0_2ch", "xin12m" }; 171PNAME(mux_i2s1_2ch_p) = { "clk_i2s1_2ch_src", "clk_i2s1_2ch_frac", "mclk_i2s1_2ch_in"}; 172PNAME(mux_i2s1_2ch_out_p) = { "clk_i2s1_2ch", "xin12m" }; 173PNAME(mux_spdif_tx_src_p) = { "clk_spdif_tx_div", "clk_spdif_tx_div50" }; 174PNAME(mux_spdif_tx_p) = { "clk_spdif_tx_src", "clk_spdif_tx_frac", "mclk_i2s0_2ch_in" }; 175PNAME(mux_spdif_rx_src_p) = { "clk_spdif_rx_div", "clk_spdif_rx_div50" }; 176PNAME(mux_spdif_rx_p) = { "clk_spdif_rx_src", "clk_spdif_rx_frac" }; 177 178static struct rockchip_pll_clock rk3308_pll_clks[] __initdata = { 179 [apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p, 180 0, RK3308_PLL_CON(0), 181 RK3308_MODE_CON, 0, 0, 0, rk3308_pll_rates), 182 [dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p, 183 0, RK3308_PLL_CON(8), 184 RK3308_MODE_CON, 2, 1, 0, rk3308_pll_rates), 185 [vpll0] = PLL(pll_rk3328, PLL_VPLL0, "vpll0", mux_pll_p, 186 0, RK3308_PLL_CON(16), 187 RK3308_MODE_CON, 4, 2, 0, rk3308_pll_rates), 188 [vpll1] = PLL(pll_rk3328, PLL_VPLL1, "vpll1", mux_pll_p, 189 0, RK3308_PLL_CON(24), 190 RK3308_MODE_CON, 6, 3, 0, rk3308_pll_rates), 191}; 192 193#define MFLAGS CLK_MUX_HIWORD_MASK 194#define DFLAGS CLK_DIVIDER_HIWORD_MASK 195#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE) 196 197static struct rockchip_clk_branch rk3308_uart0_fracmux __initdata = 198 MUX(0, "clk_uart0_mux", mux_uart0_p, CLK_SET_RATE_PARENT, 199 RK3308_CLKSEL_CON(11), 14, 2, MFLAGS); 200 201static struct rockchip_clk_branch rk3308_uart1_fracmux __initdata = 202 MUX(0, "clk_uart1_mux", mux_uart1_p, CLK_SET_RATE_PARENT, 203 RK3308_CLKSEL_CON(14), 14, 2, MFLAGS); 204 205static struct rockchip_clk_branch rk3308_uart2_fracmux __initdata = 206 MUX(0, "clk_uart2_mux", mux_uart2_p, CLK_SET_RATE_PARENT, 207 RK3308_CLKSEL_CON(17), 14, 2, MFLAGS); 208 209static struct rockchip_clk_branch rk3308_uart3_fracmux __initdata = 210 MUX(0, "clk_uart3_mux", mux_uart3_p, CLK_SET_RATE_PARENT, 211 RK3308_CLKSEL_CON(20), 14, 2, MFLAGS); 212 213static struct rockchip_clk_branch rk3308_uart4_fracmux __initdata = 214 MUX(0, "clk_uart4_mux", mux_uart4_p, CLK_SET_RATE_PARENT, 215 RK3308_CLKSEL_CON(23), 14, 2, MFLAGS); 216 217static struct rockchip_clk_branch rk3308_dclk_vop_fracmux __initdata = 218 MUX(0, "dclk_vop_mux", mux_dclk_vop_p, CLK_SET_RATE_PARENT, 219 RK3308_CLKSEL_CON(8), 14, 2, MFLAGS); 220 221static struct rockchip_clk_branch rk3308_rtc32k_fracmux __initdata = 222 MUX(SCLK_RTC32K, "clk_rtc32k", mux_rtc32k_p, CLK_SET_RATE_PARENT, 223 RK3308_CLKSEL_CON(2), 8, 2, MFLAGS); 224 225static struct rockchip_clk_branch rk3308_pdm_fracmux __initdata = 226 MUX(0, "clk_pdm_mux", mux_pdm_p, CLK_SET_RATE_PARENT, 227 RK3308_CLKSEL_CON(46), 15, 1, MFLAGS); 228 229static struct rockchip_clk_branch rk3308_i2s0_8ch_tx_fracmux __initdata = 230 MUX(SCLK_I2S0_8CH_TX_MUX, "clk_i2s0_8ch_tx_mux", mux_i2s0_8ch_tx_p, CLK_SET_RATE_PARENT, 231 RK3308_CLKSEL_CON(52), 10, 2, MFLAGS); 232 233static struct rockchip_clk_branch rk3308_i2s0_8ch_rx_fracmux __initdata = 234 MUX(SCLK_I2S0_8CH_RX_MUX, "clk_i2s0_8ch_rx_mux", mux_i2s0_8ch_rx_p, CLK_SET_RATE_PARENT, 235 RK3308_CLKSEL_CON(54), 10, 2, MFLAGS); 236 237static struct rockchip_clk_branch rk3308_i2s1_8ch_tx_fracmux __initdata = 238 MUX(SCLK_I2S1_8CH_TX_MUX, "clk_i2s1_8ch_tx_mux", mux_i2s1_8ch_tx_p, CLK_SET_RATE_PARENT, 239 RK3308_CLKSEL_CON(56), 10, 2, MFLAGS); 240 241static struct rockchip_clk_branch rk3308_i2s1_8ch_rx_fracmux __initdata = 242 MUX(SCLK_I2S1_8CH_RX_MUX, "clk_i2s1_8ch_rx_mux", mux_i2s1_8ch_rx_p, CLK_SET_RATE_PARENT, 243 RK3308_CLKSEL_CON(58), 10, 2, MFLAGS); 244 245static struct rockchip_clk_branch rk3308_i2s2_8ch_tx_fracmux __initdata = 246 MUX(SCLK_I2S2_8CH_TX_MUX, "clk_i2s2_8ch_tx_mux", mux_i2s2_8ch_tx_p, CLK_SET_RATE_PARENT, 247 RK3308_CLKSEL_CON(60), 10, 2, MFLAGS); 248 249static struct rockchip_clk_branch rk3308_i2s2_8ch_rx_fracmux __initdata = 250 MUX(SCLK_I2S2_8CH_RX_MUX, "clk_i2s2_8ch_rx_mux", mux_i2s2_8ch_rx_p, CLK_SET_RATE_PARENT, 251 RK3308_CLKSEL_CON(62), 10, 2, MFLAGS); 252 253static struct rockchip_clk_branch rk3308_i2s3_8ch_tx_fracmux __initdata = 254 MUX(SCLK_I2S3_8CH_TX_MUX, "clk_i2s3_8ch_tx_mux", mux_i2s3_8ch_tx_p, CLK_SET_RATE_PARENT, 255 RK3308_CLKSEL_CON(64), 10, 2, MFLAGS); 256 257static struct rockchip_clk_branch rk3308_i2s3_8ch_rx_fracmux __initdata = 258 MUX(SCLK_I2S3_8CH_RX_MUX, "clk_i2s3_8ch_rx_mux", mux_i2s3_8ch_rx_p, CLK_SET_RATE_PARENT, 259 RK3308_CLKSEL_CON(66), 10, 2, MFLAGS); 260 261static struct rockchip_clk_branch rk3308_i2s0_2ch_fracmux __initdata = 262 MUX(0, "clk_i2s0_2ch_mux", mux_i2s0_2ch_p, CLK_SET_RATE_PARENT, 263 RK3308_CLKSEL_CON(68), 10, 2, MFLAGS); 264 265static struct rockchip_clk_branch rk3308_i2s1_2ch_fracmux __initdata = 266 MUX(0, "clk_i2s1_2ch_mux", mux_i2s1_2ch_p, CLK_SET_RATE_PARENT, 267 RK3308_CLKSEL_CON(70), 10, 2, MFLAGS); 268 269static struct rockchip_clk_branch rk3308_spdif_tx_fracmux __initdata = 270 MUX(0, "clk_spdif_tx_mux", mux_spdif_tx_p, CLK_SET_RATE_PARENT, 271 RK3308_CLKSEL_CON(48), 14, 2, MFLAGS); 272 273static struct rockchip_clk_branch rk3308_spdif_rx_fracmux __initdata = 274 MUX(0, "clk_spdif_rx_mux", mux_spdif_rx_p, CLK_SET_RATE_PARENT, 275 RK3308_CLKSEL_CON(50), 15, 1, MFLAGS); 276 277 278static struct rockchip_clk_branch rk3308_clk_branches[] __initdata = { 279 /* 280 * Clock-Architecture Diagram 1 281 */ 282 283 MUX(USB480M, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT, 284 RK3308_MODE_CON, 8, 2, MFLAGS), 285 FACTOR(0, "xin12m", "xin24m", 0, 1, 2), 286 287 /* 288 * Clock-Architecture Diagram 2 289 */ 290 291 GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED, 292 RK3308_CLKGATE_CON(0), 0, GFLAGS), 293 GATE(0, "vpll0_core", "vpll0", CLK_IGNORE_UNUSED, 294 RK3308_CLKGATE_CON(0), 0, GFLAGS), 295 GATE(0, "vpll1_core", "vpll1", CLK_IGNORE_UNUSED, 296 RK3308_CLKGATE_CON(0), 0, GFLAGS), 297 COMPOSITE_NOMUX(0, "pclk_core_dbg", "armclk", CLK_IGNORE_UNUSED, 298 RK3308_CLKSEL_CON(0), 8, 4, DFLAGS | CLK_DIVIDER_READ_ONLY, 299 RK3308_CLKGATE_CON(0), 2, GFLAGS), 300 COMPOSITE_NOMUX(0, "aclk_core", "armclk", CLK_IGNORE_UNUSED, 301 RK3308_CLKSEL_CON(0), 12, 3, DFLAGS | CLK_DIVIDER_READ_ONLY, 302 RK3308_CLKGATE_CON(0), 1, GFLAGS), 303 304 GATE(0, "clk_jtag", "jtag_clkin", CLK_IGNORE_UNUSED, 305 RK3308_CLKGATE_CON(0), 3, GFLAGS), 306 307 GATE(SCLK_PVTM_CORE, "clk_pvtm_core", "xin24m", 0, 308 RK3308_CLKGATE_CON(0), 4, GFLAGS), 309 310 /* 311 * Clock-Architecture Diagram 3 312 */ 313 314 COMPOSITE_NODIV(ACLK_BUS_SRC, "clk_bus_src", mux_dpll_vpll0_vpll1_p, CLK_IGNORE_UNUSED, 315 RK3308_CLKSEL_CON(5), 6, 2, MFLAGS, 316 RK3308_CLKGATE_CON(1), 0, GFLAGS), 317 COMPOSITE_NOMUX(PCLK_BUS, "pclk_bus", "clk_bus_src", CLK_IGNORE_UNUSED, 318 RK3308_CLKSEL_CON(6), 8, 5, DFLAGS, 319 RK3308_CLKGATE_CON(1), 3, GFLAGS), 320 GATE(PCLK_DDR, "pclk_ddr", "pclk_bus", CLK_IGNORE_UNUSED, 321 RK3308_CLKGATE_CON(4), 15, GFLAGS), 322 COMPOSITE_NOMUX(HCLK_BUS, "hclk_bus", "clk_bus_src", CLK_IGNORE_UNUSED, 323 RK3308_CLKSEL_CON(6), 0, 5, DFLAGS, 324 RK3308_CLKGATE_CON(1), 2, GFLAGS), 325 COMPOSITE_NOMUX(ACLK_BUS, "aclk_bus", "clk_bus_src", CLK_IGNORE_UNUSED, 326 RK3308_CLKSEL_CON(5), 0, 5, DFLAGS, 327 RK3308_CLKGATE_CON(1), 1, GFLAGS), 328 329 COMPOSITE(0, "clk_uart0_src", mux_dpll_vpll0_vpll1_usb480m_xin24m_p, 0, 330 RK3308_CLKSEL_CON(10), 13, 3, MFLAGS, 0, 5, DFLAGS, 331 RK3308_CLKGATE_CON(1), 9, GFLAGS), 332 COMPOSITE_FRACMUX(0, "clk_uart0_frac", "clk_uart0_src", CLK_SET_RATE_PARENT, 333 RK3308_CLKSEL_CON(12), 0, 334 RK3308_CLKGATE_CON(1), 11, GFLAGS, 335 &rk3308_uart0_fracmux), 336 GATE(SCLK_UART0, "clk_uart0", "clk_uart0_mux", 0, 337 RK3308_CLKGATE_CON(1), 12, GFLAGS), 338 339 COMPOSITE(0, "clk_uart1_src", mux_dpll_vpll0_vpll1_usb480m_xin24m_p, 0, 340 RK3308_CLKSEL_CON(13), 13, 3, MFLAGS, 0, 5, DFLAGS, 341 RK3308_CLKGATE_CON(1), 13, GFLAGS), 342 COMPOSITE_FRACMUX(0, "clk_uart1_frac", "clk_uart1_src", CLK_SET_RATE_PARENT, 343 RK3308_CLKSEL_CON(15), 0, 344 RK3308_CLKGATE_CON(1), 15, GFLAGS, 345 &rk3308_uart1_fracmux), 346 GATE(SCLK_UART1, "clk_uart1", "clk_uart1_mux", 0, 347 RK3308_CLKGATE_CON(2), 0, GFLAGS), 348 349 COMPOSITE(0, "clk_uart2_src", mux_dpll_vpll0_vpll1_usb480m_xin24m_p, 0, 350 RK3308_CLKSEL_CON(16), 13, 3, MFLAGS, 0, 5, DFLAGS, 351 RK3308_CLKGATE_CON(2), 1, GFLAGS), 352 COMPOSITE_FRACMUX(0, "clk_uart2_frac", "clk_uart2_src", CLK_SET_RATE_PARENT, 353 RK3308_CLKSEL_CON(18), 0, 354 RK3308_CLKGATE_CON(2), 3, GFLAGS, 355 &rk3308_uart2_fracmux), 356 GATE(SCLK_UART2, "clk_uart2", "clk_uart2_mux", CLK_SET_RATE_PARENT, 357 RK3308_CLKGATE_CON(2), 4, GFLAGS), 358 359 COMPOSITE(0, "clk_uart3_src", mux_dpll_vpll0_vpll1_usb480m_xin24m_p, 0, 360 RK3308_CLKSEL_CON(19), 13, 3, MFLAGS, 0, 5, DFLAGS, 361 RK3308_CLKGATE_CON(2), 5, GFLAGS), 362 COMPOSITE_FRACMUX(0, "clk_uart3_frac", "clk_uart3_src", CLK_SET_RATE_PARENT, 363 RK3308_CLKSEL_CON(21), 0, 364 RK3308_CLKGATE_CON(2), 7, GFLAGS, 365 &rk3308_uart3_fracmux), 366 GATE(SCLK_UART3, "clk_uart3", "clk_uart3_mux", 0, 367 RK3308_CLKGATE_CON(2), 8, GFLAGS), 368 369 COMPOSITE(0, "clk_uart4_src", mux_dpll_vpll0_vpll1_usb480m_xin24m_p, 0, 370 RK3308_CLKSEL_CON(22), 13, 3, MFLAGS, 0, 5, DFLAGS, 371 RK3308_CLKGATE_CON(2), 9, GFLAGS), 372 COMPOSITE_FRACMUX(0, "clk_uart4_frac", "clk_uart4_src", CLK_SET_RATE_PARENT, 373 RK3308_CLKSEL_CON(24), 0, 374 RK3308_CLKGATE_CON(2), 11, GFLAGS, 375 &rk3308_uart4_fracmux), 376 GATE(SCLK_UART4, "clk_uart4", "clk_uart4_mux", 0, 377 RK3308_CLKGATE_CON(2), 12, GFLAGS), 378 379 COMPOSITE(SCLK_I2C0, "clk_i2c0", mux_dpll_vpll0_xin24m_p, 0, 380 RK3308_CLKSEL_CON(25), 14, 2, MFLAGS, 0, 7, DFLAGS, 381 RK3308_CLKGATE_CON(2), 13, GFLAGS), 382 COMPOSITE(SCLK_I2C1, "clk_i2c1", mux_dpll_vpll0_xin24m_p, 0, 383 RK3308_CLKSEL_CON(26), 14, 2, MFLAGS, 0, 7, DFLAGS, 384 RK3308_CLKGATE_CON(2), 14, GFLAGS), 385 COMPOSITE(SCLK_I2C2, "clk_i2c2", mux_dpll_vpll0_xin24m_p, 0, 386 RK3308_CLKSEL_CON(27), 14, 2, MFLAGS, 0, 7, DFLAGS, 387 RK3308_CLKGATE_CON(2), 15, GFLAGS), 388 COMPOSITE(SCLK_I2C3, "clk_i2c3", mux_dpll_vpll0_xin24m_p, 0, 389 RK3308_CLKSEL_CON(28), 14, 2, MFLAGS, 0, 7, DFLAGS, 390 RK3308_CLKGATE_CON(3), 0, GFLAGS), 391 392 COMPOSITE(SCLK_PWM0, "clk_pwm0", mux_dpll_vpll0_xin24m_p, 0, 393 RK3308_CLKSEL_CON(29), 14, 2, MFLAGS, 0, 7, DFLAGS, 394 RK3308_CLKGATE_CON(3), 1, GFLAGS), 395 COMPOSITE(SCLK_PWM1, "clk_pwm1", mux_dpll_vpll0_xin24m_p, 0, 396 RK3308_CLKSEL_CON(74), 14, 2, MFLAGS, 0, 7, DFLAGS, 397 RK3308_CLKGATE_CON(15), 0, GFLAGS), 398 COMPOSITE(SCLK_PWM2, "clk_pwm2", mux_dpll_vpll0_xin24m_p, 0, 399 RK3308_CLKSEL_CON(75), 14, 2, MFLAGS, 0, 7, DFLAGS, 400 RK3308_CLKGATE_CON(15), 1, GFLAGS), 401 402 COMPOSITE(SCLK_SPI0, "clk_spi0", mux_dpll_vpll0_xin24m_p, 0, 403 RK3308_CLKSEL_CON(30), 14, 2, MFLAGS, 0, 7, DFLAGS, 404 RK3308_CLKGATE_CON(3), 2, GFLAGS), 405 COMPOSITE(SCLK_SPI1, "clk_spi1", mux_dpll_vpll0_xin24m_p, 0, 406 RK3308_CLKSEL_CON(31), 14, 2, MFLAGS, 0, 7, DFLAGS, 407 RK3308_CLKGATE_CON(3), 3, GFLAGS), 408 COMPOSITE(SCLK_SPI2, "clk_spi2", mux_dpll_vpll0_xin24m_p, 0, 409 RK3308_CLKSEL_CON(32), 14, 2, MFLAGS, 0, 7, DFLAGS, 410 RK3308_CLKGATE_CON(3), 4, GFLAGS), 411 412 GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0, 413 RK3308_CLKGATE_CON(3), 10, GFLAGS), 414 GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0, 415 RK3308_CLKGATE_CON(3), 11, GFLAGS), 416 GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0, 417 RK3308_CLKGATE_CON(3), 12, GFLAGS), 418 GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 0, 419 RK3308_CLKGATE_CON(3), 13, GFLAGS), 420 GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 0, 421 RK3308_CLKGATE_CON(3), 14, GFLAGS), 422 GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 0, 423 RK3308_CLKGATE_CON(3), 15, GFLAGS), 424 425 COMPOSITE_NOMUX(SCLK_TSADC, "clk_tsadc", "xin24m", 0, 426 RK3308_CLKSEL_CON(33), 0, 11, DFLAGS, 427 RK3308_CLKGATE_CON(3), 5, GFLAGS), 428 COMPOSITE_NOMUX(SCLK_SARADC, "clk_saradc", "xin24m", 0, 429 RK3308_CLKSEL_CON(34), 0, 11, DFLAGS, 430 RK3308_CLKGATE_CON(3), 6, GFLAGS), 431 432 COMPOSITE_NOMUX(SCLK_OTP, "clk_otp", "xin24m", 0, 433 RK3308_CLKSEL_CON(35), 0, 4, DFLAGS, 434 RK3308_CLKGATE_CON(3), 7, GFLAGS), 435 COMPOSITE_NOMUX(SCLK_OTP_USR, "clk_otp_usr", "clk_otp", 0, 436 RK3308_CLKSEL_CON(35), 4, 2, DFLAGS, 437 RK3308_CLKGATE_CON(3), 8, GFLAGS), 438 439 GATE(SCLK_CPU_BOOST, "clk_cpu_boost", "xin24m", CLK_IGNORE_UNUSED, 440 RK3308_CLKGATE_CON(3), 9, GFLAGS), 441 442 COMPOSITE(SCLK_CRYPTO, "clk_crypto", mux_dpll_vpll0_vpll1_p, 0, 443 RK3308_CLKSEL_CON(7), 6, 2, MFLAGS, 0, 5, DFLAGS, 444 RK3308_CLKGATE_CON(1), 4, GFLAGS), 445 COMPOSITE(SCLK_CRYPTO_APK, "clk_crypto_apk", mux_dpll_vpll0_vpll1_p, 0, 446 RK3308_CLKSEL_CON(7), 14, 2, MFLAGS, 8, 5, DFLAGS, 447 RK3308_CLKGATE_CON(1), 5, GFLAGS), 448 449 COMPOSITE(0, "dclk_vop_src", mux_dpll_vpll0_vpll1_p, 0, 450 RK3308_CLKSEL_CON(8), 10, 2, MFLAGS, 0, 8, DFLAGS, 451 RK3308_CLKGATE_CON(1), 6, GFLAGS), 452 COMPOSITE_FRACMUX(0, "dclk_vop_frac", "dclk_vop_src", CLK_SET_RATE_PARENT, 453 RK3308_CLKSEL_CON(9), 0, 454 RK3308_CLKGATE_CON(1), 7, GFLAGS, 455 &rk3308_dclk_vop_fracmux), 456 GATE(DCLK_VOP, "dclk_vop", "dclk_vop_mux", 0, 457 RK3308_CLKGATE_CON(1), 8, GFLAGS), 458 459 /* 460 * Clock-Architecture Diagram 4 461 */ 462 463 COMPOSITE_NODIV(ACLK_PERI_SRC, "clk_peri_src", mux_dpll_vpll0_vpll1_p, CLK_IGNORE_UNUSED, 464 RK3308_CLKSEL_CON(36), 6, 2, MFLAGS, 465 RK3308_CLKGATE_CON(8), 0, GFLAGS), 466 COMPOSITE_NOMUX(ACLK_PERI, "aclk_peri", "clk_peri_src", CLK_IGNORE_UNUSED, 467 RK3308_CLKSEL_CON(36), 0, 5, DFLAGS, 468 RK3308_CLKGATE_CON(8), 1, GFLAGS), 469 COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "clk_peri_src", CLK_IGNORE_UNUSED, 470 RK3308_CLKSEL_CON(37), 0, 5, DFLAGS, 471 RK3308_CLKGATE_CON(8), 2, GFLAGS), 472 COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "clk_peri_src", CLK_IGNORE_UNUSED, 473 RK3308_CLKSEL_CON(37), 8, 5, DFLAGS, 474 RK3308_CLKGATE_CON(8), 3, GFLAGS), 475 476 COMPOSITE(SCLK_NANDC_DIV, "clk_nandc_div", mux_dpll_vpll0_vpll1_p, CLK_IGNORE_UNUSED, 477 RK3308_CLKSEL_CON(38), 6, 2, MFLAGS, 0, 5, DFLAGS, 478 RK3308_CLKGATE_CON(8), 4, GFLAGS), 479 COMPOSITE(SCLK_NANDC_DIV50, "clk_nandc_div50", mux_dpll_vpll0_vpll1_p, CLK_IGNORE_UNUSED, 480 RK3308_CLKSEL_CON(38), 6, 2, MFLAGS, 0, 5, DFLAGS, 481 RK3308_CLKGATE_CON(8), 4, GFLAGS), 482 COMPOSITE_NODIV(SCLK_NANDC, "clk_nandc", mux_nandc_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 483 RK3308_CLKSEL_CON(38), 15, 1, MFLAGS, 484 RK3308_CLKGATE_CON(8), 5, GFLAGS), 485 486 COMPOSITE(SCLK_SDMMC_DIV, "clk_sdmmc_div", mux_dpll_vpll0_vpll1_xin24m_p, CLK_IGNORE_UNUSED, 487 RK3308_CLKSEL_CON(39), 8, 2, MFLAGS, 0, 8, DFLAGS, 488 RK3308_CLKGATE_CON(8), 6, GFLAGS), 489 COMPOSITE(SCLK_SDMMC_DIV50, "clk_sdmmc_div50", mux_dpll_vpll0_vpll1_xin24m_p, CLK_IGNORE_UNUSED, 490 RK3308_CLKSEL_CON(39), 8, 2, MFLAGS, 0, 8, DFLAGS, 491 RK3308_CLKGATE_CON(8), 6, GFLAGS), 492 COMPOSITE_NODIV(SCLK_SDMMC, "clk_sdmmc", mux_sdmmc_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 493 RK3308_CLKSEL_CON(39), 15, 1, MFLAGS, 494 RK3308_CLKGATE_CON(8), 7, GFLAGS), 495 MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "clk_sdmmc", RK3308_SDMMC_CON0, 1), 496 MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "clk_sdmmc", RK3308_SDMMC_CON1, 1), 497 498 COMPOSITE(SCLK_SDIO_DIV, "clk_sdio_div", mux_dpll_vpll0_vpll1_xin24m_p, CLK_IGNORE_UNUSED, 499 RK3308_CLKSEL_CON(40), 8, 2, MFLAGS, 0, 8, DFLAGS, 500 RK3308_CLKGATE_CON(8), 8, GFLAGS), 501 COMPOSITE(SCLK_SDIO_DIV50, "clk_sdio_div50", mux_dpll_vpll0_vpll1_xin24m_p, CLK_IGNORE_UNUSED, 502 RK3308_CLKSEL_CON(40), 8, 2, MFLAGS, 0, 8, DFLAGS, 503 RK3308_CLKGATE_CON(8), 8, GFLAGS), 504 COMPOSITE_NODIV(SCLK_SDIO, "clk_sdio", mux_sdio_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 505 RK3308_CLKSEL_CON(40), 15, 1, MFLAGS, 506 RK3308_CLKGATE_CON(8), 9, GFLAGS), 507 MMC(SCLK_SDIO_DRV, "sdio_drv", "clk_sdio", RK3308_SDIO_CON0, 1), 508 MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "clk_sdio", RK3308_SDIO_CON1, 1), 509 510 COMPOSITE(SCLK_EMMC_DIV, "clk_emmc_div", mux_dpll_vpll0_vpll1_xin24m_p, CLK_IGNORE_UNUSED, 511 RK3308_CLKSEL_CON(41), 8, 2, MFLAGS, 0, 8, DFLAGS, 512 RK3308_CLKGATE_CON(8), 10, GFLAGS), 513 COMPOSITE(SCLK_EMMC_DIV50, "clk_emmc_div50", mux_dpll_vpll0_vpll1_xin24m_p, CLK_IGNORE_UNUSED, 514 RK3308_CLKSEL_CON(41), 8, 2, MFLAGS, 0, 8, DFLAGS, 515 RK3308_CLKGATE_CON(8), 10, GFLAGS), 516 COMPOSITE_NODIV(SCLK_EMMC, "clk_emmc", mux_emmc_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 517 RK3308_CLKSEL_CON(41), 15, 1, MFLAGS, 518 RK3308_CLKGATE_CON(8), 11, GFLAGS), 519 MMC(SCLK_EMMC_DRV, "emmc_drv", "clk_emmc", RK3308_EMMC_CON0, 1), 520 MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "clk_emmc", RK3308_EMMC_CON1, 1), 521 522 COMPOSITE(SCLK_SFC, "clk_sfc", mux_dpll_vpll0_vpll1_p, 0, 523 RK3308_CLKSEL_CON(42), 14, 2, MFLAGS, 0, 7, DFLAGS, 524 RK3308_CLKGATE_CON(8), 12, GFLAGS), 525 526 GATE(SCLK_OTG_ADP, "clk_otg_adp", "clk_rtc32k", 0, 527 RK3308_CLKGATE_CON(8), 13, GFLAGS), 528 529 COMPOSITE(SCLK_MAC_SRC, "clk_mac_src", mux_dpll_vpll0_vpll1_p, 0, 530 RK3308_CLKSEL_CON(43), 6, 2, MFLAGS, 0, 5, DFLAGS, 531 RK3308_CLKGATE_CON(8), 14, GFLAGS), 532 MUX(SCLK_MAC, "clk_mac", mux_mac_p, CLK_SET_RATE_PARENT, 533 RK3308_CLKSEL_CON(43), 14, 1, MFLAGS), 534 GATE(SCLK_MAC_REF, "clk_mac_ref", "clk_mac", 0, 535 RK3308_CLKGATE_CON(9), 1, GFLAGS), 536 GATE(SCLK_MAC_RX_TX, "clk_mac_rx_tx", "clk_mac", 0, 537 RK3308_CLKGATE_CON(9), 0, GFLAGS), 538 FACTOR(0, "clk_mac_rx_tx_div2", "clk_mac_rx_tx", 0, 1, 2), 539 FACTOR(0, "clk_mac_rx_tx_div20", "clk_mac_rx_tx", 0, 1, 20), 540 MUX(SCLK_MAC_RMII, "clk_mac_rmii_sel", mux_mac_rmii_sel_p, CLK_SET_RATE_PARENT, 541 RK3308_CLKSEL_CON(43), 15, 1, MFLAGS), 542 543 COMPOSITE(SCLK_OWIRE, "clk_owire", mux_dpll_vpll0_xin24m_p, 0, 544 RK3308_CLKSEL_CON(44), 14, 2, MFLAGS, 8, 6, DFLAGS, 545 RK3308_CLKGATE_CON(8), 15, GFLAGS), 546 547 /* 548 * Clock-Architecture Diagram 5 549 */ 550 551 GATE(0, "clk_ddr_mon_timer", "xin24m", CLK_IGNORE_UNUSED, 552 RK3308_CLKGATE_CON(0), 12, GFLAGS), 553 554 GATE(0, "clk_ddr_mon", "clk_ddrphy1x_out", CLK_IGNORE_UNUSED, 555 RK3308_CLKGATE_CON(4), 10, GFLAGS), 556 GATE(0, "clk_ddr_upctrl", "clk_ddrphy1x_out", CLK_IGNORE_UNUSED, 557 RK3308_CLKGATE_CON(4), 11, GFLAGS), 558 GATE(0, "clk_ddr_msch", "clk_ddrphy1x_out", CLK_IGNORE_UNUSED, 559 RK3308_CLKGATE_CON(4), 12, GFLAGS), 560 GATE(0, "clk_ddr_msch_peribus", "clk_ddrphy1x_out", CLK_IGNORE_UNUSED, 561 RK3308_CLKGATE_CON(4), 13, GFLAGS), 562 563 COMPOSITE(SCLK_DDRCLK, "clk_ddrphy4x_src", mux_dpll_vpll0_vpll1_p, CLK_IGNORE_UNUSED, 564 RK3308_CLKSEL_CON(1), 6, 2, MFLAGS, 0, 3, DFLAGS, 565 RK3308_CLKGATE_CON(0), 10, GFLAGS), 566 GATE(0, "clk_ddrphy4x", "clk_ddrphy4x_src", CLK_IGNORE_UNUSED, 567 RK3308_CLKGATE_CON(0), 11, GFLAGS), 568 FACTOR_GATE(0, "clk_ddr_stdby_div4", "clk_ddrphy4x", CLK_IGNORE_UNUSED, 1, 4, 569 RK3308_CLKGATE_CON(0), 13, GFLAGS), 570 COMPOSITE_NODIV(0, "clk_ddrstdby", mux_ddrstdby_p, CLK_IGNORE_UNUSED, 571 RK3308_CLKSEL_CON(1), 8, 1, MFLAGS, 572 RK3308_CLKGATE_CON(4), 14, GFLAGS), 573 574 /* 575 * Clock-Architecture Diagram 6 576 */ 577 578 GATE(PCLK_PMU, "pclk_pmu", "pclk_bus", CLK_IGNORE_UNUSED, 579 RK3308_CLKGATE_CON(4), 5, GFLAGS), 580 GATE(SCLK_PMU, "clk_pmu", "pclk_bus", CLK_IGNORE_UNUSED, 581 RK3308_CLKGATE_CON(4), 6, GFLAGS), 582 583 COMPOSITE_FRACMUX(0, "clk_rtc32k_frac", "xin24m", CLK_IGNORE_UNUSED, 584 RK3308_CLKSEL_CON(3), 0, 585 RK3308_CLKGATE_CON(4), 3, GFLAGS, 586 &rk3308_rtc32k_fracmux), 587 MUX(0, "clk_rtc32k_div_src", mux_vpll0_vpll1_p, 0, 588 RK3308_CLKSEL_CON(2), 10, 1, MFLAGS), 589 COMPOSITE_NOMUX(0, "clk_rtc32k_div", "clk_rtc32k_div_src", CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 590 RK3308_CLKSEL_CON(4), 0, 16, DFLAGS, 591 RK3308_CLKGATE_CON(4), 2, GFLAGS), 592 593 COMPOSITE(0, "clk_usbphy_ref_src", mux_dpll_vpll0_p, 0, 594 RK3308_CLKSEL_CON(72), 6, 1, MFLAGS, 0, 6, DFLAGS, 595 RK3308_CLKGATE_CON(4), 7, GFLAGS), 596 COMPOSITE_NODIV(SCLK_USBPHY_REF, "clk_usbphy_ref", mux_usbphy_ref_p, CLK_SET_RATE_PARENT, 597 RK3308_CLKSEL_CON(72), 7, 1, MFLAGS, 598 RK3308_CLKGATE_CON(4), 8, GFLAGS), 599 600 GATE(0, "clk_wifi_dpll", "dpll", 0, 601 RK3308_CLKGATE_CON(15), 2, GFLAGS), 602 GATE(0, "clk_wifi_vpll0", "vpll0", 0, 603 RK3308_CLKGATE_CON(15), 3, GFLAGS), 604 GATE(0, "clk_wifi_osc", "xin24m", 0, 605 RK3308_CLKGATE_CON(15), 4, GFLAGS), 606 COMPOSITE(0, "clk_wifi_src", mux_wifi_src_p, 0, 607 RK3308_CLKSEL_CON(44), 6, 1, MFLAGS, 0, 6, DFLAGS, 608 RK3308_CLKGATE_CON(4), 0, GFLAGS), 609 COMPOSITE_NODIV(SCLK_WIFI, "clk_wifi", mux_wifi_p, CLK_SET_RATE_PARENT, 610 RK3308_CLKSEL_CON(44), 7, 1, MFLAGS, 611 RK3308_CLKGATE_CON(4), 1, GFLAGS), 612 613 GATE(SCLK_PVTM_PMU, "clk_pvtm_pmu", "xin24m", 0, 614 RK3308_CLKGATE_CON(4), 4, GFLAGS), 615 616 /* 617 * Clock-Architecture Diagram 7 618 */ 619 620 COMPOSITE_NODIV(0, "clk_audio_src", mux_vpll0_vpll1_xin24m_p, 0, 621 RK3308_CLKSEL_CON(45), 6, 2, MFLAGS, 622 RK3308_CLKGATE_CON(10), 0, GFLAGS), 623 COMPOSITE_NOMUX(HCLK_AUDIO, "hclk_audio", "clk_audio_src", 0, 624 RK3308_CLKSEL_CON(45), 0, 5, DFLAGS, 625 RK3308_CLKGATE_CON(10), 1, GFLAGS), 626 COMPOSITE_NOMUX(PCLK_AUDIO, "pclk_audio", "clk_audio_src", 0, 627 RK3308_CLKSEL_CON(45), 8, 5, DFLAGS, 628 RK3308_CLKGATE_CON(10), 2, GFLAGS), 629 630 COMPOSITE(0, "clk_pdm_src", mux_vpll0_vpll1_xin24m_p, 0, 631 RK3308_CLKSEL_CON(46), 8, 2, MFLAGS, 0, 7, DFLAGS, 632 RK3308_CLKGATE_CON(10), 3, GFLAGS), 633 COMPOSITE_FRACMUX(0, "clk_pdm_frac", "clk_pdm_src", CLK_SET_RATE_PARENT, 634 RK3308_CLKSEL_CON(47), 0, 635 RK3308_CLKGATE_CON(10), 4, GFLAGS, 636 &rk3308_pdm_fracmux), 637 GATE(SCLK_PDM, "clk_pdm", "clk_pdm_mux", 0, 638 RK3308_CLKGATE_CON(10), 5, GFLAGS), 639 640 COMPOSITE(SCLK_I2S0_8CH_TX_SRC, "clk_i2s0_8ch_tx_src", mux_vpll0_vpll1_xin24m_p, 0, 641 RK3308_CLKSEL_CON(52), 8, 2, MFLAGS, 0, 7, DFLAGS, 642 RK3308_CLKGATE_CON(10), 12, GFLAGS), 643 COMPOSITE_FRACMUX(0, "clk_i2s0_8ch_tx_frac", "clk_i2s0_8ch_tx_src", CLK_SET_RATE_PARENT, 644 RK3308_CLKSEL_CON(53), 0, 645 RK3308_CLKGATE_CON(10), 13, GFLAGS, 646 &rk3308_i2s0_8ch_tx_fracmux), 647 COMPOSITE_NODIV(SCLK_I2S0_8CH_TX, "clk_i2s0_8ch_tx", mux_i2s0_8ch_tx_rx_p, CLK_SET_RATE_PARENT, 648 RK3308_CLKSEL_CON(52), 12, 1, MFLAGS, 649 RK3308_CLKGATE_CON(10), 14, GFLAGS), 650 COMPOSITE_NODIV(SCLK_I2S0_8CH_TX_OUT, "clk_i2s0_8ch_tx_out", mux_i2s0_8ch_tx_out_p, CLK_SET_RATE_PARENT, 651 RK3308_CLKSEL_CON(52), 15, 1, MFLAGS, 652 RK3308_CLKGATE_CON(10), 15, GFLAGS), 653 654 COMPOSITE(SCLK_I2S0_8CH_RX_SRC, "clk_i2s0_8ch_rx_src", mux_vpll0_vpll1_xin24m_p, 0, 655 RK3308_CLKSEL_CON(54), 8, 2, MFLAGS, 0, 7, DFLAGS, 656 RK3308_CLKGATE_CON(11), 0, GFLAGS), 657 COMPOSITE_FRACMUX(0, "clk_i2s0_8ch_rx_frac", "clk_i2s0_8ch_rx_src", CLK_SET_RATE_PARENT, 658 RK3308_CLKSEL_CON(55), 0, 659 RK3308_CLKGATE_CON(11), 1, GFLAGS, 660 &rk3308_i2s0_8ch_rx_fracmux), 661 COMPOSITE_NODIV(SCLK_I2S0_8CH_RX, "clk_i2s0_8ch_rx", mux_i2s0_8ch_rx_tx_p, CLK_SET_RATE_PARENT, 662 RK3308_CLKSEL_CON(54), 12, 1, MFLAGS, 663 RK3308_CLKGATE_CON(11), 2, GFLAGS), 664 GATE(SCLK_I2S0_8CH_RX_OUT, "clk_i2s0_8ch_rx_out", "clk_i2s0_8ch_rx", 0, 665 RK3308_CLKGATE_CON(11), 3, GFLAGS), 666 667 COMPOSITE(SCLK_I2S1_8CH_TX_SRC, "clk_i2s1_8ch_tx_src", mux_vpll0_vpll1_xin24m_p, 0, 668 RK3308_CLKSEL_CON(56), 8, 2, MFLAGS, 0, 7, DFLAGS, 669 RK3308_CLKGATE_CON(11), 4, GFLAGS), 670 COMPOSITE_FRACMUX(0, "clk_i2s1_8ch_tx_frac", "clk_i2s1_8ch_tx_src", CLK_SET_RATE_PARENT, 671 RK3308_CLKSEL_CON(57), 0, 672 RK3308_CLKGATE_CON(11), 5, GFLAGS, 673 &rk3308_i2s1_8ch_tx_fracmux), 674 COMPOSITE_NODIV(SCLK_I2S1_8CH_TX, "clk_i2s1_8ch_tx", mux_i2s1_8ch_tx_rx_p, CLK_SET_RATE_PARENT, 675 RK3308_CLKSEL_CON(56), 12, 1, MFLAGS, 676 RK3308_CLKGATE_CON(11), 6, GFLAGS), 677 COMPOSITE_NODIV(SCLK_I2S1_8CH_TX_OUT, "clk_i2s1_8ch_tx_out", mux_i2s1_8ch_tx_out_p, CLK_SET_RATE_PARENT, 678 RK3308_CLKSEL_CON(56), 15, 1, MFLAGS, 679 RK3308_CLKGATE_CON(11), 7, GFLAGS), 680 681 COMPOSITE(SCLK_I2S1_8CH_RX_SRC, "clk_i2s1_8ch_rx_src", mux_vpll0_vpll1_xin24m_p, 0, 682 RK3308_CLKSEL_CON(58), 8, 2, MFLAGS, 0, 7, DFLAGS, 683 RK3308_CLKGATE_CON(11), 8, GFLAGS), 684 COMPOSITE_FRACMUX(0, "clk_i2s1_8ch_rx_frac", "clk_i2s1_8ch_rx_src", CLK_SET_RATE_PARENT, 685 RK3308_CLKSEL_CON(59), 0, 686 RK3308_CLKGATE_CON(11), 9, GFLAGS, 687 &rk3308_i2s1_8ch_rx_fracmux), 688 COMPOSITE_NODIV(SCLK_I2S1_8CH_RX, "clk_i2s1_8ch_rx", mux_i2s1_8ch_rx_tx_p, CLK_SET_RATE_PARENT, 689 RK3308_CLKSEL_CON(58), 12, 1, MFLAGS, 690 RK3308_CLKGATE_CON(11), 10, GFLAGS), 691 GATE(SCLK_I2S1_8CH_RX_OUT, "clk_i2s1_8ch_rx_out", "clk_i2s1_8ch_rx", 0, 692 RK3308_CLKGATE_CON(11), 11, GFLAGS), 693 694 COMPOSITE(SCLK_I2S2_8CH_TX_SRC, "clk_i2s2_8ch_tx_src", mux_vpll0_vpll1_xin24m_p, 0, 695 RK3308_CLKSEL_CON(60), 8, 2, MFLAGS, 0, 7, DFLAGS, 696 RK3308_CLKGATE_CON(11), 12, GFLAGS), 697 COMPOSITE_FRACMUX(0, "clk_i2s2_8ch_tx_frac", "clk_i2s2_8ch_tx_src", CLK_SET_RATE_PARENT, 698 RK3308_CLKSEL_CON(61), 0, 699 RK3308_CLKGATE_CON(11), 13, GFLAGS, 700 &rk3308_i2s2_8ch_tx_fracmux), 701 COMPOSITE_NODIV(SCLK_I2S2_8CH_TX, "clk_i2s2_8ch_tx", mux_i2s2_8ch_tx_rx_p, CLK_SET_RATE_PARENT, 702 RK3308_CLKSEL_CON(60), 12, 1, MFLAGS, 703 RK3308_CLKGATE_CON(11), 14, GFLAGS), 704 COMPOSITE_NODIV(SCLK_I2S2_8CH_TX_OUT, "clk_i2s2_8ch_tx_out", mux_i2s2_8ch_tx_out_p, CLK_SET_RATE_PARENT, 705 RK3308_CLKSEL_CON(60), 15, 1, MFLAGS, 706 RK3308_CLKGATE_CON(11), 15, GFLAGS), 707 708 COMPOSITE(SCLK_I2S2_8CH_RX_SRC, "clk_i2s2_8ch_rx_src", mux_vpll0_vpll1_xin24m_p, 0, 709 RK3308_CLKSEL_CON(62), 8, 2, MFLAGS, 0, 7, DFLAGS, 710 RK3308_CLKGATE_CON(12), 0, GFLAGS), 711 COMPOSITE_FRACMUX(0, "clk_i2s2_8ch_rx_frac", "clk_i2s2_8ch_rx_src", CLK_SET_RATE_PARENT, 712 RK3308_CLKSEL_CON(63), 0, 713 RK3308_CLKGATE_CON(12), 1, GFLAGS, 714 &rk3308_i2s2_8ch_rx_fracmux), 715 COMPOSITE_NODIV(SCLK_I2S2_8CH_RX, "clk_i2s2_8ch_rx", mux_i2s2_8ch_rx_tx_p, CLK_SET_RATE_PARENT, 716 RK3308_CLKSEL_CON(62), 12, 1, MFLAGS, 717 RK3308_CLKGATE_CON(12), 2, GFLAGS), 718 GATE(SCLK_I2S2_8CH_RX_OUT, "clk_i2s2_8ch_rx_out", "clk_i2s2_8ch_rx", 0, 719 RK3308_CLKGATE_CON(12), 3, GFLAGS), 720 721 COMPOSITE(SCLK_I2S3_8CH_TX_SRC, "clk_i2s3_8ch_tx_src", mux_vpll0_vpll1_xin24m_p, 0, 722 RK3308_CLKSEL_CON(64), 8, 2, MFLAGS, 0, 7, DFLAGS, 723 RK3308_CLKGATE_CON(12), 4, GFLAGS), 724 COMPOSITE_FRACMUX(0, "clk_i2s3_8ch_tx_frac", "clk_i2s3_8ch_tx_src", CLK_SET_RATE_PARENT, 725 RK3308_CLKSEL_CON(65), 0, 726 RK3308_CLKGATE_CON(12), 5, GFLAGS, 727 &rk3308_i2s3_8ch_tx_fracmux), 728 COMPOSITE_NODIV(SCLK_I2S3_8CH_TX, "clk_i2s3_8ch_tx", mux_i2s3_8ch_tx_rx_p, CLK_SET_RATE_PARENT, 729 RK3308_CLKSEL_CON(64), 12, 1, MFLAGS, 730 RK3308_CLKGATE_CON(12), 6, GFLAGS), 731 COMPOSITE_NODIV(SCLK_I2S3_8CH_TX_OUT, "clk_i2s3_8ch_tx_out", mux_i2s3_8ch_tx_out_p, CLK_SET_RATE_PARENT, 732 RK3308_CLKSEL_CON(64), 15, 1, MFLAGS, 733 RK3308_CLKGATE_CON(12), 7, GFLAGS), 734 735 COMPOSITE(SCLK_I2S3_8CH_RX_SRC, "clk_i2s3_8ch_rx_src", mux_vpll0_vpll1_xin24m_p, 0, 736 RK3308_CLKSEL_CON(66), 8, 2, MFLAGS, 0, 7, DFLAGS, 737 RK3308_CLKGATE_CON(12), 8, GFLAGS), 738 COMPOSITE_FRACMUX(0, "clk_i2s3_8ch_rx_frac", "clk_i2s3_8ch_rx_src", CLK_SET_RATE_PARENT, 739 RK3308_CLKSEL_CON(67), 0, 740 RK3308_CLKGATE_CON(12), 9, GFLAGS, 741 &rk3308_i2s3_8ch_rx_fracmux), 742 COMPOSITE_NODIV(SCLK_I2S3_8CH_RX, "clk_i2s3_8ch_rx", mux_i2s3_8ch_rx_tx_p, CLK_SET_RATE_PARENT, 743 RK3308_CLKSEL_CON(66), 12, 1, MFLAGS, 744 RK3308_CLKGATE_CON(12), 10, GFLAGS), 745 GATE(SCLK_I2S3_8CH_RX_OUT, "clk_i2s3_8ch_rx_out", "clk_i2s3_8ch_rx", 0, 746 RK3308_CLKGATE_CON(12), 11, GFLAGS), 747 748 COMPOSITE(SCLK_I2S0_2CH_SRC, "clk_i2s0_2ch_src", mux_vpll0_vpll1_xin24m_p, 0, 749 RK3308_CLKSEL_CON(68), 8, 2, MFLAGS, 0, 7, DFLAGS, 750 RK3308_CLKGATE_CON(12), 12, GFLAGS), 751 COMPOSITE_FRACMUX(0, "clk_i2s0_2ch_frac", "clk_i2s0_2ch_src", CLK_SET_RATE_PARENT, 752 RK3308_CLKSEL_CON(69), 0, 753 RK3308_CLKGATE_CON(12), 13, GFLAGS, 754 &rk3308_i2s0_2ch_fracmux), 755 GATE(SCLK_I2S0_2CH, "clk_i2s0_2ch", "clk_i2s0_2ch_mux", 0, 756 RK3308_CLKGATE_CON(12), 14, GFLAGS), 757 COMPOSITE_NODIV(SCLK_I2S0_2CH_OUT, "clk_i2s0_2ch_out", mux_i2s0_2ch_out_p, CLK_SET_RATE_PARENT, 758 RK3308_CLKSEL_CON(68), 15, 1, MFLAGS, 759 RK3308_CLKGATE_CON(12), 15, GFLAGS), 760 761 COMPOSITE(SCLK_I2S1_2CH_SRC, "clk_i2s1_2ch_src", mux_vpll0_vpll1_xin24m_p, 0, 762 RK3308_CLKSEL_CON(70), 8, 2, MFLAGS, 0, 7, DFLAGS, 763 RK3308_CLKGATE_CON(13), 0, GFLAGS), 764 COMPOSITE_FRACMUX(0, "clk_i2s1_2ch_frac", "clk_i2s1_2ch_src", CLK_SET_RATE_PARENT, 765 RK3308_CLKSEL_CON(71), 0, 766 RK3308_CLKGATE_CON(13), 1, GFLAGS, 767 &rk3308_i2s1_2ch_fracmux), 768 GATE(SCLK_I2S1_2CH, "clk_i2s1_2ch", "clk_i2s1_2ch_mux", 0, 769 RK3308_CLKGATE_CON(13), 2, GFLAGS), 770 COMPOSITE_NODIV(SCLK_I2S1_2CH_OUT, "clk_i2s1_2ch_out", mux_i2s1_2ch_out_p, CLK_SET_RATE_PARENT, 771 RK3308_CLKSEL_CON(70), 15, 1, MFLAGS, 772 RK3308_CLKGATE_CON(13), 3, GFLAGS), 773 774 COMPOSITE(SCLK_SPDIF_TX_DIV, "clk_spdif_tx_div", mux_vpll0_vpll1_xin24m_p, CLK_IGNORE_UNUSED, 775 RK3308_CLKSEL_CON(48), 8, 2, MFLAGS, 0, 7, DFLAGS, 776 RK3308_CLKGATE_CON(10), 6, GFLAGS), 777 COMPOSITE(SCLK_SPDIF_TX_DIV50, "clk_spdif_tx_div50", mux_vpll0_vpll1_xin24m_p, CLK_IGNORE_UNUSED, 778 RK3308_CLKSEL_CON(48), 8, 2, MFLAGS, 0, 7, DFLAGS, 779 RK3308_CLKGATE_CON(10), 6, GFLAGS), 780 MUX(0, "clk_spdif_tx_src", mux_spdif_tx_src_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 781 RK3308_CLKSEL_CON(48), 12, 1, MFLAGS), 782 COMPOSITE_FRACMUX(0, "clk_spdif_tx_frac", "clk_spdif_tx_src", CLK_SET_RATE_PARENT, 783 RK3308_CLKSEL_CON(49), 0, 784 RK3308_CLKGATE_CON(10), 7, GFLAGS, 785 &rk3308_spdif_tx_fracmux), 786 GATE(SCLK_SPDIF_TX, "clk_spdif_tx", "clk_spdif_tx_mux", 0, 787 RK3308_CLKGATE_CON(10), 8, GFLAGS), 788 789 COMPOSITE(SCLK_SPDIF_RX_DIV, "clk_spdif_rx_div", mux_vpll0_vpll1_xin24m_p, CLK_IGNORE_UNUSED, 790 RK3308_CLKSEL_CON(50), 8, 2, MFLAGS, 0, 7, DFLAGS, 791 RK3308_CLKGATE_CON(10), 9, GFLAGS), 792 COMPOSITE(SCLK_SPDIF_RX_DIV50, "clk_spdif_rx_div50", mux_vpll0_vpll1_xin24m_p, CLK_IGNORE_UNUSED, 793 RK3308_CLKSEL_CON(50), 8, 2, MFLAGS, 0, 7, DFLAGS, 794 RK3308_CLKGATE_CON(10), 9, GFLAGS), 795 MUX(0, "clk_spdif_rx_src", mux_spdif_rx_src_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 796 RK3308_CLKSEL_CON(50), 14, 1, MFLAGS), 797 COMPOSITE_FRACMUX(0, "clk_spdif_rx_frac", "clk_spdif_rx_src", CLK_SET_RATE_PARENT, 798 RK3308_CLKSEL_CON(51), 0, 799 RK3308_CLKGATE_CON(10), 10, GFLAGS, 800 &rk3308_spdif_rx_fracmux), 801 GATE(SCLK_SPDIF_RX, "clk_spdif_rx", "clk_spdif_rx_mux", 0, 802 RK3308_CLKGATE_CON(10), 11, GFLAGS), 803 804 /* 805 * Clock-Architecture Diagram 8 806 */ 807 808 GATE(0, "aclk_core_niu", "aclk_core", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(0), 5, GFLAGS), 809 GATE(0, "pclk_core_dbg_niu", "aclk_core", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(0), 6, GFLAGS), 810 GATE(0, "pclk_core_dbg_daplite", "pclk_core_dbg", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(0), 7, GFLAGS), 811 GATE(0, "aclk_core_perf", "pclk_core_dbg", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(0), 8, GFLAGS), 812 GATE(0, "pclk_core_grf", "pclk_core_dbg", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(0), 9, GFLAGS), 813 814 GATE(0, "aclk_peri_niu", "aclk_peri", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(9), 2, GFLAGS), 815 GATE(0, "aclk_peribus_niu", "aclk_peri", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(9), 3, GFLAGS), 816 GATE(ACLK_MAC, "aclk_mac", "aclk_peri", 0, RK3308_CLKGATE_CON(9), 4, GFLAGS), 817 818 GATE(0, "hclk_peri_niu", "hclk_peri", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(9), 5, GFLAGS), 819 GATE(HCLK_NANDC, "hclk_nandc", "hclk_peri", 0, RK3308_CLKGATE_CON(9), 6, GFLAGS), 820 GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK3308_CLKGATE_CON(9), 7, GFLAGS), 821 GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 0, RK3308_CLKGATE_CON(9), 8, GFLAGS), 822 GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK3308_CLKGATE_CON(9), 9, GFLAGS), 823 GATE(HCLK_SFC, "hclk_sfc", "hclk_peri", 0, RK3308_CLKGATE_CON(9), 10, GFLAGS), 824 GATE(HCLK_OTG, "hclk_otg", "hclk_peri", 0, RK3308_CLKGATE_CON(9), 11, GFLAGS), 825 GATE(HCLK_HOST, "hclk_host", "hclk_peri", 0, RK3308_CLKGATE_CON(9), 12, GFLAGS), 826 GATE(HCLK_HOST_ARB, "hclk_host_arb", "hclk_peri", 0, RK3308_CLKGATE_CON(9), 13, GFLAGS), 827 828 GATE(0, "pclk_peri_niu", "pclk_peri", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(9), 14, GFLAGS), 829 GATE(PCLK_MAC, "pclk_mac", "pclk_peri", 0, RK3308_CLKGATE_CON(9), 15, GFLAGS), 830 831 GATE(0, "hclk_audio_niu", "hclk_audio", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(14), 0, GFLAGS), 832 GATE(HCLK_PDM, "hclk_pdm", "hclk_audio", 0, RK3308_CLKGATE_CON(14), 1, GFLAGS), 833 GATE(HCLK_SPDIFTX, "hclk_spdiftx", "hclk_audio", 0, RK3308_CLKGATE_CON(14), 2, GFLAGS), 834 GATE(HCLK_SPDIFRX, "hclk_spdifrx", "hclk_audio", 0, RK3308_CLKGATE_CON(14), 3, GFLAGS), 835 GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_audio", 0, RK3308_CLKGATE_CON(14), 4, GFLAGS), 836 GATE(HCLK_I2S1_8CH, "hclk_i2s1_8ch", "hclk_audio", 0, RK3308_CLKGATE_CON(14), 5, GFLAGS), 837 GATE(HCLK_I2S2_8CH, "hclk_i2s2_8ch", "hclk_audio", 0, RK3308_CLKGATE_CON(14), 6, GFLAGS), 838 GATE(HCLK_I2S3_8CH, "hclk_i2s3_8ch", "hclk_audio", 0, RK3308_CLKGATE_CON(14), 7, GFLAGS), 839 GATE(HCLK_I2S0_2CH, "hclk_i2s0_2ch", "hclk_audio", 0, RK3308_CLKGATE_CON(14), 8, GFLAGS), 840 GATE(HCLK_I2S1_2CH, "hclk_i2s1_2ch", "hclk_audio", 0, RK3308_CLKGATE_CON(14), 9, GFLAGS), 841 GATE(HCLK_VAD, "hclk_vad", "hclk_audio", 0, RK3308_CLKGATE_CON(14), 10, GFLAGS), 842 843 GATE(0, "pclk_audio_niu", "pclk_audio", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(14), 11, GFLAGS), 844 GATE(PCLK_ACODEC, "pclk_acodec", "pclk_audio", 0, RK3308_CLKGATE_CON(14), 12, GFLAGS), 845 846 GATE(0, "aclk_bus_niu", "aclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(5), 0, GFLAGS), 847 GATE(0, "aclk_intmem", "aclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(5), 1, GFLAGS), 848 GATE(ACLK_CRYPTO, "aclk_crypto", "aclk_bus", 0, RK3308_CLKGATE_CON(5), 2, GFLAGS), 849 GATE(ACLK_VOP, "aclk_vop", "aclk_bus", 0, RK3308_CLKGATE_CON(5), 3, GFLAGS), 850 GATE(0, "aclk_gic", "aclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(5), 4, GFLAGS), 851 /* aclk_dmaci0 is controlled by sgrf_clkgat_con. */ 852 SGRF_GATE(ACLK_DMAC0, "aclk_dmac0", "aclk_bus"), 853 /* aclk_dmac1 is controlled by sgrf_clkgat_con. */ 854 SGRF_GATE(ACLK_DMAC1, "aclk_dmac1", "aclk_bus"), 855 /* watchdog pclk is controlled by sgrf_clkgat_con. */ 856 SGRF_GATE(PCLK_WDT, "pclk_wdt", "pclk_bus"), 857 858 GATE(0, "hclk_bus_niu", "hclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(5), 5, GFLAGS), 859 GATE(0, "hclk_rom", "hclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(5), 6, GFLAGS), 860 GATE(HCLK_CRYPTO, "hclk_crypto", "hclk_bus", 0, RK3308_CLKGATE_CON(5), 7, GFLAGS), 861 GATE(HCLK_VOP, "hclk_vop", "hclk_bus", 0, RK3308_CLKGATE_CON(5), 8, GFLAGS), 862 863 GATE(0, "pclk_bus_niu", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(5), 9, GFLAGS), 864 GATE(PCLK_UART0, "pclk_uart0", "pclk_bus", 0, RK3308_CLKGATE_CON(5), 10, GFLAGS), 865 GATE(PCLK_UART1, "pclk_uart1", "pclk_bus", 0, RK3308_CLKGATE_CON(5), 11, GFLAGS), 866 GATE(PCLK_UART2, "pclk_uart2", "pclk_bus", 0, RK3308_CLKGATE_CON(5), 12, GFLAGS), 867 GATE(PCLK_UART3, "pclk_uart3", "pclk_bus", 0, RK3308_CLKGATE_CON(5), 13, GFLAGS), 868 GATE(PCLK_UART4, "pclk_uart4", "pclk_bus", 0, RK3308_CLKGATE_CON(5), 14, GFLAGS), 869 GATE(PCLK_I2C0, "pclk_i2c0", "pclk_bus", 0, RK3308_CLKGATE_CON(5), 15, GFLAGS), 870 GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 0, GFLAGS), 871 GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 1, GFLAGS), 872 GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 2, GFLAGS), 873 GATE(PCLK_PWM0, "pclk_pwm0", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 3, GFLAGS), 874 GATE(PCLK_SPI0, "pclk_spi0", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 4, GFLAGS), 875 GATE(PCLK_SPI1, "pclk_spi1", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 5, GFLAGS), 876 GATE(PCLK_SPI2, "pclk_spi2", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 6, GFLAGS), 877 GATE(PCLK_SARADC, "pclk_saradc", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 7, GFLAGS), 878 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 8, GFLAGS), 879 GATE(PCLK_TIMER, "pclk_timer", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 9, GFLAGS), 880 GATE(PCLK_OTP_NS, "pclk_otp_ns", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 10, GFLAGS), 881 GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 12, GFLAGS), 882 GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 13, GFLAGS), 883 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 14, GFLAGS), 884 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 15, GFLAGS), 885 GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_bus", 0, RK3308_CLKGATE_CON(7), 0, GFLAGS), 886 GATE(PCLK_SGRF, "pclk_sgrf", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 1, GFLAGS), 887 GATE(PCLK_GRF, "pclk_grf", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 2, GFLAGS), 888 GATE(PCLK_USBSD_DET, "pclk_usbsd_det", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 3, GFLAGS), 889 GATE(PCLK_DDR_UPCTL, "pclk_ddr_upctl", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 4, GFLAGS), 890 GATE(PCLK_DDR_MON, "pclk_ddr_mon", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 5, GFLAGS), 891 GATE(PCLK_DDRPHY, "pclk_ddrphy", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 6, GFLAGS), 892 GATE(PCLK_DDR_STDBY, "pclk_ddr_stdby", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 7, GFLAGS), 893 GATE(PCLK_USB_GRF, "pclk_usb_grf", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 8, GFLAGS), 894 GATE(PCLK_CRU, "pclk_cru", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 9, GFLAGS), 895 GATE(PCLK_OTP_PHY, "pclk_otp_phy", "pclk_bus", 0, RK3308_CLKGATE_CON(7), 10, GFLAGS), 896 GATE(PCLK_CPU_BOOST, "pclk_cpu_boost", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 11, GFLAGS), 897 GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 12, GFLAGS), 898 GATE(PCLK_PWM2, "pclk_pwm2", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 13, GFLAGS), 899 GATE(PCLK_CAN, "pclk_can", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 14, GFLAGS), 900 GATE(PCLK_OWIRE, "pclk_owire", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 15, GFLAGS), 901}; 902 903static const char *const rk3308_critical_clocks[] __initconst = { 904 "aclk_bus", 905 "hclk_bus", 906 "pclk_bus", 907 "aclk_peri", 908 "hclk_peri", 909 "pclk_peri", 910 "hclk_audio", 911 "pclk_audio", 912 "sclk_ddrc", 913}; 914 915static void __init rk3308_clk_init(struct device_node *np) 916{ 917 struct rockchip_clk_provider *ctx; 918 void __iomem *reg_base; 919 920 reg_base = of_iomap(np, 0); 921 if (!reg_base) { 922 pr_err("%s: could not map cru region\n", __func__); 923 return; 924 } 925 926 ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS); 927 if (IS_ERR(ctx)) { 928 pr_err("%s: rockchip clk init failed\n", __func__); 929 iounmap(reg_base); 930 return; 931 } 932 933 rockchip_clk_register_plls(ctx, rk3308_pll_clks, 934 ARRAY_SIZE(rk3308_pll_clks), 935 RK3308_GRF_SOC_STATUS0); 936 rockchip_clk_register_branches(ctx, rk3308_clk_branches, 937 ARRAY_SIZE(rk3308_clk_branches)); 938 rockchip_clk_protect_critical(rk3308_critical_clocks, 939 ARRAY_SIZE(rk3308_critical_clocks)); 940 941 rockchip_clk_register_armclk(ctx, ARMCLK, "armclk", 942 mux_armclk_p, ARRAY_SIZE(mux_armclk_p), 943 &rk3308_cpuclk_data, rk3308_cpuclk_rates, 944 ARRAY_SIZE(rk3308_cpuclk_rates)); 945 946 rockchip_register_softrst(np, 10, reg_base + RK3308_SOFTRST_CON(0), 947 ROCKCHIP_SOFTRST_HIWORD_MASK); 948 949 rockchip_register_restart_notifier(ctx, RK3308_GLB_SRST_FST, NULL); 950 951 rockchip_clk_of_add_provider(np, ctx); 952} 953 954CLK_OF_DECLARE(rk3308_cru, "rockchip,rk3308-cru", rk3308_clk_init); 955