1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * Copyright (c) 2014 MundoReader S.L. 4 * Author: Heiko Stuebner <heiko@sntech.de> 5 */ 6 7#include <linux/clk.h> 8#include <linux/clk-provider.h> 9#include <linux/io.h> 10#include <linux/of.h> 11#include <linux/of_address.h> 12#include <dt-bindings/clock/rk3188-cru-common.h> 13#include "clk.h" 14 15#define RK3066_GRF_SOC_STATUS 0x15c 16#define RK3188_GRF_SOC_STATUS 0xac 17 18enum rk3188_plls { 19 apll, cpll, dpll, gpll, 20}; 21 22static struct rockchip_pll_rate_table rk3188_pll_rates[] = { 23 RK3066_PLL_RATE(2208000000, 1, 92, 1), 24 RK3066_PLL_RATE(2184000000, 1, 91, 1), 25 RK3066_PLL_RATE(2160000000, 1, 90, 1), 26 RK3066_PLL_RATE(2136000000, 1, 89, 1), 27 RK3066_PLL_RATE(2112000000, 1, 88, 1), 28 RK3066_PLL_RATE(2088000000, 1, 87, 1), 29 RK3066_PLL_RATE(2064000000, 1, 86, 1), 30 RK3066_PLL_RATE(2040000000, 1, 85, 1), 31 RK3066_PLL_RATE(2016000000, 1, 84, 1), 32 RK3066_PLL_RATE(1992000000, 1, 83, 1), 33 RK3066_PLL_RATE(1968000000, 1, 82, 1), 34 RK3066_PLL_RATE(1944000000, 1, 81, 1), 35 RK3066_PLL_RATE(1920000000, 1, 80, 1), 36 RK3066_PLL_RATE(1896000000, 1, 79, 1), 37 RK3066_PLL_RATE(1872000000, 1, 78, 1), 38 RK3066_PLL_RATE(1848000000, 1, 77, 1), 39 RK3066_PLL_RATE(1824000000, 1, 76, 1), 40 RK3066_PLL_RATE(1800000000, 1, 75, 1), 41 RK3066_PLL_RATE(1776000000, 1, 74, 1), 42 RK3066_PLL_RATE(1752000000, 1, 73, 1), 43 RK3066_PLL_RATE(1728000000, 1, 72, 1), 44 RK3066_PLL_RATE(1704000000, 1, 71, 1), 45 RK3066_PLL_RATE(1680000000, 1, 70, 1), 46 RK3066_PLL_RATE(1656000000, 1, 69, 1), 47 RK3066_PLL_RATE(1632000000, 1, 68, 1), 48 RK3066_PLL_RATE(1608000000, 1, 67, 1), 49 RK3066_PLL_RATE(1560000000, 1, 65, 1), 50 RK3066_PLL_RATE(1512000000, 1, 63, 1), 51 RK3066_PLL_RATE(1488000000, 1, 62, 1), 52 RK3066_PLL_RATE(1464000000, 1, 61, 1), 53 RK3066_PLL_RATE(1440000000, 1, 60, 1), 54 RK3066_PLL_RATE(1416000000, 1, 59, 1), 55 RK3066_PLL_RATE(1392000000, 1, 58, 1), 56 RK3066_PLL_RATE(1368000000, 1, 57, 1), 57 RK3066_PLL_RATE(1344000000, 1, 56, 1), 58 RK3066_PLL_RATE(1320000000, 1, 55, 1), 59 RK3066_PLL_RATE(1296000000, 1, 54, 1), 60 RK3066_PLL_RATE(1272000000, 1, 53, 1), 61 RK3066_PLL_RATE(1248000000, 1, 52, 1), 62 RK3066_PLL_RATE(1224000000, 1, 51, 1), 63 RK3066_PLL_RATE(1200000000, 1, 50, 1), 64 RK3066_PLL_RATE(1188000000, 2, 99, 1), 65 RK3066_PLL_RATE(1176000000, 1, 49, 1), 66 RK3066_PLL_RATE(1128000000, 1, 47, 1), 67 RK3066_PLL_RATE(1104000000, 1, 46, 1), 68 RK3066_PLL_RATE(1008000000, 1, 84, 2), 69 RK3066_PLL_RATE( 912000000, 1, 76, 2), 70 RK3066_PLL_RATE( 891000000, 8, 594, 2), 71 RK3066_PLL_RATE( 888000000, 1, 74, 2), 72 RK3066_PLL_RATE( 816000000, 1, 68, 2), 73 RK3066_PLL_RATE( 798000000, 2, 133, 2), 74 RK3066_PLL_RATE( 792000000, 1, 66, 2), 75 RK3066_PLL_RATE( 768000000, 1, 64, 2), 76 RK3066_PLL_RATE( 742500000, 8, 495, 2), 77 RK3066_PLL_RATE( 696000000, 1, 58, 2), 78 RK3066_PLL_RATE( 600000000, 1, 50, 2), 79 RK3066_PLL_RATE( 594000000, 2, 198, 4), 80 RK3066_PLL_RATE( 552000000, 1, 46, 2), 81 RK3066_PLL_RATE( 504000000, 1, 84, 4), 82 RK3066_PLL_RATE( 456000000, 1, 76, 4), 83 RK3066_PLL_RATE( 408000000, 1, 68, 4), 84 RK3066_PLL_RATE( 400000000, 3, 100, 2), 85 RK3066_PLL_RATE( 384000000, 2, 128, 4), 86 RK3066_PLL_RATE( 360000000, 1, 60, 4), 87 RK3066_PLL_RATE( 312000000, 1, 52, 4), 88 RK3066_PLL_RATE( 300000000, 1, 50, 4), 89 RK3066_PLL_RATE( 297000000, 2, 198, 8), 90 RK3066_PLL_RATE( 252000000, 1, 84, 8), 91 RK3066_PLL_RATE( 216000000, 1, 72, 8), 92 RK3066_PLL_RATE( 148500000, 2, 99, 8), 93 RK3066_PLL_RATE( 126000000, 1, 84, 16), 94 RK3066_PLL_RATE( 48000000, 1, 64, 32), 95 { /* sentinel */ }, 96}; 97 98#define RK3066_DIV_CORE_PERIPH_MASK 0x3 99#define RK3066_DIV_CORE_PERIPH_SHIFT 6 100#define RK3066_DIV_ACLK_CORE_MASK 0x7 101#define RK3066_DIV_ACLK_CORE_SHIFT 0 102#define RK3066_DIV_ACLK_HCLK_MASK 0x3 103#define RK3066_DIV_ACLK_HCLK_SHIFT 8 104#define RK3066_DIV_ACLK_PCLK_MASK 0x3 105#define RK3066_DIV_ACLK_PCLK_SHIFT 12 106#define RK3066_DIV_AHB2APB_MASK 0x3 107#define RK3066_DIV_AHB2APB_SHIFT 14 108 109#define RK3066_CLKSEL0(_core_peri) \ 110 { \ 111 .reg = RK2928_CLKSEL_CON(0), \ 112 .val = HIWORD_UPDATE(_core_peri, RK3066_DIV_CORE_PERIPH_MASK, \ 113 RK3066_DIV_CORE_PERIPH_SHIFT) \ 114 } 115#define RK3066_CLKSEL1(_aclk_core, _aclk_hclk, _aclk_pclk, _ahb2apb) \ 116 { \ 117 .reg = RK2928_CLKSEL_CON(1), \ 118 .val = HIWORD_UPDATE(_aclk_core, RK3066_DIV_ACLK_CORE_MASK, \ 119 RK3066_DIV_ACLK_CORE_SHIFT) | \ 120 HIWORD_UPDATE(_aclk_hclk, RK3066_DIV_ACLK_HCLK_MASK, \ 121 RK3066_DIV_ACLK_HCLK_SHIFT) | \ 122 HIWORD_UPDATE(_aclk_pclk, RK3066_DIV_ACLK_PCLK_MASK, \ 123 RK3066_DIV_ACLK_PCLK_SHIFT) | \ 124 HIWORD_UPDATE(_ahb2apb, RK3066_DIV_AHB2APB_MASK, \ 125 RK3066_DIV_AHB2APB_SHIFT), \ 126 } 127 128#define RK3066_CPUCLK_RATE(_prate, _core_peri, _acore, _ahclk, _apclk, _h2p) \ 129 { \ 130 .prate = _prate, \ 131 .divs = { \ 132 RK3066_CLKSEL0(_core_peri), \ 133 RK3066_CLKSEL1(_acore, _ahclk, _apclk, _h2p), \ 134 }, \ 135 } 136 137static struct rockchip_cpuclk_rate_table rk3066_cpuclk_rates[] __initdata = { 138 RK3066_CPUCLK_RATE(1416000000, 2, 3, 1, 2, 1), 139 RK3066_CPUCLK_RATE(1200000000, 2, 3, 1, 2, 1), 140 RK3066_CPUCLK_RATE(1008000000, 2, 2, 1, 2, 1), 141 RK3066_CPUCLK_RATE( 816000000, 2, 2, 1, 2, 1), 142 RK3066_CPUCLK_RATE( 600000000, 1, 2, 1, 2, 1), 143 RK3066_CPUCLK_RATE( 504000000, 1, 1, 1, 2, 1), 144 RK3066_CPUCLK_RATE( 312000000, 0, 1, 1, 1, 0), 145}; 146 147static const struct rockchip_cpuclk_reg_data rk3066_cpuclk_data = { 148 .core_reg = RK2928_CLKSEL_CON(0), 149 .div_core_shift = 0, 150 .div_core_mask = 0x1f, 151 .mux_core_alt = 1, 152 .mux_core_main = 0, 153 .mux_core_shift = 8, 154 .mux_core_mask = 0x1, 155}; 156 157#define RK3188_DIV_ACLK_CORE_MASK 0x7 158#define RK3188_DIV_ACLK_CORE_SHIFT 3 159 160#define RK3188_CLKSEL1(_aclk_core) \ 161 { \ 162 .reg = RK2928_CLKSEL_CON(1), \ 163 .val = HIWORD_UPDATE(_aclk_core, RK3188_DIV_ACLK_CORE_MASK,\ 164 RK3188_DIV_ACLK_CORE_SHIFT) \ 165 } 166#define RK3188_CPUCLK_RATE(_prate, _core_peri, _aclk_core) \ 167 { \ 168 .prate = _prate, \ 169 .divs = { \ 170 RK3066_CLKSEL0(_core_peri), \ 171 RK3188_CLKSEL1(_aclk_core), \ 172 }, \ 173 } 174 175static struct rockchip_cpuclk_rate_table rk3188_cpuclk_rates[] __initdata = { 176 RK3188_CPUCLK_RATE(1608000000, 2, 3), 177 RK3188_CPUCLK_RATE(1416000000, 2, 3), 178 RK3188_CPUCLK_RATE(1200000000, 2, 3), 179 RK3188_CPUCLK_RATE(1008000000, 2, 3), 180 RK3188_CPUCLK_RATE( 816000000, 2, 3), 181 RK3188_CPUCLK_RATE( 600000000, 1, 3), 182 RK3188_CPUCLK_RATE( 504000000, 1, 3), 183 RK3188_CPUCLK_RATE( 312000000, 0, 1), 184}; 185 186static const struct rockchip_cpuclk_reg_data rk3188_cpuclk_data = { 187 .core_reg = RK2928_CLKSEL_CON(0), 188 .div_core_shift = 9, 189 .div_core_mask = 0x1f, 190 .mux_core_alt = 1, 191 .mux_core_main = 0, 192 .mux_core_shift = 8, 193 .mux_core_mask = 0x1, 194}; 195 196PNAME(mux_pll_p) = { "xin24m", "xin32k" }; 197PNAME(mux_armclk_p) = { "apll", "gpll_armclk" }; 198PNAME(mux_ddrphy_p) = { "dpll", "gpll_ddr" }; 199PNAME(mux_pll_src_gpll_cpll_p) = { "gpll", "cpll" }; 200PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" }; 201PNAME(mux_aclk_cpu_p) = { "apll", "gpll" }; 202PNAME(mux_sclk_cif0_p) = { "cif0_pre", "xin24m" }; 203PNAME(mux_sclk_i2s0_p) = { "i2s0_pre", "i2s0_frac", "xin12m" }; 204PNAME(mux_sclk_spdif_p) = { "spdif_pre", "spdif_frac", "xin12m" }; 205PNAME(mux_sclk_uart0_p) = { "uart0_pre", "uart0_frac", "xin24m" }; 206PNAME(mux_sclk_uart1_p) = { "uart1_pre", "uart1_frac", "xin24m" }; 207PNAME(mux_sclk_uart2_p) = { "uart2_pre", "uart2_frac", "xin24m" }; 208PNAME(mux_sclk_uart3_p) = { "uart3_pre", "uart3_frac", "xin24m" }; 209PNAME(mux_sclk_hsadc_p) = { "hsadc_src", "hsadc_frac", "ext_hsadc" }; 210PNAME(mux_mac_p) = { "gpll", "dpll" }; 211PNAME(mux_sclk_macref_p) = { "mac_src", "ext_rmii" }; 212 213static struct rockchip_pll_clock rk3066_pll_clks[] __initdata = { 214 [apll] = PLL(pll_rk3066, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0), 215 RK2928_MODE_CON, 0, 5, 0, rk3188_pll_rates), 216 [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4), 217 RK2928_MODE_CON, 4, 4, 0, NULL), 218 [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(8), 219 RK2928_MODE_CON, 8, 6, ROCKCHIP_PLL_SYNC_RATE, rk3188_pll_rates), 220 [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(12), 221 RK2928_MODE_CON, 12, 7, ROCKCHIP_PLL_SYNC_RATE, rk3188_pll_rates), 222}; 223 224static struct rockchip_pll_clock rk3188_pll_clks[] __initdata = { 225 [apll] = PLL(pll_rk3066, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0), 226 RK2928_MODE_CON, 0, 6, 0, rk3188_pll_rates), 227 [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4), 228 RK2928_MODE_CON, 4, 5, 0, NULL), 229 [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(8), 230 RK2928_MODE_CON, 8, 7, ROCKCHIP_PLL_SYNC_RATE, rk3188_pll_rates), 231 [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(12), 232 RK2928_MODE_CON, 12, 8, ROCKCHIP_PLL_SYNC_RATE, rk3188_pll_rates), 233}; 234 235#define MFLAGS CLK_MUX_HIWORD_MASK 236#define DFLAGS CLK_DIVIDER_HIWORD_MASK 237#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE) 238#define IFLAGS ROCKCHIP_INVERTER_HIWORD_MASK 239 240/* 2 ^ (val + 1) */ 241static struct clk_div_table div_core_peri_t[] = { 242 { .val = 0, .div = 2 }, 243 { .val = 1, .div = 4 }, 244 { .val = 2, .div = 8 }, 245 { .val = 3, .div = 16 }, 246 { /* sentinel */ }, 247}; 248 249static struct rockchip_clk_branch common_hsadc_out_fracmux __initdata = 250 MUX(0, "sclk_hsadc_out", mux_sclk_hsadc_p, 0, 251 RK2928_CLKSEL_CON(22), 4, 2, MFLAGS); 252 253static struct rockchip_clk_branch common_spdif_fracmux __initdata = 254 MUX(SCLK_SPDIF, "sclk_spdif", mux_sclk_spdif_p, CLK_SET_RATE_PARENT, 255 RK2928_CLKSEL_CON(5), 8, 2, MFLAGS); 256 257static struct rockchip_clk_branch common_uart0_fracmux __initdata = 258 MUX(SCLK_UART0, "sclk_uart0", mux_sclk_uart0_p, 0, 259 RK2928_CLKSEL_CON(13), 8, 2, MFLAGS); 260 261static struct rockchip_clk_branch common_uart1_fracmux __initdata = 262 MUX(SCLK_UART1, "sclk_uart1", mux_sclk_uart1_p, 0, 263 RK2928_CLKSEL_CON(14), 8, 2, MFLAGS); 264 265static struct rockchip_clk_branch common_uart2_fracmux __initdata = 266 MUX(SCLK_UART2, "sclk_uart2", mux_sclk_uart2_p, 0, 267 RK2928_CLKSEL_CON(15), 8, 2, MFLAGS); 268 269static struct rockchip_clk_branch common_uart3_fracmux __initdata = 270 MUX(SCLK_UART3, "sclk_uart3", mux_sclk_uart3_p, 0, 271 RK2928_CLKSEL_CON(16), 8, 2, MFLAGS); 272 273static struct rockchip_clk_branch common_clk_branches[] __initdata = { 274 /* 275 * Clock-Architecture Diagram 2 276 */ 277 278 GATE(0, "gpll_armclk", "gpll", 0, RK2928_CLKGATE_CON(0), 1, GFLAGS), 279 280 /* these two are set by the cpuclk and should not be changed */ 281 COMPOSITE_NOMUX_DIVTBL(CORE_PERI, "core_peri", "armclk", 0, 282 RK2928_CLKSEL_CON(0), 6, 2, DFLAGS | CLK_DIVIDER_READ_ONLY, 283 div_core_peri_t, RK2928_CLKGATE_CON(0), 0, GFLAGS), 284 285 COMPOSITE(ACLK_VEPU, "aclk_vepu", mux_pll_src_cpll_gpll_p, 0, 286 RK2928_CLKSEL_CON(32), 7, 1, MFLAGS, 0, 5, DFLAGS, 287 RK2928_CLKGATE_CON(3), 9, GFLAGS), 288 GATE(HCLK_VEPU, "hclk_vepu", "aclk_vepu", 0, 289 RK2928_CLKGATE_CON(3), 10, GFLAGS), 290 COMPOSITE(ACLK_VDPU, "aclk_vdpu", mux_pll_src_cpll_gpll_p, 0, 291 RK2928_CLKSEL_CON(32), 15, 1, MFLAGS, 8, 5, DFLAGS, 292 RK2928_CLKGATE_CON(3), 11, GFLAGS), 293 GATE(HCLK_VDPU, "hclk_vdpu", "aclk_vdpu", 0, 294 RK2928_CLKGATE_CON(3), 12, GFLAGS), 295 296 GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED, 297 RK2928_CLKGATE_CON(1), 7, GFLAGS), 298 COMPOSITE(0, "ddrphy", mux_ddrphy_p, CLK_IGNORE_UNUSED, 299 RK2928_CLKSEL_CON(26), 8, 1, MFLAGS, 0, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO, 300 RK2928_CLKGATE_CON(0), 2, GFLAGS), 301 302 GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_pre", 0, 303 RK2928_CLKGATE_CON(0), 3, GFLAGS), 304 305 GATE(0, "atclk_cpu", "pclk_cpu_pre", 0, 306 RK2928_CLKGATE_CON(0), 6, GFLAGS), 307 GATE(PCLK_CPU, "pclk_cpu", "pclk_cpu_pre", 0, 308 RK2928_CLKGATE_CON(0), 5, GFLAGS), 309 GATE(HCLK_CPU, "hclk_cpu", "hclk_cpu_pre", CLK_IGNORE_UNUSED, 310 RK2928_CLKGATE_CON(0), 4, GFLAGS), 311 312 COMPOSITE(0, "aclk_lcdc0_pre", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED, 313 RK2928_CLKSEL_CON(31), 7, 1, MFLAGS, 0, 5, DFLAGS, 314 RK2928_CLKGATE_CON(3), 0, GFLAGS), 315 COMPOSITE(0, "aclk_lcdc1_pre", mux_pll_src_cpll_gpll_p, 0, 316 RK2928_CLKSEL_CON(31), 15, 1, MFLAGS, 8, 5, DFLAGS, 317 RK2928_CLKGATE_CON(1), 4, GFLAGS), 318 319 GATE(ACLK_PERI, "aclk_peri", "aclk_peri_pre", 0, 320 RK2928_CLKGATE_CON(2), 1, GFLAGS), 321 COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_pre", 0, 322 RK2928_CLKSEL_CON(10), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO, 323 RK2928_CLKGATE_CON(2), 2, GFLAGS), 324 COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_pre", 0, 325 RK2928_CLKSEL_CON(10), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO, 326 RK2928_CLKGATE_CON(2), 3, GFLAGS), 327 328 MUX(0, "cif_src", mux_pll_src_cpll_gpll_p, 0, 329 RK2928_CLKSEL_CON(29), 0, 1, MFLAGS), 330 COMPOSITE_NOMUX(0, "cif0_pre", "cif_src", 0, 331 RK2928_CLKSEL_CON(29), 1, 5, DFLAGS, 332 RK2928_CLKGATE_CON(3), 7, GFLAGS), 333 MUX(SCLK_CIF0, "sclk_cif0", mux_sclk_cif0_p, 0, 334 RK2928_CLKSEL_CON(29), 7, 1, MFLAGS), 335 336 GATE(0, "pclkin_cif0", "ext_cif0", 0, 337 RK2928_CLKGATE_CON(3), 3, GFLAGS), 338 INVERTER(0, "pclk_cif0", "pclkin_cif0", 339 RK2928_CLKSEL_CON(30), 8, IFLAGS), 340 341 FACTOR(0, "xin12m", "xin24m", 0, 1, 2), 342 343 /* 344 * the 480m are generated inside the usb block from these clocks, 345 * but they are also a source for the hsicphy clock. 346 */ 347 GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin24m", CLK_IGNORE_UNUSED, 348 RK2928_CLKGATE_CON(1), 5, GFLAGS), 349 GATE(SCLK_OTGPHY1, "sclk_otgphy1", "xin24m", CLK_IGNORE_UNUSED, 350 RK2928_CLKGATE_CON(1), 6, GFLAGS), 351 352 COMPOSITE(0, "mac_src", mux_mac_p, 0, 353 RK2928_CLKSEL_CON(21), 0, 1, MFLAGS, 8, 5, DFLAGS, 354 RK2928_CLKGATE_CON(2), 5, GFLAGS), 355 MUX(SCLK_MAC, "sclk_macref", mux_sclk_macref_p, CLK_SET_RATE_PARENT, 356 RK2928_CLKSEL_CON(21), 4, 1, MFLAGS), 357 GATE(0, "sclk_mac_lbtest", "sclk_macref", 0, 358 RK2928_CLKGATE_CON(2), 12, GFLAGS), 359 360 COMPOSITE(0, "hsadc_src", mux_pll_src_gpll_cpll_p, 0, 361 RK2928_CLKSEL_CON(22), 0, 1, MFLAGS, 8, 8, DFLAGS, 362 RK2928_CLKGATE_CON(2), 6, GFLAGS), 363 COMPOSITE_FRACMUX(0, "hsadc_frac", "hsadc_src", 0, 364 RK2928_CLKSEL_CON(23), 0, 365 RK2928_CLKGATE_CON(2), 7, GFLAGS, 366 &common_hsadc_out_fracmux), 367 INVERTER(SCLK_HSADC, "sclk_hsadc", "sclk_hsadc_out", 368 RK2928_CLKSEL_CON(22), 7, IFLAGS), 369 370 COMPOSITE_NOMUX(SCLK_SARADC, "sclk_saradc", "xin24m", 0, 371 RK2928_CLKSEL_CON(24), 8, 8, DFLAGS, 372 RK2928_CLKGATE_CON(2), 8, GFLAGS), 373 374 COMPOSITE_NOMUX(0, "spdif_pre", "i2s_src", 0, 375 RK2928_CLKSEL_CON(5), 0, 7, DFLAGS, 376 RK2928_CLKGATE_CON(0), 13, GFLAGS), 377 COMPOSITE_FRACMUX(0, "spdif_frac", "spdif_pre", CLK_SET_RATE_PARENT, 378 RK2928_CLKSEL_CON(9), 0, 379 RK2928_CLKGATE_CON(0), 14, GFLAGS, 380 &common_spdif_fracmux), 381 382 /* 383 * Clock-Architecture Diagram 4 384 */ 385 386 GATE(SCLK_SMC, "sclk_smc", "hclk_peri", 0, 387 RK2928_CLKGATE_CON(2), 4, GFLAGS), 388 389 COMPOSITE_NOMUX(SCLK_SPI0, "sclk_spi0", "pclk_peri", 0, 390 RK2928_CLKSEL_CON(25), 0, 7, DFLAGS, 391 RK2928_CLKGATE_CON(2), 9, GFLAGS), 392 COMPOSITE_NOMUX(SCLK_SPI1, "sclk_spi1", "pclk_peri", 0, 393 RK2928_CLKSEL_CON(25), 8, 7, DFLAGS, 394 RK2928_CLKGATE_CON(2), 10, GFLAGS), 395 396 COMPOSITE_NOMUX(SCLK_SDMMC, "sclk_sdmmc", "hclk_peri", 0, 397 RK2928_CLKSEL_CON(11), 0, 6, DFLAGS, 398 RK2928_CLKGATE_CON(2), 11, GFLAGS), 399 COMPOSITE_NOMUX(SCLK_SDIO, "sclk_sdio", "hclk_peri", 0, 400 RK2928_CLKSEL_CON(12), 0, 6, DFLAGS, 401 RK2928_CLKGATE_CON(2), 13, GFLAGS), 402 COMPOSITE_NOMUX(SCLK_EMMC, "sclk_emmc", "hclk_peri", 0, 403 RK2928_CLKSEL_CON(12), 8, 6, DFLAGS, 404 RK2928_CLKGATE_CON(2), 14, GFLAGS), 405 406 MUX(0, "uart_src", mux_pll_src_gpll_cpll_p, 0, 407 RK2928_CLKSEL_CON(12), 15, 1, MFLAGS), 408 COMPOSITE_NOMUX(0, "uart0_pre", "uart_src", 0, 409 RK2928_CLKSEL_CON(13), 0, 7, DFLAGS, 410 RK2928_CLKGATE_CON(1), 8, GFLAGS), 411 COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_pre", 0, 412 RK2928_CLKSEL_CON(17), 0, 413 RK2928_CLKGATE_CON(1), 9, GFLAGS, 414 &common_uart0_fracmux), 415 COMPOSITE_NOMUX(0, "uart1_pre", "uart_src", 0, 416 RK2928_CLKSEL_CON(14), 0, 7, DFLAGS, 417 RK2928_CLKGATE_CON(1), 10, GFLAGS), 418 COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_pre", 0, 419 RK2928_CLKSEL_CON(18), 0, 420 RK2928_CLKGATE_CON(1), 11, GFLAGS, 421 &common_uart1_fracmux), 422 COMPOSITE_NOMUX(0, "uart2_pre", "uart_src", 0, 423 RK2928_CLKSEL_CON(15), 0, 7, DFLAGS, 424 RK2928_CLKGATE_CON(1), 12, GFLAGS), 425 COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_pre", 0, 426 RK2928_CLKSEL_CON(19), 0, 427 RK2928_CLKGATE_CON(1), 13, GFLAGS, 428 &common_uart2_fracmux), 429 COMPOSITE_NOMUX(0, "uart3_pre", "uart_src", 0, 430 RK2928_CLKSEL_CON(16), 0, 7, DFLAGS, 431 RK2928_CLKGATE_CON(1), 14, GFLAGS), 432 COMPOSITE_FRACMUX(0, "uart3_frac", "uart3_pre", 0, 433 RK2928_CLKSEL_CON(20), 0, 434 RK2928_CLKGATE_CON(1), 15, GFLAGS, 435 &common_uart3_fracmux), 436 437 GATE(SCLK_JTAG, "jtag", "ext_jtag", 0, RK2928_CLKGATE_CON(1), 3, GFLAGS), 438 439 GATE(SCLK_TIMER0, "timer0", "xin24m", 0, RK2928_CLKGATE_CON(1), 0, GFLAGS), 440 GATE(SCLK_TIMER1, "timer1", "xin24m", 0, RK2928_CLKGATE_CON(1), 1, GFLAGS), 441 442 /* clk_core_pre gates */ 443 GATE(0, "core_dbg", "armclk", 0, RK2928_CLKGATE_CON(9), 0, GFLAGS), 444 445 /* aclk_cpu gates */ 446 GATE(ACLK_DMA1, "aclk_dma1", "aclk_cpu", 0, RK2928_CLKGATE_CON(5), 0, GFLAGS), 447 GATE(0, "aclk_intmem", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 12, GFLAGS), 448 GATE(0, "aclk_strc_sys", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 10, GFLAGS), 449 450 /* hclk_cpu gates */ 451 GATE(HCLK_ROM, "hclk_rom", "hclk_cpu", 0, RK2928_CLKGATE_CON(5), 6, GFLAGS), 452 GATE(HCLK_I2S0, "hclk_i2s0", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 2, GFLAGS), 453 GATE(HCLK_SPDIF, "hclk_spdif", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 1, GFLAGS), 454 GATE(0, "hclk_cpubus", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 8, GFLAGS), 455 /* hclk_ahb2apb is part of a clk branch */ 456 GATE(0, "hclk_vio_bus", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 12, GFLAGS), 457 GATE(HCLK_LCDC0, "hclk_lcdc0", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 1, GFLAGS), 458 GATE(HCLK_LCDC1, "hclk_lcdc1", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 2, GFLAGS), 459 GATE(HCLK_CIF0, "hclk_cif0", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 4, GFLAGS), 460 GATE(HCLK_IPP, "hclk_ipp", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 9, GFLAGS), 461 GATE(HCLK_RGA, "hclk_rga", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 10, GFLAGS), 462 463 /* hclk_peri gates */ 464 GATE(0, "hclk_peri_axi_matrix", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 0, GFLAGS), 465 GATE(0, "hclk_peri_ahb_arbi", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 6, GFLAGS), 466 GATE(0, "hclk_emem_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 7, GFLAGS), 467 GATE(HCLK_EMAC, "hclk_emac", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 0, GFLAGS), 468 GATE(HCLK_NANDC0, "hclk_nandc0", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 9, GFLAGS), 469 GATE(0, "hclk_usb_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 5, GFLAGS), 470 GATE(HCLK_OTG0, "hclk_usbotg0", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 13, GFLAGS), 471 GATE(HCLK_HSADC, "hclk_hsadc", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 5, GFLAGS), 472 GATE(HCLK_PIDF, "hclk_pidfilter", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 6, GFLAGS), 473 GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 10, GFLAGS), 474 GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 11, GFLAGS), 475 GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 12, GFLAGS), 476 477 /* aclk_lcdc0_pre gates */ 478 GATE(0, "aclk_vio0", "aclk_lcdc0_pre", 0, RK2928_CLKGATE_CON(6), 13, GFLAGS), 479 GATE(ACLK_LCDC0, "aclk_lcdc0", "aclk_vio0", 0, RK2928_CLKGATE_CON(6), 0, GFLAGS), 480 GATE(ACLK_CIF0, "aclk_cif0", "aclk_vio0", 0, RK2928_CLKGATE_CON(6), 5, GFLAGS), 481 GATE(ACLK_IPP, "aclk_ipp", "aclk_vio0", 0, RK2928_CLKGATE_CON(6), 8, GFLAGS), 482 483 /* aclk_lcdc1_pre gates */ 484 GATE(0, "aclk_vio1", "aclk_lcdc1_pre", 0, RK2928_CLKGATE_CON(9), 5, GFLAGS), 485 GATE(ACLK_LCDC1, "aclk_lcdc1", "aclk_vio1", 0, RK2928_CLKGATE_CON(6), 3, GFLAGS), 486 GATE(ACLK_RGA, "aclk_rga", "aclk_vio1", 0, RK2928_CLKGATE_CON(6), 11, GFLAGS), 487 488 /* atclk_cpu gates */ 489 GATE(0, "atclk", "atclk_cpu", 0, RK2928_CLKGATE_CON(9), 3, GFLAGS), 490 GATE(0, "trace", "atclk_cpu", 0, RK2928_CLKGATE_CON(9), 2, GFLAGS), 491 492 /* pclk_cpu gates */ 493 GATE(PCLK_PWM01, "pclk_pwm01", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 10, GFLAGS), 494 GATE(PCLK_TIMER0, "pclk_timer0", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 7, GFLAGS), 495 GATE(PCLK_I2C0, "pclk_i2c0", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 4, GFLAGS), 496 GATE(PCLK_I2C1, "pclk_i2c1", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 5, GFLAGS), 497 GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 9, GFLAGS), 498 GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 10, GFLAGS), 499 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 11, GFLAGS), 500 GATE(PCLK_EFUSE, "pclk_efuse", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 2, GFLAGS), 501 GATE(PCLK_TZPC, "pclk_tzpc", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 3, GFLAGS), 502 GATE(PCLK_DDRUPCTL, "pclk_ddrupctl", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 7, GFLAGS), 503 GATE(PCLK_PUBL, "pclk_ddrpubl", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 6, GFLAGS), 504 GATE(0, "pclk_dbg", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 1, GFLAGS), 505 GATE(PCLK_GRF, "pclk_grf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 4, GFLAGS), 506 GATE(PCLK_PMU, "pclk_pmu", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 5, GFLAGS), 507 508 /* aclk_peri */ 509 GATE(ACLK_DMA2, "aclk_dma2", "aclk_peri", 0, RK2928_CLKGATE_CON(5), 1, GFLAGS), 510 GATE(ACLK_SMC, "aclk_smc", "aclk_peri", 0, RK2928_CLKGATE_CON(5), 8, GFLAGS), 511 GATE(0, "aclk_peri_niu", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 4, GFLAGS), 512 GATE(0, "aclk_cpu_peri", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 2, GFLAGS), 513 GATE(0, "aclk_peri_axi_matrix", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 3, GFLAGS), 514 515 /* pclk_peri gates */ 516 GATE(0, "pclk_peri_axi_matrix", "pclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 1, GFLAGS), 517 GATE(PCLK_PWM23, "pclk_pwm23", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 11, GFLAGS), 518 GATE(PCLK_WDT, "pclk_wdt", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 15, GFLAGS), 519 GATE(PCLK_SPI0, "pclk_spi0", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 12, GFLAGS), 520 GATE(PCLK_SPI1, "pclk_spi1", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 13, GFLAGS), 521 GATE(PCLK_UART2, "pclk_uart2", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 2, GFLAGS), 522 GATE(PCLK_UART3, "pclk_uart3", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 3, GFLAGS), 523 GATE(PCLK_I2C2, "pclk_i2c2", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 6, GFLAGS), 524 GATE(PCLK_I2C3, "pclk_i2c3", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 7, GFLAGS), 525 GATE(PCLK_I2C4, "pclk_i2c4", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 8, GFLAGS), 526 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 12, GFLAGS), 527 GATE(PCLK_SARADC, "pclk_saradc", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 14, GFLAGS), 528}; 529 530PNAME(mux_rk3066_lcdc0_p) = { "dclk_lcdc0_src", "xin27m" }; 531PNAME(mux_rk3066_lcdc1_p) = { "dclk_lcdc1_src", "xin27m" }; 532PNAME(mux_sclk_cif1_p) = { "cif1_pre", "xin24m" }; 533PNAME(mux_sclk_i2s1_p) = { "i2s1_pre", "i2s1_frac", "xin12m" }; 534PNAME(mux_sclk_i2s2_p) = { "i2s2_pre", "i2s2_frac", "xin12m" }; 535 536static struct clk_div_table div_aclk_cpu_t[] = { 537 { .val = 0, .div = 1 }, 538 { .val = 1, .div = 2 }, 539 { .val = 2, .div = 3 }, 540 { .val = 3, .div = 4 }, 541 { .val = 4, .div = 8 }, 542 { /* sentinel */ }, 543}; 544 545static struct rockchip_clk_branch rk3066a_i2s0_fracmux __initdata = 546 MUX(SCLK_I2S0, "sclk_i2s0", mux_sclk_i2s0_p, 0, 547 RK2928_CLKSEL_CON(2), 8, 2, MFLAGS); 548 549static struct rockchip_clk_branch rk3066a_i2s1_fracmux __initdata = 550 MUX(SCLK_I2S1, "sclk_i2s1", mux_sclk_i2s1_p, 0, 551 RK2928_CLKSEL_CON(3), 8, 2, MFLAGS); 552 553static struct rockchip_clk_branch rk3066a_i2s2_fracmux __initdata = 554 MUX(SCLK_I2S2, "sclk_i2s2", mux_sclk_i2s2_p, 0, 555 RK2928_CLKSEL_CON(4), 8, 2, MFLAGS); 556 557static struct rockchip_clk_branch rk3066a_clk_branches[] __initdata = { 558 DIVTBL(0, "aclk_cpu_pre", "armclk", 0, 559 RK2928_CLKSEL_CON(1), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY, div_aclk_cpu_t), 560 DIV(0, "pclk_cpu_pre", "aclk_cpu_pre", 0, 561 RK2928_CLKSEL_CON(1), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO 562 | CLK_DIVIDER_READ_ONLY), 563 DIV(0, "hclk_cpu_pre", "aclk_cpu_pre", 0, 564 RK2928_CLKSEL_CON(1), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO 565 | CLK_DIVIDER_READ_ONLY), 566 COMPOSITE_NOMUX(0, "hclk_ahb2apb", "hclk_cpu_pre", 0, 567 RK2928_CLKSEL_CON(1), 14, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO 568 | CLK_DIVIDER_READ_ONLY, 569 RK2928_CLKGATE_CON(4), 9, GFLAGS), 570 571 GATE(CORE_L2C, "core_l2c", "aclk_cpu", CLK_IGNORE_UNUSED, 572 RK2928_CLKGATE_CON(9), 4, GFLAGS), 573 574 COMPOSITE(0, "aclk_peri_pre", mux_pll_src_gpll_cpll_p, 0, 575 RK2928_CLKSEL_CON(10), 15, 1, MFLAGS, 0, 5, DFLAGS, 576 RK2928_CLKGATE_CON(2), 0, GFLAGS), 577 578 COMPOSITE(0, "dclk_lcdc0_src", mux_pll_src_cpll_gpll_p, 0, 579 RK2928_CLKSEL_CON(27), 0, 1, MFLAGS, 8, 8, DFLAGS, 580 RK2928_CLKGATE_CON(3), 1, GFLAGS), 581 MUX(DCLK_LCDC0, "dclk_lcdc0", mux_rk3066_lcdc0_p, CLK_SET_RATE_PARENT, 582 RK2928_CLKSEL_CON(27), 4, 1, MFLAGS), 583 COMPOSITE(0, "dclk_lcdc1_src", mux_pll_src_cpll_gpll_p, 0, 584 RK2928_CLKSEL_CON(28), 0, 1, MFLAGS, 8, 8, DFLAGS, 585 RK2928_CLKGATE_CON(3), 2, GFLAGS), 586 MUX(DCLK_LCDC1, "dclk_lcdc1", mux_rk3066_lcdc1_p, CLK_SET_RATE_PARENT, 587 RK2928_CLKSEL_CON(28), 4, 1, MFLAGS), 588 589 COMPOSITE_NOMUX(0, "cif1_pre", "cif_src", 0, 590 RK2928_CLKSEL_CON(29), 8, 5, DFLAGS, 591 RK2928_CLKGATE_CON(3), 8, GFLAGS), 592 MUX(SCLK_CIF1, "sclk_cif1", mux_sclk_cif1_p, 0, 593 RK2928_CLKSEL_CON(29), 15, 1, MFLAGS), 594 595 GATE(0, "pclkin_cif1", "ext_cif1", 0, 596 RK2928_CLKGATE_CON(3), 4, GFLAGS), 597 INVERTER(0, "pclk_cif1", "pclkin_cif1", 598 RK2928_CLKSEL_CON(30), 12, IFLAGS), 599 600 COMPOSITE(0, "aclk_gpu_src", mux_pll_src_cpll_gpll_p, 0, 601 RK2928_CLKSEL_CON(33), 8, 1, MFLAGS, 0, 5, DFLAGS, 602 RK2928_CLKGATE_CON(3), 13, GFLAGS), 603 GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_src", 0, 604 RK2928_CLKGATE_CON(5), 15, GFLAGS), 605 606 GATE(SCLK_TIMER2, "timer2", "xin24m", 0, 607 RK2928_CLKGATE_CON(3), 2, GFLAGS), 608 609 COMPOSITE_NOMUX(SCLK_TSADC, "sclk_tsadc", "xin24m", 0, 610 RK2928_CLKSEL_CON(34), 0, 16, DFLAGS, 611 RK2928_CLKGATE_CON(2), 15, GFLAGS), 612 613 MUX(0, "i2s_src", mux_pll_src_gpll_cpll_p, 0, 614 RK2928_CLKSEL_CON(2), 15, 1, MFLAGS), 615 COMPOSITE_NOMUX(0, "i2s0_pre", "i2s_src", 0, 616 RK2928_CLKSEL_CON(2), 0, 7, DFLAGS, 617 RK2928_CLKGATE_CON(0), 7, GFLAGS), 618 COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_pre", 0, 619 RK2928_CLKSEL_CON(6), 0, 620 RK2928_CLKGATE_CON(0), 8, GFLAGS, 621 &rk3066a_i2s0_fracmux), 622 COMPOSITE_NOMUX(0, "i2s1_pre", "i2s_src", 0, 623 RK2928_CLKSEL_CON(3), 0, 7, DFLAGS, 624 RK2928_CLKGATE_CON(0), 9, GFLAGS), 625 COMPOSITE_FRACMUX(0, "i2s1_frac", "i2s1_pre", 0, 626 RK2928_CLKSEL_CON(7), 0, 627 RK2928_CLKGATE_CON(0), 10, GFLAGS, 628 &rk3066a_i2s1_fracmux), 629 COMPOSITE_NOMUX(0, "i2s2_pre", "i2s_src", 0, 630 RK2928_CLKSEL_CON(4), 0, 7, DFLAGS, 631 RK2928_CLKGATE_CON(0), 11, GFLAGS), 632 COMPOSITE_FRACMUX(0, "i2s2_frac", "i2s2_pre", 0, 633 RK2928_CLKSEL_CON(8), 0, 634 RK2928_CLKGATE_CON(0), 12, GFLAGS, 635 &rk3066a_i2s2_fracmux), 636 637 GATE(HCLK_I2S1, "hclk_i2s1", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 3, GFLAGS), 638 GATE(HCLK_I2S2, "hclk_i2s2", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 4, GFLAGS), 639 GATE(HCLK_CIF1, "hclk_cif1", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 6, GFLAGS), 640 GATE(HCLK_HDMI, "hclk_hdmi", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 14, GFLAGS), 641 642 GATE(HCLK_OTG1, "hclk_usbotg1", "hclk_peri", CLK_IGNORE_UNUSED, 643 RK2928_CLKGATE_CON(5), 14, GFLAGS), 644 645 GATE(ACLK_CIF1, "aclk_cif1", "aclk_vio1", 0, RK2928_CLKGATE_CON(6), 7, GFLAGS), 646 647 GATE(PCLK_TIMER1, "pclk_timer1", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 8, GFLAGS), 648 GATE(PCLK_TIMER2, "pclk_timer2", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 9, GFLAGS), 649 GATE(PCLK_GPIO6, "pclk_gpio6", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 15, GFLAGS), 650 GATE(PCLK_UART0, "pclk_uart0", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 0, GFLAGS), 651 GATE(PCLK_UART1, "pclk_uart1", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 1, GFLAGS), 652 653 GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 13, GFLAGS), 654 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_peri", 0, RK2928_CLKGATE_CON(4), 13, GFLAGS), 655}; 656 657static struct clk_div_table div_rk3188_aclk_core_t[] = { 658 { .val = 0, .div = 1 }, 659 { .val = 1, .div = 2 }, 660 { .val = 2, .div = 3 }, 661 { .val = 3, .div = 4 }, 662 { .val = 4, .div = 8 }, 663 { /* sentinel */ }, 664}; 665 666PNAME(mux_hsicphy_p) = { "sclk_otgphy0_480m", "sclk_otgphy1_480m", 667 "gpll", "cpll" }; 668 669static struct rockchip_clk_branch rk3188_i2s0_fracmux __initdata = 670 MUX(SCLK_I2S0, "sclk_i2s0", mux_sclk_i2s0_p, CLK_SET_RATE_PARENT, 671 RK2928_CLKSEL_CON(3), 8, 2, MFLAGS); 672 673static struct rockchip_clk_branch rk3188_clk_branches[] __initdata = { 674 COMPOSITE_NOMUX_DIVTBL(0, "aclk_core", "armclk", CLK_IGNORE_UNUSED, 675 RK2928_CLKSEL_CON(1), 3, 3, DFLAGS | CLK_DIVIDER_READ_ONLY, 676 div_rk3188_aclk_core_t, RK2928_CLKGATE_CON(0), 7, GFLAGS), 677 678 /* do not source aclk_cpu_pre from the apll, to keep complexity down */ 679 COMPOSITE_NOGATE(0, "aclk_cpu_pre", mux_aclk_cpu_p, CLK_SET_RATE_NO_REPARENT, 680 RK2928_CLKSEL_CON(0), 5, 1, MFLAGS, 0, 5, DFLAGS), 681 DIV(0, "pclk_cpu_pre", "aclk_cpu_pre", 0, 682 RK2928_CLKSEL_CON(1), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO), 683 DIV(0, "hclk_cpu_pre", "aclk_cpu_pre", 0, 684 RK2928_CLKSEL_CON(1), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO), 685 COMPOSITE_NOMUX(0, "hclk_ahb2apb", "hclk_cpu_pre", 0, 686 RK2928_CLKSEL_CON(1), 14, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO, 687 RK2928_CLKGATE_CON(4), 9, GFLAGS), 688 689 GATE(CORE_L2C, "core_l2c", "armclk", CLK_IGNORE_UNUSED, 690 RK2928_CLKGATE_CON(9), 4, GFLAGS), 691 692 COMPOSITE(0, "aclk_peri_pre", mux_pll_src_cpll_gpll_p, 0, 693 RK2928_CLKSEL_CON(10), 15, 1, MFLAGS, 0, 5, DFLAGS, 694 RK2928_CLKGATE_CON(2), 0, GFLAGS), 695 696 COMPOSITE(DCLK_LCDC0, "dclk_lcdc0", mux_pll_src_cpll_gpll_p, 0, 697 RK2928_CLKSEL_CON(27), 0, 1, MFLAGS, 8, 8, DFLAGS, 698 RK2928_CLKGATE_CON(3), 1, GFLAGS), 699 COMPOSITE(DCLK_LCDC1, "dclk_lcdc1", mux_pll_src_cpll_gpll_p, 0, 700 RK2928_CLKSEL_CON(28), 0, 1, MFLAGS, 8, 8, DFLAGS, 701 RK2928_CLKGATE_CON(3), 2, GFLAGS), 702 703 COMPOSITE(0, "aclk_gpu_src", mux_pll_src_cpll_gpll_p, 0, 704 RK2928_CLKSEL_CON(34), 7, 1, MFLAGS, 0, 5, DFLAGS, 705 RK2928_CLKGATE_CON(3), 15, GFLAGS), 706 GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_src", 0, 707 RK2928_CLKGATE_CON(9), 7, GFLAGS), 708 709 GATE(SCLK_TIMER2, "timer2", "xin24m", 0, RK2928_CLKGATE_CON(3), 4, GFLAGS), 710 GATE(SCLK_TIMER3, "timer3", "xin24m", 0, RK2928_CLKGATE_CON(1), 2, GFLAGS), 711 GATE(SCLK_TIMER4, "timer4", "xin24m", 0, RK2928_CLKGATE_CON(3), 5, GFLAGS), 712 GATE(SCLK_TIMER5, "timer5", "xin24m", 0, RK2928_CLKGATE_CON(3), 8, GFLAGS), 713 GATE(SCLK_TIMER6, "timer6", "xin24m", 0, RK2928_CLKGATE_CON(3), 14, GFLAGS), 714 715 COMPOSITE_NODIV(0, "sclk_hsicphy_480m", mux_hsicphy_p, 0, 716 RK2928_CLKSEL_CON(30), 0, 2, DFLAGS, 717 RK2928_CLKGATE_CON(3), 6, GFLAGS), 718 DIV(0, "sclk_hsicphy_12m", "sclk_hsicphy_480m", 0, 719 RK2928_CLKSEL_CON(11), 8, 6, DFLAGS), 720 721 MUX(0, "i2s_src", mux_pll_src_gpll_cpll_p, 0, 722 RK2928_CLKSEL_CON(2), 15, 1, MFLAGS), 723 COMPOSITE_NOMUX(0, "i2s0_pre", "i2s_src", 0, 724 RK2928_CLKSEL_CON(3), 0, 7, DFLAGS, 725 RK2928_CLKGATE_CON(0), 9, GFLAGS), 726 COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_pre", CLK_SET_RATE_PARENT, 727 RK2928_CLKSEL_CON(7), 0, 728 RK2928_CLKGATE_CON(0), 10, GFLAGS, 729 &rk3188_i2s0_fracmux), 730 731 GATE(0, "hclk_imem0", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 14, GFLAGS), 732 GATE(0, "hclk_imem1", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 15, GFLAGS), 733 734 GATE(HCLK_OTG1, "hclk_usbotg1", "hclk_peri", CLK_IGNORE_UNUSED, 735 RK2928_CLKGATE_CON(7), 3, GFLAGS), 736 GATE(HCLK_HSIC, "hclk_hsic", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 4, GFLAGS), 737 738 GATE(PCLK_TIMER3, "pclk_timer3", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 9, GFLAGS), 739 740 GATE(PCLK_UART0, "pclk_uart0", "hclk_ahb2apb", 0, RK2928_CLKGATE_CON(8), 0, GFLAGS), 741 GATE(PCLK_UART1, "pclk_uart1", "hclk_ahb2apb", 0, RK2928_CLKGATE_CON(8), 1, GFLAGS), 742 743 GATE(ACLK_GPS, "aclk_gps", "aclk_peri", 0, RK2928_CLKGATE_CON(8), 13, GFLAGS), 744}; 745 746static const char *const rk3188_critical_clocks[] __initconst = { 747 "aclk_cpu", 748 "aclk_peri", 749 "hclk_peri", 750 "pclk_cpu", 751 "pclk_peri", 752 "hclk_cpubus", 753 "hclk_vio_bus", 754 "sclk_mac_lbtest", 755}; 756 757static struct rockchip_clk_provider *__init rk3188_common_clk_init(struct device_node *np) 758{ 759 struct rockchip_clk_provider *ctx; 760 void __iomem *reg_base; 761 762 reg_base = of_iomap(np, 0); 763 if (!reg_base) { 764 pr_err("%s: could not map cru region\n", __func__); 765 return ERR_PTR(-ENOMEM); 766 } 767 768 ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS); 769 if (IS_ERR(ctx)) { 770 pr_err("%s: rockchip clk init failed\n", __func__); 771 iounmap(reg_base); 772 return ERR_PTR(-ENOMEM); 773 } 774 775 rockchip_clk_register_branches(ctx, common_clk_branches, 776 ARRAY_SIZE(common_clk_branches)); 777 778 rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0), 779 ROCKCHIP_SOFTRST_HIWORD_MASK); 780 781 rockchip_register_restart_notifier(ctx, RK2928_GLB_SRST_FST, NULL); 782 783 return ctx; 784} 785 786static void __init rk3066a_clk_init(struct device_node *np) 787{ 788 struct rockchip_clk_provider *ctx; 789 790 ctx = rk3188_common_clk_init(np); 791 if (IS_ERR(ctx)) 792 return; 793 794 rockchip_clk_register_plls(ctx, rk3066_pll_clks, 795 ARRAY_SIZE(rk3066_pll_clks), 796 RK3066_GRF_SOC_STATUS); 797 rockchip_clk_register_branches(ctx, rk3066a_clk_branches, 798 ARRAY_SIZE(rk3066a_clk_branches)); 799 rockchip_clk_register_armclk(ctx, ARMCLK, "armclk", 800 mux_armclk_p, ARRAY_SIZE(mux_armclk_p), 801 &rk3066_cpuclk_data, rk3066_cpuclk_rates, 802 ARRAY_SIZE(rk3066_cpuclk_rates)); 803 rockchip_clk_protect_critical(rk3188_critical_clocks, 804 ARRAY_SIZE(rk3188_critical_clocks)); 805 rockchip_clk_of_add_provider(np, ctx); 806} 807CLK_OF_DECLARE(rk3066a_cru, "rockchip,rk3066a-cru", rk3066a_clk_init); 808 809static void __init rk3188a_clk_init(struct device_node *np) 810{ 811 struct rockchip_clk_provider *ctx; 812 struct clk *clk1, *clk2; 813 unsigned long rate; 814 int ret; 815 816 ctx = rk3188_common_clk_init(np); 817 if (IS_ERR(ctx)) 818 return; 819 820 rockchip_clk_register_plls(ctx, rk3188_pll_clks, 821 ARRAY_SIZE(rk3188_pll_clks), 822 RK3188_GRF_SOC_STATUS); 823 rockchip_clk_register_branches(ctx, rk3188_clk_branches, 824 ARRAY_SIZE(rk3188_clk_branches)); 825 rockchip_clk_register_armclk(ctx, ARMCLK, "armclk", 826 mux_armclk_p, ARRAY_SIZE(mux_armclk_p), 827 &rk3188_cpuclk_data, rk3188_cpuclk_rates, 828 ARRAY_SIZE(rk3188_cpuclk_rates)); 829 830 /* reparent aclk_cpu_pre from apll */ 831 clk1 = __clk_lookup("aclk_cpu_pre"); 832 clk2 = __clk_lookup("gpll"); 833 if (clk1 && clk2) { 834 rate = clk_get_rate(clk1); 835 836 ret = clk_set_parent(clk1, clk2); 837 if (ret < 0) 838 pr_warn("%s: could not reparent aclk_cpu_pre to gpll\n", 839 __func__); 840 841 clk_set_rate(clk1, rate); 842 } else { 843 pr_warn("%s: missing clocks to reparent aclk_cpu_pre to gpll\n", 844 __func__); 845 } 846 847 rockchip_clk_protect_critical(rk3188_critical_clocks, 848 ARRAY_SIZE(rk3188_critical_clocks)); 849 rockchip_clk_of_add_provider(np, ctx); 850} 851CLK_OF_DECLARE(rk3188a_cru, "rockchip,rk3188a-cru", rk3188a_clk_init); 852 853static void __init rk3188_clk_init(struct device_node *np) 854{ 855 int i; 856 857 for (i = 0; i < ARRAY_SIZE(rk3188_pll_clks); i++) { 858 struct rockchip_pll_clock *pll = &rk3188_pll_clks[i]; 859 struct rockchip_pll_rate_table *rate; 860 861 if (!pll->rate_table) 862 continue; 863 864 rate = pll->rate_table; 865 while (rate->rate > 0) { 866 rate->nb = 1; 867 rate++; 868 } 869 } 870 871 rk3188a_clk_init(np); 872} 873CLK_OF_DECLARE(rk3188_cru, "rockchip,rk3188-cru", rk3188_clk_init); 874