1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * Copyright (c) 2014 MundoReader S.L. 4 * Author: Heiko Stuebner <heiko@sntech.de> 5 * 6 * Copyright (c) 2015 Rockchip Electronics Co. Ltd. 7 * Author: Xing Zheng <zhengxing@rock-chips.com> 8 */ 9 10#include <linux/clk-provider.h> 11#include <linux/io.h> 12#include <linux/of.h> 13#include <linux/of_address.h> 14#include <linux/syscore_ops.h> 15#include <dt-bindings/clock/rk3036-cru.h> 16#include "clk.h" 17 18#define RK3036_GRF_SOC_STATUS0 0x14c 19 20enum rk3036_plls { 21 apll, dpll, gpll, 22}; 23 24static struct rockchip_pll_rate_table rk3036_pll_rates[] = { 25 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ 26 RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0), 27 RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0), 28 RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0), 29 RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0), 30 RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0), 31 RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0), 32 RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0), 33 RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0), 34 RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0), 35 RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0), 36 RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0), 37 RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0), 38 RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0), 39 RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0), 40 RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0), 41 RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0), 42 RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0), 43 RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0), 44 RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0), 45 RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0), 46 RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0), 47 RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0), 48 RK3036_PLL_RATE( 984000000, 1, 82, 2, 1, 1, 0), 49 RK3036_PLL_RATE( 960000000, 1, 80, 2, 1, 1, 0), 50 RK3036_PLL_RATE( 936000000, 1, 78, 2, 1, 1, 0), 51 RK3036_PLL_RATE( 912000000, 1, 76, 2, 1, 1, 0), 52 RK3036_PLL_RATE( 900000000, 4, 300, 2, 1, 1, 0), 53 RK3036_PLL_RATE( 888000000, 1, 74, 2, 1, 1, 0), 54 RK3036_PLL_RATE( 864000000, 1, 72, 2, 1, 1, 0), 55 RK3036_PLL_RATE( 840000000, 1, 70, 2, 1, 1, 0), 56 RK3036_PLL_RATE( 816000000, 1, 68, 2, 1, 1, 0), 57 RK3036_PLL_RATE( 800000000, 6, 400, 2, 1, 1, 0), 58 RK3036_PLL_RATE( 700000000, 6, 350, 2, 1, 1, 0), 59 RK3036_PLL_RATE( 696000000, 1, 58, 2, 1, 1, 0), 60 RK3036_PLL_RATE( 600000000, 1, 75, 3, 1, 1, 0), 61 RK3036_PLL_RATE( 594000000, 2, 99, 2, 1, 1, 0), 62 RK3036_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0), 63 RK3036_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0), 64 RK3036_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0), 65 RK3036_PLL_RATE( 312000000, 1, 52, 2, 2, 1, 0), 66 RK3036_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0), 67 RK3036_PLL_RATE( 96000000, 1, 64, 4, 4, 1, 0), 68 { /* sentinel */ }, 69}; 70 71#define RK3036_DIV_CPU_MASK 0x1f 72#define RK3036_DIV_CPU_SHIFT 8 73 74#define RK3036_DIV_PERI_MASK 0xf 75#define RK3036_DIV_PERI_SHIFT 0 76#define RK3036_DIV_ACLK_MASK 0x7 77#define RK3036_DIV_ACLK_SHIFT 4 78#define RK3036_DIV_HCLK_MASK 0x3 79#define RK3036_DIV_HCLK_SHIFT 8 80#define RK3036_DIV_PCLK_MASK 0x7 81#define RK3036_DIV_PCLK_SHIFT 12 82 83#define RK3036_CLKSEL1(_core_periph_div) \ 84 { \ 85 .reg = RK2928_CLKSEL_CON(1), \ 86 .val = HIWORD_UPDATE(_core_periph_div, RK3036_DIV_PERI_MASK, \ 87 RK3036_DIV_PERI_SHIFT) \ 88 } 89 90#define RK3036_CPUCLK_RATE(_prate, _core_periph_div) \ 91 { \ 92 .prate = _prate, \ 93 .divs = { \ 94 RK3036_CLKSEL1(_core_periph_div), \ 95 }, \ 96 } 97 98static struct rockchip_cpuclk_rate_table rk3036_cpuclk_rates[] __initdata = { 99 RK3036_CPUCLK_RATE(816000000, 4), 100 RK3036_CPUCLK_RATE(600000000, 4), 101 RK3036_CPUCLK_RATE(312000000, 4), 102}; 103 104static const struct rockchip_cpuclk_reg_data rk3036_cpuclk_data = { 105 .core_reg = RK2928_CLKSEL_CON(0), 106 .div_core_shift = 0, 107 .div_core_mask = 0x1f, 108 .mux_core_alt = 1, 109 .mux_core_main = 0, 110 .mux_core_shift = 7, 111 .mux_core_mask = 0x1, 112}; 113 114PNAME(mux_pll_p) = { "xin24m", "xin24m" }; 115 116PNAME(mux_armclk_p) = { "apll", "gpll_armclk" }; 117PNAME(mux_busclk_p) = { "apll", "dpll_cpu", "gpll_cpu" }; 118PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr" }; 119PNAME(mux_pll_src_3plls_p) = { "apll", "dpll", "gpll" }; 120PNAME(mux_timer_p) = { "xin24m", "pclk_peri_src" }; 121 122PNAME(mux_pll_src_apll_dpll_gpll_usb480m_p) = { "apll", "dpll", "gpll", "usb480m" }; 123 124PNAME(mux_mmc_src_p) = { "apll", "dpll", "gpll", "xin24m" }; 125PNAME(mux_i2s_pre_p) = { "i2s_src", "i2s_frac", "ext_i2s", "xin12m" }; 126PNAME(mux_i2s_clkout_p) = { "i2s_pre", "xin12m" }; 127PNAME(mux_spdif_p) = { "spdif_src", "spdif_frac", "xin12m" }; 128PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" }; 129PNAME(mux_uart1_p) = { "uart1_src", "uart1_frac", "xin24m" }; 130PNAME(mux_uart2_p) = { "uart2_src", "uart2_frac", "xin24m" }; 131PNAME(mux_mac_p) = { "mac_pll_src", "rmii_clkin" }; 132PNAME(mux_dclk_p) = { "dclk_lcdc", "dclk_cru" }; 133 134static struct rockchip_pll_clock rk3036_pll_clks[] __initdata = { 135 [apll] = PLL(pll_rk3036, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0), 136 RK2928_MODE_CON, 0, 5, 0, rk3036_pll_rates), 137 [dpll] = PLL(pll_rk3036, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4), 138 RK2928_MODE_CON, 4, 4, 0, NULL), 139 [gpll] = PLL(pll_rk3036, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(12), 140 RK2928_MODE_CON, 12, 6, ROCKCHIP_PLL_SYNC_RATE, rk3036_pll_rates), 141}; 142 143#define MFLAGS CLK_MUX_HIWORD_MASK 144#define DFLAGS CLK_DIVIDER_HIWORD_MASK 145#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE) 146 147static struct rockchip_clk_branch rk3036_uart0_fracmux __initdata = 148 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT, 149 RK2928_CLKSEL_CON(13), 8, 2, MFLAGS); 150 151static struct rockchip_clk_branch rk3036_uart1_fracmux __initdata = 152 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT, 153 RK2928_CLKSEL_CON(14), 8, 2, MFLAGS); 154 155static struct rockchip_clk_branch rk3036_uart2_fracmux __initdata = 156 MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT, 157 RK2928_CLKSEL_CON(15), 8, 2, MFLAGS); 158 159static struct rockchip_clk_branch rk3036_i2s_fracmux __initdata = 160 MUX(0, "i2s_pre", mux_i2s_pre_p, CLK_SET_RATE_PARENT, 161 RK2928_CLKSEL_CON(3), 8, 2, MFLAGS); 162 163static struct rockchip_clk_branch rk3036_spdif_fracmux __initdata = 164 MUX(SCLK_SPDIF, "sclk_spdif", mux_spdif_p, 0, 165 RK2928_CLKSEL_CON(5), 8, 2, MFLAGS); 166 167static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = { 168 /* 169 * Clock-Architecture Diagram 1 170 */ 171 172 GATE(0, "gpll_armclk", "gpll", CLK_IGNORE_UNUSED, 173 RK2928_CLKGATE_CON(0), 6, GFLAGS), 174 175 FACTOR(0, "xin12m", "xin24m", 0, 1, 2), 176 177 /* 178 * Clock-Architecture Diagram 2 179 */ 180 181 GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED, 182 RK2928_CLKGATE_CON(0), 2, GFLAGS), 183 GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED, 184 RK2928_CLKGATE_CON(0), 8, GFLAGS), 185 COMPOSITE_NOGATE(0, "ddrphy2x", mux_ddrphy_p, CLK_IGNORE_UNUSED, 186 RK2928_CLKSEL_CON(26), 8, 1, MFLAGS, 0, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO), 187 FACTOR(0, "ddrphy", "ddrphy2x", 0, 1, 2), 188 189 COMPOSITE_NOMUX(0, "pclk_dbg", "armclk", CLK_IGNORE_UNUSED, 190 RK2928_CLKSEL_CON(1), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY, 191 RK2928_CLKGATE_CON(0), 7, GFLAGS), 192 COMPOSITE_NOMUX(0, "aclk_core_pre", "armclk", CLK_IGNORE_UNUSED, 193 RK2928_CLKSEL_CON(1), 4, 3, DFLAGS | CLK_DIVIDER_READ_ONLY, 194 RK2928_CLKGATE_CON(0), 7, GFLAGS), 195 196 GATE(0, "dpll_cpu", "dpll", 0, RK2928_CLKGATE_CON(10), 8, GFLAGS), 197 GATE(0, "gpll_cpu", "gpll", 0, RK2928_CLKGATE_CON(0), 1, GFLAGS), 198 COMPOSITE_NOGATE(0, "aclk_cpu_src", mux_busclk_p, 0, 199 RK2928_CLKSEL_CON(0), 14, 2, MFLAGS, 8, 5, DFLAGS), 200 GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_src", CLK_IGNORE_UNUSED, 201 RK2928_CLKGATE_CON(0), 3, GFLAGS), 202 COMPOSITE_NOMUX(PCLK_CPU, "pclk_cpu", "aclk_cpu_src", CLK_IGNORE_UNUSED, 203 RK2928_CLKSEL_CON(1), 12, 3, DFLAGS | CLK_DIVIDER_READ_ONLY, 204 RK2928_CLKGATE_CON(0), 5, GFLAGS), 205 COMPOSITE_NOMUX(HCLK_CPU, "hclk_cpu", "aclk_cpu_src", CLK_IGNORE_UNUSED, 206 RK2928_CLKSEL_CON(1), 8, 2, DFLAGS | CLK_DIVIDER_READ_ONLY, 207 RK2928_CLKGATE_CON(0), 4, GFLAGS), 208 209 COMPOSITE(0, "aclk_peri_src", mux_pll_src_3plls_p, 0, 210 RK2928_CLKSEL_CON(10), 14, 2, MFLAGS, 0, 5, DFLAGS, 211 RK2928_CLKGATE_CON(2), 0, GFLAGS), 212 213 GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", 0, 214 RK2928_CLKGATE_CON(2), 1, GFLAGS), 215 DIV(0, "pclk_peri_src", "aclk_peri_src", CLK_IGNORE_UNUSED, 216 RK2928_CLKSEL_CON(10), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO), 217 GATE(PCLK_PERI, "pclk_peri", "pclk_peri_src", 0, 218 RK2928_CLKGATE_CON(2), 3, GFLAGS), 219 DIV(0, "hclk_peri_src", "aclk_peri_src", CLK_IGNORE_UNUSED, 220 RK2928_CLKSEL_CON(10), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO), 221 GATE(HCLK_PERI, "hclk_peri", "hclk_peri_src", 0, 222 RK2928_CLKGATE_CON(2), 2, GFLAGS), 223 224 COMPOSITE_NODIV(SCLK_TIMER0, "sclk_timer0", mux_timer_p, CLK_IGNORE_UNUSED, 225 RK2928_CLKSEL_CON(2), 4, 1, MFLAGS, 226 RK2928_CLKGATE_CON(1), 0, GFLAGS), 227 COMPOSITE_NODIV(SCLK_TIMER1, "sclk_timer1", mux_timer_p, CLK_IGNORE_UNUSED, 228 RK2928_CLKSEL_CON(2), 5, 1, MFLAGS, 229 RK2928_CLKGATE_CON(1), 1, GFLAGS), 230 COMPOSITE_NODIV(SCLK_TIMER2, "sclk_timer2", mux_timer_p, CLK_IGNORE_UNUSED, 231 RK2928_CLKSEL_CON(2), 6, 1, MFLAGS, 232 RK2928_CLKGATE_CON(2), 4, GFLAGS), 233 COMPOSITE_NODIV(SCLK_TIMER3, "sclk_timer3", mux_timer_p, CLK_IGNORE_UNUSED, 234 RK2928_CLKSEL_CON(2), 7, 1, MFLAGS, 235 RK2928_CLKGATE_CON(2), 5, GFLAGS), 236 237 MUX(0, "uart_pll_clk", mux_pll_src_apll_dpll_gpll_usb480m_p, 0, 238 RK2928_CLKSEL_CON(13), 10, 2, MFLAGS), 239 COMPOSITE_NOMUX(0, "uart0_src", "uart_pll_clk", 0, 240 RK2928_CLKSEL_CON(13), 0, 7, DFLAGS, 241 RK2928_CLKGATE_CON(1), 8, GFLAGS), 242 COMPOSITE_NOMUX(0, "uart1_src", "uart_pll_clk", 0, 243 RK2928_CLKSEL_CON(14), 0, 7, DFLAGS, 244 RK2928_CLKGATE_CON(1), 10, GFLAGS), 245 COMPOSITE_NOMUX(0, "uart2_src", "uart_pll_clk", 0, 246 RK2928_CLKSEL_CON(15), 0, 7, DFLAGS, 247 RK2928_CLKGATE_CON(1), 12, GFLAGS), 248 COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT, 249 RK2928_CLKSEL_CON(17), 0, 250 RK2928_CLKGATE_CON(1), 9, GFLAGS, 251 &rk3036_uart0_fracmux), 252 COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT, 253 RK2928_CLKSEL_CON(18), 0, 254 RK2928_CLKGATE_CON(1), 11, GFLAGS, 255 &rk3036_uart1_fracmux), 256 COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT, 257 RK2928_CLKSEL_CON(19), 0, 258 RK2928_CLKGATE_CON(1), 13, GFLAGS, 259 &rk3036_uart2_fracmux), 260 261 COMPOSITE(0, "aclk_vcodec", mux_pll_src_3plls_p, 0, 262 RK2928_CLKSEL_CON(32), 14, 2, MFLAGS, 8, 5, DFLAGS, 263 RK2928_CLKGATE_CON(3), 11, GFLAGS), 264 FACTOR_GATE(HCLK_VCODEC, "hclk_vcodec", "aclk_vcodec", 0, 1, 4, 265 RK2928_CLKGATE_CON(3), 12, GFLAGS), 266 267 COMPOSITE(0, "aclk_hvec", mux_pll_src_3plls_p, 0, 268 RK2928_CLKSEL_CON(20), 0, 2, MFLAGS, 2, 5, DFLAGS, 269 RK2928_CLKGATE_CON(10), 6, GFLAGS), 270 271 COMPOSITE(0, "aclk_disp1_pre", mux_pll_src_3plls_p, 0, 272 RK2928_CLKSEL_CON(31), 14, 2, MFLAGS, 8, 5, DFLAGS, 273 RK2928_CLKGATE_CON(1), 4, GFLAGS), 274 COMPOSITE(0, "hclk_disp_pre", mux_pll_src_3plls_p, 0, 275 RK2928_CLKSEL_CON(30), 14, 2, MFLAGS, 8, 5, DFLAGS, 276 RK2928_CLKGATE_CON(0), 11, GFLAGS), 277 COMPOSITE(SCLK_LCDC, "dclk_lcdc", mux_pll_src_3plls_p, 0, 278 RK2928_CLKSEL_CON(28), 0, 2, MFLAGS, 8, 8, DFLAGS, 279 RK2928_CLKGATE_CON(3), 2, GFLAGS), 280 281 COMPOSITE_NODIV(0, "sclk_sdmmc_src", mux_mmc_src_p, 0, 282 RK2928_CLKSEL_CON(12), 8, 2, MFLAGS, 283 RK2928_CLKGATE_CON(2), 11, GFLAGS), 284 DIV(SCLK_SDMMC, "sclk_sdmmc", "sclk_sdmmc_src", 0, 285 RK2928_CLKSEL_CON(11), 0, 7, DFLAGS), 286 287 COMPOSITE_NODIV(0, "sclk_sdio_src", mux_mmc_src_p, 0, 288 RK2928_CLKSEL_CON(12), 10, 2, MFLAGS, 289 RK2928_CLKGATE_CON(2), 13, GFLAGS), 290 DIV(SCLK_SDIO, "sclk_sdio", "sclk_sdio_src", 0, 291 RK2928_CLKSEL_CON(11), 8, 7, DFLAGS), 292 293 COMPOSITE(SCLK_EMMC, "sclk_emmc", mux_mmc_src_p, 0, 294 RK2928_CLKSEL_CON(12), 12, 2, MFLAGS, 0, 7, DFLAGS, 295 RK2928_CLKGATE_CON(2), 14, GFLAGS), 296 297 MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "sclk_sdmmc", RK3036_SDMMC_CON0, 1), 298 MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RK3036_SDMMC_CON1, 0), 299 300 MMC(SCLK_SDIO_DRV, "sdio_drv", "sclk_sdio", RK3036_SDIO_CON0, 1), 301 MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "sclk_sdio", RK3036_SDIO_CON1, 0), 302 303 MMC(SCLK_EMMC_DRV, "emmc_drv", "sclk_emmc", RK3036_EMMC_CON0, 1), 304 MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "sclk_emmc", RK3036_EMMC_CON1, 0), 305 306 COMPOSITE(0, "i2s_src", mux_pll_src_3plls_p, 0, 307 RK2928_CLKSEL_CON(3), 14, 2, MFLAGS, 0, 7, DFLAGS, 308 RK2928_CLKGATE_CON(0), 9, GFLAGS), 309 COMPOSITE_FRACMUX(0, "i2s_frac", "i2s_src", CLK_SET_RATE_PARENT, 310 RK2928_CLKSEL_CON(7), 0, 311 RK2928_CLKGATE_CON(0), 10, GFLAGS, 312 &rk3036_i2s_fracmux), 313 COMPOSITE_NODIV(SCLK_I2S_OUT, "i2s_clkout", mux_i2s_clkout_p, 0, 314 RK2928_CLKSEL_CON(3), 12, 1, MFLAGS, 315 RK2928_CLKGATE_CON(0), 13, GFLAGS), 316 GATE(SCLK_I2S, "sclk_i2s", "i2s_pre", CLK_SET_RATE_PARENT, 317 RK2928_CLKGATE_CON(0), 14, GFLAGS), 318 319 COMPOSITE(0, "spdif_src", mux_pll_src_3plls_p, 0, 320 RK2928_CLKSEL_CON(5), 10, 2, MFLAGS, 0, 7, DFLAGS, 321 RK2928_CLKGATE_CON(2), 10, GFLAGS), 322 COMPOSITE_FRACMUX(0, "spdif_frac", "spdif_src", 0, 323 RK2928_CLKSEL_CON(9), 0, 324 RK2928_CLKGATE_CON(2), 12, GFLAGS, 325 &rk3036_spdif_fracmux), 326 327 GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin12m", CLK_IGNORE_UNUSED, 328 RK2928_CLKGATE_CON(1), 5, GFLAGS), 329 330 COMPOSITE(SCLK_GPU, "sclk_gpu", mux_pll_src_3plls_p, 0, 331 RK2928_CLKSEL_CON(34), 8, 2, MFLAGS, 0, 5, DFLAGS, 332 RK2928_CLKGATE_CON(3), 13, GFLAGS), 333 334 COMPOSITE(SCLK_SPI, "sclk_spi", mux_pll_src_3plls_p, 0, 335 RK2928_CLKSEL_CON(25), 8, 2, MFLAGS, 0, 7, DFLAGS, 336 RK2928_CLKGATE_CON(2), 9, GFLAGS), 337 338 COMPOSITE(SCLK_NANDC, "sclk_nandc", mux_pll_src_3plls_p, 0, 339 RK2928_CLKSEL_CON(16), 8, 2, MFLAGS, 10, 5, DFLAGS, 340 RK2928_CLKGATE_CON(10), 4, GFLAGS), 341 342 COMPOSITE(SCLK_SFC, "sclk_sfc", mux_pll_src_apll_dpll_gpll_usb480m_p, 0, 343 RK2928_CLKSEL_CON(16), 0, 2, MFLAGS, 2, 5, DFLAGS, 344 RK2928_CLKGATE_CON(10), 5, GFLAGS), 345 346 COMPOSITE_NOGATE(SCLK_MACPLL, "mac_pll_src", mux_pll_src_3plls_p, CLK_SET_RATE_NO_REPARENT, 347 RK2928_CLKSEL_CON(21), 0, 2, MFLAGS, 9, 5, DFLAGS), 348 MUX(SCLK_MACREF, "mac_clk_ref", mux_mac_p, CLK_SET_RATE_PARENT, 349 RK2928_CLKSEL_CON(21), 3, 1, MFLAGS), 350 351 COMPOSITE_NOMUX(SCLK_MAC, "mac_clk", "mac_clk_ref", 0, 352 RK2928_CLKSEL_CON(21), 4, 5, DFLAGS, 353 RK2928_CLKGATE_CON(2), 6, GFLAGS), 354 FACTOR(0, "sclk_macref_out", "hclk_peri_src", 0, 1, 2), 355 356 MUX(SCLK_HDMI, "dclk_hdmi", mux_dclk_p, 0, 357 RK2928_CLKSEL_CON(31), 0, 1, MFLAGS), 358 359 /* 360 * Clock-Architecture Diagram 3 361 */ 362 363 /* aclk_cpu gates */ 364 GATE(0, "sclk_intmem", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 12, GFLAGS), 365 GATE(0, "aclk_strc_sys", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 10, GFLAGS), 366 367 /* hclk_cpu gates */ 368 GATE(HCLK_ROM, "hclk_rom", "hclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 6, GFLAGS), 369 370 /* pclk_cpu gates */ 371 GATE(PCLK_GRF, "pclk_grf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 4, GFLAGS), 372 GATE(PCLK_DDRUPCTL, "pclk_ddrupctl", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 7, GFLAGS), 373 GATE(PCLK_ACODEC, "pclk_acodec", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 14, GFLAGS), 374 GATE(PCLK_HDMI, "pclk_hdmi", "pclk_cpu", 0, RK2928_CLKGATE_CON(3), 8, GFLAGS), 375 376 /* aclk_vio gates */ 377 GATE(ACLK_VIO, "aclk_vio", "aclk_disp1_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(6), 13, GFLAGS), 378 GATE(ACLK_LCDC, "aclk_lcdc", "aclk_disp1_pre", 0, RK2928_CLKGATE_CON(9), 6, GFLAGS), 379 380 GATE(HCLK_VIO_BUS, "hclk_vio_bus", "hclk_disp_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(6), 12, GFLAGS), 381 GATE(HCLK_LCDC, "hclk_lcdc", "hclk_disp_pre", 0, RK2928_CLKGATE_CON(9), 5, GFLAGS), 382 383 384 /* xin24m gates */ 385 GATE(SCLK_PVTM_CORE, "sclk_pvtm_core", "xin24m", 0, RK2928_CLKGATE_CON(10), 0, GFLAGS), 386 GATE(SCLK_PVTM_GPU, "sclk_pvtm_gpu", "xin24m", 0, RK2928_CLKGATE_CON(10), 1, GFLAGS), 387 388 /* aclk_peri gates */ 389 GATE(0, "aclk_peri_axi_matrix", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 3, GFLAGS), 390 GATE(0, "aclk_cpu_peri", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 2, GFLAGS), 391 GATE(ACLK_DMAC2, "aclk_dmac2", "aclk_peri", 0, RK2928_CLKGATE_CON(5), 1, GFLAGS), 392 GATE(0, "aclk_peri_niu", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 15, GFLAGS), 393 394 /* hclk_peri gates */ 395 GATE(0, "hclk_peri_matrix", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 0, GFLAGS), 396 GATE(0, "hclk_usb_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 13, GFLAGS), 397 GATE(0, "hclk_peri_arbi", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 14, GFLAGS), 398 GATE(HCLK_NANDC, "hclk_nandc", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 9, GFLAGS), 399 GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 10, GFLAGS), 400 GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 11, GFLAGS), 401 GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 0, GFLAGS), 402 GATE(HCLK_OTG0, "hclk_otg0", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 13, GFLAGS), 403 GATE(HCLK_OTG1, "hclk_otg1", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(7), 3, GFLAGS), 404 GATE(HCLK_I2S, "hclk_i2s", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 2, GFLAGS), 405 GATE(0, "hclk_sfc", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(3), 14, GFLAGS), 406 GATE(HCLK_MAC, "hclk_mac", "hclk_peri", 0, RK2928_CLKGATE_CON(3), 5, GFLAGS), 407 408 /* pclk_peri gates */ 409 GATE(0, "pclk_peri_matrix", "pclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 1, GFLAGS), 410 GATE(0, "pclk_efuse", "pclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 2, GFLAGS), 411 GATE(PCLK_TIMER, "pclk_timer", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 7, GFLAGS), 412 GATE(PCLK_PWM, "pclk_pwm", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 10, GFLAGS), 413 GATE(PCLK_SPI, "pclk_spi", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 12, GFLAGS), 414 GATE(PCLK_WDT, "pclk_wdt", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 15, GFLAGS), 415 GATE(PCLK_UART0, "pclk_uart0", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 0, GFLAGS), 416 GATE(PCLK_UART1, "pclk_uart1", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 1, GFLAGS), 417 GATE(PCLK_UART2, "pclk_uart2", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 2, GFLAGS), 418 GATE(PCLK_I2C0, "pclk_i2c0", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 4, GFLAGS), 419 GATE(PCLK_I2C1, "pclk_i2c1", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 5, GFLAGS), 420 GATE(PCLK_I2C2, "pclk_i2c2", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 6, GFLAGS), 421 GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 9, GFLAGS), 422 GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 10, GFLAGS), 423 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 11, GFLAGS), 424}; 425 426static const char *const rk3036_critical_clocks[] __initconst = { 427 "aclk_cpu", 428 "aclk_peri", 429 "hclk_peri", 430 "pclk_peri", 431 "pclk_ddrupctl", 432}; 433 434static void __init rk3036_clk_init(struct device_node *np) 435{ 436 struct rockchip_clk_provider *ctx; 437 void __iomem *reg_base; 438 struct clk *clk; 439 440 reg_base = of_iomap(np, 0); 441 if (!reg_base) { 442 pr_err("%s: could not map cru region\n", __func__); 443 return; 444 } 445 446 /* 447 * Make uart_pll_clk a child of the gpll, as all other sources are 448 * not that usable / stable. 449 */ 450 writel_relaxed(HIWORD_UPDATE(0x2, 0x3, 10), 451 reg_base + RK2928_CLKSEL_CON(13)); 452 453 ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS); 454 if (IS_ERR(ctx)) { 455 pr_err("%s: rockchip clk init failed\n", __func__); 456 iounmap(reg_base); 457 return; 458 } 459 460 clk = clk_register_fixed_factor(NULL, "usb480m", "xin24m", 0, 20, 1); 461 if (IS_ERR(clk)) 462 pr_warn("%s: could not register clock usb480m: %ld\n", 463 __func__, PTR_ERR(clk)); 464 465 rockchip_clk_register_plls(ctx, rk3036_pll_clks, 466 ARRAY_SIZE(rk3036_pll_clks), 467 RK3036_GRF_SOC_STATUS0); 468 rockchip_clk_register_branches(ctx, rk3036_clk_branches, 469 ARRAY_SIZE(rk3036_clk_branches)); 470 rockchip_clk_protect_critical(rk3036_critical_clocks, 471 ARRAY_SIZE(rk3036_critical_clocks)); 472 473 rockchip_clk_register_armclk(ctx, ARMCLK, "armclk", 474 mux_armclk_p, ARRAY_SIZE(mux_armclk_p), 475 &rk3036_cpuclk_data, rk3036_cpuclk_rates, 476 ARRAY_SIZE(rk3036_cpuclk_rates)); 477 478 rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0), 479 ROCKCHIP_SOFTRST_HIWORD_MASK); 480 481 rockchip_register_restart_notifier(ctx, RK2928_GLB_SRST_FST, NULL); 482 483 rockchip_clk_of_add_provider(np, ctx); 484} 485CLK_OF_DECLARE(rk3036_cru, "rockchip,rk3036-cru", rk3036_clk_init); 486