1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * Copyright (c) 2018 Rockchip Electronics Co. Ltd. 4 * Author: Elaine Zhang<zhangqing@rock-chips.com> 5 */ 6 7#include <linux/clk-provider.h> 8#include <linux/io.h> 9#include <linux/of.h> 10#include <linux/of_address.h> 11#include <linux/syscore_ops.h> 12#include <dt-bindings/clock/px30-cru.h> 13#include "clk.h" 14 15#define PX30_GRF_SOC_STATUS0 0x480 16 17enum px30_plls { 18 apll, dpll, cpll, npll, apll_b_h, apll_b_l, 19}; 20 21enum px30_pmu_plls { 22 gpll, 23}; 24 25static struct rockchip_pll_rate_table px30_pll_rates[] = { 26 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ 27 RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0), 28 RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0), 29 RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0), 30 RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0), 31 RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0), 32 RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0), 33 RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0), 34 RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0), 35 RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0), 36 RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0), 37 RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0), 38 RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0), 39 RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0), 40 RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0), 41 RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0), 42 RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0), 43 RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0), 44 RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0), 45 RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0), 46 RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0), 47 RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0), 48 RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0), 49 RK3036_PLL_RATE(984000000, 1, 82, 2, 1, 1, 0), 50 RK3036_PLL_RATE(960000000, 1, 80, 2, 1, 1, 0), 51 RK3036_PLL_RATE(936000000, 1, 78, 2, 1, 1, 0), 52 RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0), 53 RK3036_PLL_RATE(900000000, 4, 300, 2, 1, 1, 0), 54 RK3036_PLL_RATE(888000000, 1, 74, 2, 1, 1, 0), 55 RK3036_PLL_RATE(864000000, 1, 72, 2, 1, 1, 0), 56 RK3036_PLL_RATE(840000000, 1, 70, 2, 1, 1, 0), 57 RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0), 58 RK3036_PLL_RATE(800000000, 6, 400, 2, 1, 1, 0), 59 RK3036_PLL_RATE(700000000, 6, 350, 2, 1, 1, 0), 60 RK3036_PLL_RATE(696000000, 1, 58, 2, 1, 1, 0), 61 RK3036_PLL_RATE(624000000, 1, 52, 2, 1, 1, 0), 62 RK3036_PLL_RATE(600000000, 1, 75, 3, 1, 1, 0), 63 RK3036_PLL_RATE(594000000, 2, 99, 2, 1, 1, 0), 64 RK3036_PLL_RATE(504000000, 1, 63, 3, 1, 1, 0), 65 RK3036_PLL_RATE(500000000, 6, 250, 2, 1, 1, 0), 66 RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0), 67 RK3036_PLL_RATE(312000000, 1, 52, 2, 2, 1, 0), 68 RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0), 69 RK3036_PLL_RATE(96000000, 1, 64, 4, 4, 1, 0), 70 { /* sentinel */ }, 71}; 72 73#define PX30_DIV_ACLKM_MASK 0x7 74#define PX30_DIV_ACLKM_SHIFT 12 75#define PX30_DIV_PCLK_DBG_MASK 0xf 76#define PX30_DIV_PCLK_DBG_SHIFT 8 77 78#define PX30_CLKSEL0(_aclk_core, _pclk_dbg) \ 79{ \ 80 .reg = PX30_CLKSEL_CON(0), \ 81 .val = HIWORD_UPDATE(_aclk_core, PX30_DIV_ACLKM_MASK, \ 82 PX30_DIV_ACLKM_SHIFT) | \ 83 HIWORD_UPDATE(_pclk_dbg, PX30_DIV_PCLK_DBG_MASK, \ 84 PX30_DIV_PCLK_DBG_SHIFT), \ 85} 86 87#define PX30_CPUCLK_RATE(_prate, _aclk_core, _pclk_dbg) \ 88{ \ 89 .prate = _prate, \ 90 .divs = { \ 91 PX30_CLKSEL0(_aclk_core, _pclk_dbg), \ 92 }, \ 93} 94 95static struct rockchip_cpuclk_rate_table px30_cpuclk_rates[] __initdata = { 96 PX30_CPUCLK_RATE(1608000000, 1, 7), 97 PX30_CPUCLK_RATE(1584000000, 1, 7), 98 PX30_CPUCLK_RATE(1560000000, 1, 7), 99 PX30_CPUCLK_RATE(1536000000, 1, 7), 100 PX30_CPUCLK_RATE(1512000000, 1, 7), 101 PX30_CPUCLK_RATE(1488000000, 1, 5), 102 PX30_CPUCLK_RATE(1464000000, 1, 5), 103 PX30_CPUCLK_RATE(1440000000, 1, 5), 104 PX30_CPUCLK_RATE(1416000000, 1, 5), 105 PX30_CPUCLK_RATE(1392000000, 1, 5), 106 PX30_CPUCLK_RATE(1368000000, 1, 5), 107 PX30_CPUCLK_RATE(1344000000, 1, 5), 108 PX30_CPUCLK_RATE(1320000000, 1, 5), 109 PX30_CPUCLK_RATE(1296000000, 1, 5), 110 PX30_CPUCLK_RATE(1272000000, 1, 5), 111 PX30_CPUCLK_RATE(1248000000, 1, 5), 112 PX30_CPUCLK_RATE(1224000000, 1, 5), 113 PX30_CPUCLK_RATE(1200000000, 1, 5), 114 PX30_CPUCLK_RATE(1104000000, 1, 5), 115 PX30_CPUCLK_RATE(1008000000, 1, 5), 116 PX30_CPUCLK_RATE(912000000, 1, 5), 117 PX30_CPUCLK_RATE(816000000, 1, 3), 118 PX30_CPUCLK_RATE(696000000, 1, 3), 119 PX30_CPUCLK_RATE(600000000, 1, 3), 120 PX30_CPUCLK_RATE(408000000, 1, 1), 121 PX30_CPUCLK_RATE(312000000, 1, 1), 122 PX30_CPUCLK_RATE(216000000, 1, 1), 123 PX30_CPUCLK_RATE(96000000, 1, 1), 124}; 125 126static const struct rockchip_cpuclk_reg_data px30_cpuclk_data = { 127 .core_reg = PX30_CLKSEL_CON(0), 128 .div_core_shift = 0, 129 .div_core_mask = 0xf, 130 .mux_core_alt = 1, 131 .mux_core_main = 0, 132 .mux_core_shift = 7, 133 .mux_core_mask = 0x1, 134}; 135 136PNAME(mux_pll_p) = { "xin24m"}; 137PNAME(mux_usb480m_p) = { "xin24m", "usb480m_phy", "clk_rtc32k_pmu" }; 138PNAME(mux_armclk_p) = { "apll_core", "gpll_core" }; 139PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr" }; 140PNAME(mux_ddrstdby_p) = { "clk_ddrphy1x", "clk_stdby_2wrap" }; 141PNAME(mux_4plls_p) = { "gpll", "dummy_cpll", "usb480m", "npll" }; 142PNAME(mux_cpll_npll_p) = { "cpll", "npll" }; 143PNAME(mux_npll_cpll_p) = { "npll", "cpll" }; 144PNAME(mux_gpll_cpll_p) = { "gpll", "dummy_cpll" }; 145PNAME(mux_gpll_npll_p) = { "gpll", "npll" }; 146PNAME(mux_gpll_xin24m_p) = { "gpll", "xin24m"}; 147PNAME(mux_gpll_cpll_npll_p) = { "gpll", "dummy_cpll", "npll" }; 148PNAME(mux_gpll_cpll_npll_xin24m_p) = { "gpll", "dummy_cpll", "npll", "xin24m" }; 149PNAME(mux_gpll_xin24m_npll_p) = { "gpll", "xin24m", "npll"}; 150PNAME(mux_pdm_p) = { "clk_pdm_src", "clk_pdm_frac" }; 151PNAME(mux_i2s0_tx_p) = { "clk_i2s0_tx_src", "clk_i2s0_tx_frac", "mclk_i2s0_tx_in", "xin12m"}; 152PNAME(mux_i2s0_rx_p) = { "clk_i2s0_rx_src", "clk_i2s0_rx_frac", "mclk_i2s0_rx_in", "xin12m"}; 153PNAME(mux_i2s1_p) = { "clk_i2s1_src", "clk_i2s1_frac", "i2s1_clkin", "xin12m"}; 154PNAME(mux_i2s2_p) = { "clk_i2s2_src", "clk_i2s2_frac", "i2s2_clkin", "xin12m"}; 155PNAME(mux_i2s0_tx_out_p) = { "clk_i2s0_tx", "xin12m", "clk_i2s0_rx"}; 156PNAME(mux_i2s0_rx_out_p) = { "clk_i2s0_rx", "xin12m", "clk_i2s0_tx"}; 157PNAME(mux_i2s1_out_p) = { "clk_i2s1", "xin12m"}; 158PNAME(mux_i2s2_out_p) = { "clk_i2s2", "xin12m"}; 159PNAME(mux_i2s0_tx_rx_p) = { "clk_i2s0_tx_mux", "clk_i2s0_rx_mux"}; 160PNAME(mux_i2s0_rx_tx_p) = { "clk_i2s0_rx_mux", "clk_i2s0_tx_mux"}; 161PNAME(mux_uart_src_p) = { "gpll", "xin24m", "usb480m", "npll" }; 162PNAME(mux_uart1_p) = { "clk_uart1_src", "clk_uart1_np5", "clk_uart1_frac" }; 163PNAME(mux_uart2_p) = { "clk_uart2_src", "clk_uart2_np5", "clk_uart2_frac" }; 164PNAME(mux_uart3_p) = { "clk_uart3_src", "clk_uart3_np5", "clk_uart3_frac" }; 165PNAME(mux_uart4_p) = { "clk_uart4_src", "clk_uart4_np5", "clk_uart4_frac" }; 166PNAME(mux_uart5_p) = { "clk_uart5_src", "clk_uart5_np5", "clk_uart5_frac" }; 167PNAME(mux_cif_out_p) = { "xin24m", "dummy_cpll", "npll", "usb480m" }; 168PNAME(mux_dclk_vopb_p) = { "dclk_vopb_src", "dclk_vopb_frac", "xin24m" }; 169PNAME(mux_dclk_vopl_p) = { "dclk_vopl_src", "dclk_vopl_frac", "xin24m" }; 170PNAME(mux_nandc_p) = { "clk_nandc_div", "clk_nandc_div50" }; 171PNAME(mux_sdio_p) = { "clk_sdio_div", "clk_sdio_div50" }; 172PNAME(mux_emmc_p) = { "clk_emmc_div", "clk_emmc_div50" }; 173PNAME(mux_sdmmc_p) = { "clk_sdmmc_div", "clk_sdmmc_div50" }; 174PNAME(mux_gmac_p) = { "clk_gmac_src", "gmac_clkin" }; 175PNAME(mux_gmac_rmii_sel_p) = { "clk_gmac_rx_tx_div20", "clk_gmac_rx_tx_div2" }; 176PNAME(mux_rtc32k_pmu_p) = { "xin32k", "pmu_pvtm_32k", "clk_rtc32k_frac", }; 177PNAME(mux_wifi_pmu_p) = { "xin24m", "clk_wifi_pmu_src" }; 178PNAME(mux_uart0_pmu_p) = { "clk_uart0_pmu_src", "clk_uart0_np5", "clk_uart0_frac" }; 179PNAME(mux_usbphy_ref_p) = { "xin24m", "clk_ref24m_pmu" }; 180PNAME(mux_mipidsiphy_ref_p) = { "xin24m", "clk_ref24m_pmu" }; 181PNAME(mux_gpu_p) = { "clk_gpu_div", "clk_gpu_np5" }; 182 183static struct rockchip_pll_clock px30_pll_clks[] __initdata = { 184 [apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p, 185 0, PX30_PLL_CON(0), 186 PX30_MODE_CON, 0, 0, 0, px30_pll_rates), 187 [dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p, 188 0, PX30_PLL_CON(8), 189 PX30_MODE_CON, 4, 1, 0, NULL), 190 [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p, 191 0, PX30_PLL_CON(16), 192 PX30_MODE_CON, 2, 2, 0, px30_pll_rates), 193 [npll] = PLL(pll_rk3328, PLL_NPLL, "npll", mux_pll_p, 194 0, PX30_PLL_CON(24), 195 PX30_MODE_CON, 6, 4, 0, px30_pll_rates), 196}; 197 198static struct rockchip_pll_clock px30_pmu_pll_clks[] __initdata = { 199 [gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p, 0, PX30_PMU_PLL_CON(0), 200 PX30_PMU_MODE, 0, 3, 0, px30_pll_rates), 201}; 202 203#define MFLAGS CLK_MUX_HIWORD_MASK 204#define DFLAGS CLK_DIVIDER_HIWORD_MASK 205#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE) 206 207static struct rockchip_clk_branch px30_pdm_fracmux __initdata = 208 MUX(0, "clk_pdm_mux", mux_pdm_p, CLK_SET_RATE_PARENT, 209 PX30_CLKSEL_CON(26), 15, 1, MFLAGS); 210 211static struct rockchip_clk_branch px30_i2s0_tx_fracmux __initdata = 212 MUX(0, "clk_i2s0_tx_mux", mux_i2s0_tx_p, CLK_SET_RATE_PARENT, 213 PX30_CLKSEL_CON(28), 10, 2, MFLAGS); 214 215static struct rockchip_clk_branch px30_i2s0_rx_fracmux __initdata = 216 MUX(0, "clk_i2s0_rx_mux", mux_i2s0_rx_p, CLK_SET_RATE_PARENT, 217 PX30_CLKSEL_CON(58), 10, 2, MFLAGS); 218 219static struct rockchip_clk_branch px30_i2s1_fracmux __initdata = 220 MUX(0, "clk_i2s1_mux", mux_i2s1_p, CLK_SET_RATE_PARENT, 221 PX30_CLKSEL_CON(30), 10, 2, MFLAGS); 222 223static struct rockchip_clk_branch px30_i2s2_fracmux __initdata = 224 MUX(0, "clk_i2s2_mux", mux_i2s2_p, CLK_SET_RATE_PARENT, 225 PX30_CLKSEL_CON(32), 10, 2, MFLAGS); 226 227static struct rockchip_clk_branch px30_uart1_fracmux __initdata = 228 MUX(0, "clk_uart1_mux", mux_uart1_p, CLK_SET_RATE_PARENT, 229 PX30_CLKSEL_CON(35), 14, 2, MFLAGS); 230 231static struct rockchip_clk_branch px30_uart2_fracmux __initdata = 232 MUX(0, "clk_uart2_mux", mux_uart2_p, CLK_SET_RATE_PARENT, 233 PX30_CLKSEL_CON(38), 14, 2, MFLAGS); 234 235static struct rockchip_clk_branch px30_uart3_fracmux __initdata = 236 MUX(0, "clk_uart3_mux", mux_uart3_p, CLK_SET_RATE_PARENT, 237 PX30_CLKSEL_CON(41), 14, 2, MFLAGS); 238 239static struct rockchip_clk_branch px30_uart4_fracmux __initdata = 240 MUX(0, "clk_uart4_mux", mux_uart4_p, CLK_SET_RATE_PARENT, 241 PX30_CLKSEL_CON(44), 14, 2, MFLAGS); 242 243static struct rockchip_clk_branch px30_uart5_fracmux __initdata = 244 MUX(0, "clk_uart5_mux", mux_uart5_p, CLK_SET_RATE_PARENT, 245 PX30_CLKSEL_CON(47), 14, 2, MFLAGS); 246 247static struct rockchip_clk_branch px30_dclk_vopb_fracmux __initdata = 248 MUX(0, "dclk_vopb_mux", mux_dclk_vopb_p, CLK_SET_RATE_PARENT, 249 PX30_CLKSEL_CON(5), 14, 2, MFLAGS); 250 251static struct rockchip_clk_branch px30_dclk_vopl_fracmux __initdata = 252 MUX(0, "dclk_vopl_mux", mux_dclk_vopl_p, CLK_SET_RATE_PARENT, 253 PX30_CLKSEL_CON(8), 14, 2, MFLAGS); 254 255static struct rockchip_clk_branch px30_rtc32k_pmu_fracmux __initdata = 256 MUX(SCLK_RTC32K_PMU, "clk_rtc32k_pmu", mux_rtc32k_pmu_p, CLK_SET_RATE_PARENT, 257 PX30_PMU_CLKSEL_CON(0), 14, 2, MFLAGS); 258 259static struct rockchip_clk_branch px30_uart0_pmu_fracmux __initdata = 260 MUX(0, "clk_uart0_pmu_mux", mux_uart0_pmu_p, CLK_SET_RATE_PARENT, 261 PX30_PMU_CLKSEL_CON(4), 14, 2, MFLAGS); 262 263static struct rockchip_clk_branch px30_clk_branches[] __initdata = { 264 /* 265 * Clock-Architecture Diagram 1 266 */ 267 268 MUX(USB480M, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT, 269 PX30_MODE_CON, 8, 2, MFLAGS), 270 FACTOR(0, "xin12m", "xin24m", 0, 1, 2), 271 272 /* 273 * Clock-Architecture Diagram 3 274 */ 275 276 /* PD_CORE */ 277 GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED, 278 PX30_CLKGATE_CON(0), 0, GFLAGS), 279 GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED, 280 PX30_CLKGATE_CON(0), 0, GFLAGS), 281 COMPOSITE_NOMUX(0, "pclk_dbg", "armclk", CLK_IGNORE_UNUSED, 282 PX30_CLKSEL_CON(0), 8, 4, DFLAGS | CLK_DIVIDER_READ_ONLY, 283 PX30_CLKGATE_CON(0), 2, GFLAGS), 284 COMPOSITE_NOMUX(0, "aclk_core", "armclk", CLK_IGNORE_UNUSED, 285 PX30_CLKSEL_CON(0), 12, 3, DFLAGS | CLK_DIVIDER_READ_ONLY, 286 PX30_CLKGATE_CON(0), 1, GFLAGS), 287 GATE(0, "aclk_core_niu", "aclk_core", CLK_IGNORE_UNUSED, 288 PX30_CLKGATE_CON(0), 4, GFLAGS), 289 GATE(0, "aclk_core_prf", "aclk_core", CLK_IGNORE_UNUSED, 290 PX30_CLKGATE_CON(17), 5, GFLAGS), 291 GATE(0, "pclk_dbg_niu", "pclk_dbg", CLK_IGNORE_UNUSED, 292 PX30_CLKGATE_CON(0), 5, GFLAGS), 293 GATE(0, "pclk_core_dbg", "pclk_dbg", CLK_IGNORE_UNUSED, 294 PX30_CLKGATE_CON(0), 6, GFLAGS), 295 GATE(0, "pclk_core_grf", "pclk_dbg", CLK_IGNORE_UNUSED, 296 PX30_CLKGATE_CON(17), 6, GFLAGS), 297 298 GATE(0, "clk_jtag", "jtag_clkin", CLK_IGNORE_UNUSED, 299 PX30_CLKGATE_CON(0), 3, GFLAGS), 300 GATE(SCLK_PVTM, "clk_pvtm", "xin24m", 0, 301 PX30_CLKGATE_CON(17), 4, GFLAGS), 302 303 /* PD_GPU */ 304 COMPOSITE_NODIV(0, "clk_gpu_src", mux_4plls_p, 0, 305 PX30_CLKSEL_CON(1), 6, 2, MFLAGS, 306 PX30_CLKGATE_CON(0), 8, GFLAGS), 307 COMPOSITE_NOMUX(0, "clk_gpu_div", "clk_gpu_src", 0, 308 PX30_CLKSEL_CON(1), 0, 4, DFLAGS, 309 PX30_CLKGATE_CON(0), 12, GFLAGS), 310 COMPOSITE_NOMUX_HALFDIV(0, "clk_gpu_np5", "clk_gpu_src", 0, 311 PX30_CLKSEL_CON(1), 8, 4, DFLAGS, 312 PX30_CLKGATE_CON(0), 9, GFLAGS), 313 COMPOSITE_NODIV(SCLK_GPU, "clk_gpu", mux_gpu_p, CLK_SET_RATE_PARENT, 314 PX30_CLKSEL_CON(1), 15, 1, MFLAGS, 315 PX30_CLKGATE_CON(0), 10, GFLAGS), 316 COMPOSITE_NOMUX(0, "aclk_gpu", "clk_gpu", CLK_IGNORE_UNUSED, 317 PX30_CLKSEL_CON(1), 13, 2, DFLAGS, 318 PX30_CLKGATE_CON(17), 10, GFLAGS), 319 GATE(0, "aclk_gpu_niu", "aclk_gpu", CLK_IGNORE_UNUSED, 320 PX30_CLKGATE_CON(0), 11, GFLAGS), 321 GATE(0, "aclk_gpu_prf", "aclk_gpu", CLK_IGNORE_UNUSED, 322 PX30_CLKGATE_CON(17), 8, GFLAGS), 323 GATE(0, "pclk_gpu_grf", "aclk_gpu", CLK_IGNORE_UNUSED, 324 PX30_CLKGATE_CON(17), 9, GFLAGS), 325 326 /* 327 * Clock-Architecture Diagram 4 328 */ 329 330 /* PD_DDR */ 331 GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED, 332 PX30_CLKGATE_CON(0), 7, GFLAGS), 333 GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED, 334 PX30_CLKGATE_CON(0), 13, GFLAGS), 335 COMPOSITE_NOGATE(SCLK_DDRCLK, "sclk_ddrc", mux_ddrphy_p, CLK_IGNORE_UNUSED, 336 PX30_CLKSEL_CON(2), 7, 1, MFLAGS, 0, 3, DFLAGS | CLK_DIVIDER_POWER_OF_TWO), 337 COMPOSITE_NOGATE(0, "clk_ddrphy4x", mux_ddrphy_p, CLK_IGNORE_UNUSED, 338 PX30_CLKSEL_CON(2), 7, 1, MFLAGS, 0, 3, DFLAGS), 339 FACTOR_GATE(0, "clk_ddrphy1x", "clk_ddrphy4x", CLK_IGNORE_UNUSED, 1, 4, 340 PX30_CLKGATE_CON(0), 14, GFLAGS), 341 FACTOR_GATE(0, "clk_stdby_2wrap", "clk_ddrphy4x", CLK_IGNORE_UNUSED, 1, 4, 342 PX30_CLKGATE_CON(1), 0, GFLAGS), 343 COMPOSITE_NODIV(0, "clk_ddrstdby", mux_ddrstdby_p, CLK_IGNORE_UNUSED, 344 PX30_CLKSEL_CON(2), 4, 1, MFLAGS, 345 PX30_CLKGATE_CON(1), 13, GFLAGS), 346 GATE(0, "aclk_split", "clk_ddrphy1x", CLK_IGNORE_UNUSED, 347 PX30_CLKGATE_CON(1), 15, GFLAGS), 348 GATE(0, "clk_msch", "clk_ddrphy1x", CLK_IGNORE_UNUSED, 349 PX30_CLKGATE_CON(1), 8, GFLAGS), 350 GATE(0, "aclk_ddrc", "clk_ddrphy1x", CLK_IGNORE_UNUSED, 351 PX30_CLKGATE_CON(1), 5, GFLAGS), 352 GATE(0, "clk_core_ddrc", "clk_ddrphy1x", CLK_IGNORE_UNUSED, 353 PX30_CLKGATE_CON(1), 6, GFLAGS), 354 GATE(0, "aclk_cmd_buff", "clk_ddrphy1x", CLK_IGNORE_UNUSED, 355 PX30_CLKGATE_CON(1), 6, GFLAGS), 356 GATE(0, "clk_ddrmon", "clk_ddrphy1x", CLK_IGNORE_UNUSED, 357 PX30_CLKGATE_CON(1), 11, GFLAGS), 358 359 GATE(0, "clk_ddrmon_timer", "xin24m", CLK_IGNORE_UNUSED, 360 PX30_CLKGATE_CON(0), 15, GFLAGS), 361 362 COMPOSITE_NOMUX(PCLK_DDR, "pclk_ddr", "gpll", CLK_IGNORE_UNUSED, 363 PX30_CLKSEL_CON(2), 8, 5, DFLAGS, 364 PX30_CLKGATE_CON(1), 1, GFLAGS), 365 GATE(0, "pclk_ddrmon", "pclk_ddr", CLK_IGNORE_UNUSED, 366 PX30_CLKGATE_CON(1), 10, GFLAGS), 367 GATE(0, "pclk_ddrc", "pclk_ddr", CLK_IGNORE_UNUSED, 368 PX30_CLKGATE_CON(1), 7, GFLAGS), 369 GATE(0, "pclk_msch", "pclk_ddr", CLK_IGNORE_UNUSED, 370 PX30_CLKGATE_CON(1), 9, GFLAGS), 371 GATE(0, "pclk_stdby", "pclk_ddr", CLK_IGNORE_UNUSED, 372 PX30_CLKGATE_CON(1), 12, GFLAGS), 373 GATE(0, "pclk_ddr_grf", "pclk_ddr", CLK_IGNORE_UNUSED, 374 PX30_CLKGATE_CON(1), 14, GFLAGS), 375 GATE(0, "pclk_cmdbuff", "pclk_ddr", CLK_IGNORE_UNUSED, 376 PX30_CLKGATE_CON(1), 3, GFLAGS), 377 378 /* 379 * Clock-Architecture Diagram 5 380 */ 381 382 /* PD_VI */ 383 COMPOSITE(ACLK_VI_PRE, "aclk_vi_pre", mux_gpll_cpll_npll_p, 0, 384 PX30_CLKSEL_CON(11), 6, 2, MFLAGS, 0, 5, DFLAGS, 385 PX30_CLKGATE_CON(4), 8, GFLAGS), 386 COMPOSITE_NOMUX(HCLK_VI_PRE, "hclk_vi_pre", "aclk_vi_pre", 0, 387 PX30_CLKSEL_CON(11), 8, 4, DFLAGS, 388 PX30_CLKGATE_CON(4), 12, GFLAGS), 389 COMPOSITE(SCLK_ISP, "clk_isp", mux_gpll_cpll_npll_p, 0, 390 PX30_CLKSEL_CON(12), 6, 2, MFLAGS, 0, 5, DFLAGS, 391 PX30_CLKGATE_CON(4), 9, GFLAGS), 392 COMPOSITE(SCLK_CIF_OUT, "clk_cif_out", mux_cif_out_p, 0, 393 PX30_CLKSEL_CON(13), 6, 2, MFLAGS, 0, 6, DFLAGS, 394 PX30_CLKGATE_CON(4), 11, GFLAGS), 395 GATE(PCLK_ISP, "pclkin_isp", "ext_pclkin", 0, 396 PX30_CLKGATE_CON(4), 13, GFLAGS), 397 GATE(PCLK_CIF, "pclkin_cif", "ext_pclkin", 0, 398 PX30_CLKGATE_CON(4), 14, GFLAGS), 399 400 /* 401 * Clock-Architecture Diagram 6 402 */ 403 404 /* PD_VO */ 405 COMPOSITE(ACLK_VO_PRE, "aclk_vo_pre", mux_gpll_cpll_npll_p, 0, 406 PX30_CLKSEL_CON(3), 6, 2, MFLAGS, 0, 5, DFLAGS, 407 PX30_CLKGATE_CON(2), 0, GFLAGS), 408 COMPOSITE_NOMUX(HCLK_VO_PRE, "hclk_vo_pre", "aclk_vo_pre", 0, 409 PX30_CLKSEL_CON(3), 8, 4, DFLAGS, 410 PX30_CLKGATE_CON(2), 12, GFLAGS), 411 COMPOSITE_NOMUX(PCLK_VO_PRE, "pclk_vo_pre", "aclk_vo_pre", 0, 412 PX30_CLKSEL_CON(3), 12, 4, DFLAGS, 413 PX30_CLKGATE_CON(2), 13, GFLAGS), 414 COMPOSITE(SCLK_RGA_CORE, "clk_rga_core", mux_gpll_cpll_npll_p, 0, 415 PX30_CLKSEL_CON(4), 6, 2, MFLAGS, 0, 5, DFLAGS, 416 PX30_CLKGATE_CON(2), 1, GFLAGS), 417 418 COMPOSITE(SCLK_VOPB_PWM, "clk_vopb_pwm", mux_gpll_xin24m_p, 0, 419 PX30_CLKSEL_CON(7), 7, 1, MFLAGS, 0, 7, DFLAGS, 420 PX30_CLKGATE_CON(2), 5, GFLAGS), 421 COMPOSITE(0, "dclk_vopb_src", mux_cpll_npll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 422 PX30_CLKSEL_CON(5), 11, 1, MFLAGS, 0, 8, DFLAGS, 423 PX30_CLKGATE_CON(2), 2, GFLAGS), 424 COMPOSITE_FRACMUX(0, "dclk_vopb_frac", "dclk_vopb_src", CLK_SET_RATE_PARENT, 425 PX30_CLKSEL_CON(6), 0, 426 PX30_CLKGATE_CON(2), 3, GFLAGS, 427 &px30_dclk_vopb_fracmux), 428 GATE(DCLK_VOPB, "dclk_vopb", "dclk_vopb_mux", CLK_SET_RATE_PARENT, 429 PX30_CLKGATE_CON(2), 4, GFLAGS), 430 COMPOSITE(0, "dclk_vopl_src", mux_npll_cpll_p, 0, 431 PX30_CLKSEL_CON(8), 11, 1, MFLAGS, 0, 8, DFLAGS, 432 PX30_CLKGATE_CON(2), 6, GFLAGS), 433 COMPOSITE_FRACMUX(0, "dclk_vopl_frac", "dclk_vopl_src", CLK_SET_RATE_PARENT, 434 PX30_CLKSEL_CON(9), 0, 435 PX30_CLKGATE_CON(2), 7, GFLAGS, 436 &px30_dclk_vopl_fracmux), 437 GATE(DCLK_VOPL, "dclk_vopl", "dclk_vopl_mux", CLK_SET_RATE_PARENT, 438 PX30_CLKGATE_CON(2), 8, GFLAGS), 439 440 /* PD_VPU */ 441 COMPOSITE(0, "aclk_vpu_pre", mux_gpll_cpll_npll_p, 0, 442 PX30_CLKSEL_CON(10), 6, 2, MFLAGS, 0, 5, DFLAGS, 443 PX30_CLKGATE_CON(4), 0, GFLAGS), 444 COMPOSITE_NOMUX(0, "hclk_vpu_pre", "aclk_vpu_pre", 0, 445 PX30_CLKSEL_CON(10), 8, 4, DFLAGS, 446 PX30_CLKGATE_CON(4), 2, GFLAGS), 447 COMPOSITE(SCLK_CORE_VPU, "sclk_core_vpu", mux_gpll_cpll_npll_p, 0, 448 PX30_CLKSEL_CON(13), 14, 2, MFLAGS, 8, 5, DFLAGS, 449 PX30_CLKGATE_CON(4), 1, GFLAGS), 450 451 /* 452 * Clock-Architecture Diagram 7 453 */ 454 455 COMPOSITE_NODIV(ACLK_PERI_SRC, "aclk_peri_src", mux_gpll_cpll_p, 0, 456 PX30_CLKSEL_CON(14), 15, 1, MFLAGS, 457 PX30_CLKGATE_CON(5), 7, GFLAGS), 458 COMPOSITE_NOMUX(ACLK_PERI_PRE, "aclk_peri_pre", "aclk_peri_src", CLK_IGNORE_UNUSED, 459 PX30_CLKSEL_CON(14), 0, 5, DFLAGS, 460 PX30_CLKGATE_CON(5), 8, GFLAGS), 461 DIV(HCLK_PERI_PRE, "hclk_peri_pre", "aclk_peri_src", CLK_IGNORE_UNUSED, 462 PX30_CLKSEL_CON(14), 8, 5, DFLAGS), 463 464 /* PD_MMC_NAND */ 465 GATE(HCLK_MMC_NAND, "hclk_mmc_nand", "hclk_peri_pre", 0, 466 PX30_CLKGATE_CON(6), 0, GFLAGS), 467 COMPOSITE(SCLK_NANDC_DIV, "clk_nandc_div", mux_gpll_cpll_npll_p, 0, 468 PX30_CLKSEL_CON(15), 6, 2, MFLAGS, 0, 5, DFLAGS, 469 PX30_CLKGATE_CON(5), 11, GFLAGS), 470 COMPOSITE(SCLK_NANDC_DIV50, "clk_nandc_div50", mux_gpll_cpll_npll_p, 0, 471 PX30_CLKSEL_CON(15), 6, 2, MFLAGS, 8, 5, DFLAGS, 472 PX30_CLKGATE_CON(5), 12, GFLAGS), 473 COMPOSITE_NODIV(SCLK_NANDC, "clk_nandc", mux_nandc_p, 474 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 475 PX30_CLKSEL_CON(15), 15, 1, MFLAGS, 476 PX30_CLKGATE_CON(5), 13, GFLAGS), 477 478 COMPOSITE(SCLK_SDIO_DIV, "clk_sdio_div", mux_gpll_cpll_npll_xin24m_p, 0, 479 PX30_CLKSEL_CON(18), 14, 2, MFLAGS, 0, 8, DFLAGS, 480 PX30_CLKGATE_CON(6), 1, GFLAGS), 481 COMPOSITE_DIV_OFFSET(SCLK_SDIO_DIV50, "clk_sdio_div50", 482 mux_gpll_cpll_npll_xin24m_p, 0, 483 PX30_CLKSEL_CON(18), 14, 2, MFLAGS, 484 PX30_CLKSEL_CON(19), 0, 8, DFLAGS, 485 PX30_CLKGATE_CON(6), 2, GFLAGS), 486 COMPOSITE_NODIV(SCLK_SDIO, "clk_sdio", mux_sdio_p, 487 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 488 PX30_CLKSEL_CON(19), 15, 1, MFLAGS, 489 PX30_CLKGATE_CON(6), 3, GFLAGS), 490 491 COMPOSITE(SCLK_EMMC_DIV, "clk_emmc_div", mux_gpll_cpll_npll_xin24m_p, 0, 492 PX30_CLKSEL_CON(20), 14, 2, MFLAGS, 0, 8, DFLAGS, 493 PX30_CLKGATE_CON(6), 4, GFLAGS), 494 COMPOSITE_DIV_OFFSET(SCLK_EMMC_DIV50, "clk_emmc_div50", mux_gpll_cpll_npll_xin24m_p, 0, 495 PX30_CLKSEL_CON(20), 14, 2, MFLAGS, 496 PX30_CLKSEL_CON(21), 0, 8, DFLAGS, 497 PX30_CLKGATE_CON(6), 5, GFLAGS), 498 COMPOSITE_NODIV(SCLK_EMMC, "clk_emmc", mux_emmc_p, 499 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 500 PX30_CLKSEL_CON(21), 15, 1, MFLAGS, 501 PX30_CLKGATE_CON(6), 6, GFLAGS), 502 503 COMPOSITE(SCLK_SFC, "clk_sfc", mux_gpll_cpll_p, 0, 504 PX30_CLKSEL_CON(22), 7, 1, MFLAGS, 0, 7, DFLAGS, 505 PX30_CLKGATE_CON(6), 7, GFLAGS), 506 507 MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "clk_sdmmc", 508 PX30_SDMMC_CON0, 1), 509 MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "clk_sdmmc", 510 PX30_SDMMC_CON1, 1), 511 512 MMC(SCLK_SDIO_DRV, "sdio_drv", "clk_sdio", 513 PX30_SDIO_CON0, 1), 514 MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "clk_sdio", 515 PX30_SDIO_CON1, 1), 516 517 MMC(SCLK_EMMC_DRV, "emmc_drv", "clk_emmc", 518 PX30_EMMC_CON0, 1), 519 MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "clk_emmc", 520 PX30_EMMC_CON1, 1), 521 522 /* PD_SDCARD */ 523 GATE(0, "hclk_sdmmc_pre", "hclk_peri_pre", 0, 524 PX30_CLKGATE_CON(6), 12, GFLAGS), 525 COMPOSITE(SCLK_SDMMC_DIV, "clk_sdmmc_div", mux_gpll_cpll_npll_xin24m_p, 0, 526 PX30_CLKSEL_CON(16), 14, 2, MFLAGS, 0, 8, DFLAGS, 527 PX30_CLKGATE_CON(6), 13, GFLAGS), 528 COMPOSITE_DIV_OFFSET(SCLK_SDMMC_DIV50, "clk_sdmmc_div50", mux_gpll_cpll_npll_xin24m_p, 0, 529 PX30_CLKSEL_CON(16), 14, 2, MFLAGS, 530 PX30_CLKSEL_CON(17), 0, 8, DFLAGS, 531 PX30_CLKGATE_CON(6), 14, GFLAGS), 532 COMPOSITE_NODIV(SCLK_SDMMC, "clk_sdmmc", mux_sdmmc_p, 533 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 534 PX30_CLKSEL_CON(17), 15, 1, MFLAGS, 535 PX30_CLKGATE_CON(6), 15, GFLAGS), 536 537 /* PD_USB */ 538 GATE(HCLK_USB, "hclk_usb", "hclk_peri_pre", 0, 539 PX30_CLKGATE_CON(7), 2, GFLAGS), 540 GATE(SCLK_OTG_ADP, "clk_otg_adp", "clk_rtc32k_pmu", 0, 541 PX30_CLKGATE_CON(7), 3, GFLAGS), 542 543 /* PD_GMAC */ 544 COMPOSITE(SCLK_GMAC_SRC, "clk_gmac_src", mux_gpll_cpll_npll_p, 0, 545 PX30_CLKSEL_CON(22), 14, 2, MFLAGS, 8, 5, DFLAGS, 546 PX30_CLKGATE_CON(7), 11, GFLAGS), 547 MUX(SCLK_GMAC, "clk_gmac", mux_gmac_p, CLK_SET_RATE_PARENT, 548 PX30_CLKSEL_CON(23), 6, 1, MFLAGS), 549 GATE(SCLK_MAC_REF, "clk_mac_ref", "clk_gmac", 0, 550 PX30_CLKGATE_CON(7), 15, GFLAGS), 551 GATE(SCLK_GMAC_RX_TX, "clk_gmac_rx_tx", "clk_gmac", 0, 552 PX30_CLKGATE_CON(7), 13, GFLAGS), 553 FACTOR(0, "clk_gmac_rx_tx_div2", "clk_gmac_rx_tx", 0, 1, 2), 554 FACTOR(0, "clk_gmac_rx_tx_div20", "clk_gmac_rx_tx", 0, 1, 20), 555 MUX(SCLK_GMAC_RMII, "clk_gmac_rmii_sel", mux_gmac_rmii_sel_p, CLK_SET_RATE_PARENT, 556 PX30_CLKSEL_CON(23), 7, 1, MFLAGS), 557 558 GATE(0, "aclk_gmac_pre", "aclk_peri_pre", 0, 559 PX30_CLKGATE_CON(7), 10, GFLAGS), 560 COMPOSITE_NOMUX(0, "pclk_gmac_pre", "aclk_gmac_pre", 0, 561 PX30_CLKSEL_CON(23), 0, 4, DFLAGS, 562 PX30_CLKGATE_CON(7), 12, GFLAGS), 563 564 COMPOSITE(SCLK_MAC_OUT, "clk_mac_out", mux_gpll_cpll_npll_p, 0, 565 PX30_CLKSEL_CON(12), 14, 2, MFLAGS, 8, 5, DFLAGS, 566 PX30_CLKGATE_CON(8), 5, GFLAGS), 567 568 /* 569 * Clock-Architecture Diagram 8 570 */ 571 572 /* PD_BUS */ 573 COMPOSITE_NODIV(ACLK_BUS_SRC, "aclk_bus_src", mux_gpll_cpll_p, CLK_IGNORE_UNUSED, 574 PX30_CLKSEL_CON(23), 15, 1, MFLAGS, 575 PX30_CLKGATE_CON(8), 6, GFLAGS), 576 COMPOSITE_NOMUX(HCLK_BUS_PRE, "hclk_bus_pre", "aclk_bus_src", CLK_IGNORE_UNUSED, 577 PX30_CLKSEL_CON(24), 0, 5, DFLAGS, 578 PX30_CLKGATE_CON(8), 8, GFLAGS), 579 COMPOSITE_NOMUX(ACLK_BUS_PRE, "aclk_bus_pre", "aclk_bus_src", CLK_IGNORE_UNUSED, 580 PX30_CLKSEL_CON(23), 8, 5, DFLAGS, 581 PX30_CLKGATE_CON(8), 7, GFLAGS), 582 COMPOSITE_NOMUX(PCLK_BUS_PRE, "pclk_bus_pre", "aclk_bus_pre", CLK_IGNORE_UNUSED, 583 PX30_CLKSEL_CON(24), 8, 2, DFLAGS, 584 PX30_CLKGATE_CON(8), 9, GFLAGS), 585 GATE(0, "pclk_top_pre", "pclk_bus_pre", CLK_IGNORE_UNUSED, 586 PX30_CLKGATE_CON(8), 10, GFLAGS), 587 588 COMPOSITE(0, "clk_pdm_src", mux_gpll_xin24m_npll_p, 0, 589 PX30_CLKSEL_CON(26), 8, 2, MFLAGS, 0, 7, DFLAGS, 590 PX30_CLKGATE_CON(9), 9, GFLAGS), 591 COMPOSITE_FRACMUX(0, "clk_pdm_frac", "clk_pdm_src", CLK_SET_RATE_PARENT, 592 PX30_CLKSEL_CON(27), 0, 593 PX30_CLKGATE_CON(9), 10, GFLAGS, 594 &px30_pdm_fracmux), 595 GATE(SCLK_PDM, "clk_pdm", "clk_pdm_mux", CLK_SET_RATE_PARENT, 596 PX30_CLKGATE_CON(9), 11, GFLAGS), 597 598 COMPOSITE(0, "clk_i2s0_tx_src", mux_gpll_npll_p, 0, 599 PX30_CLKSEL_CON(28), 8, 1, MFLAGS, 0, 7, DFLAGS, 600 PX30_CLKGATE_CON(9), 12, GFLAGS), 601 COMPOSITE_FRACMUX(0, "clk_i2s0_tx_frac", "clk_i2s0_tx_src", CLK_SET_RATE_PARENT, 602 PX30_CLKSEL_CON(29), 0, 603 PX30_CLKGATE_CON(9), 13, GFLAGS, 604 &px30_i2s0_tx_fracmux), 605 COMPOSITE_NODIV(SCLK_I2S0_TX, "clk_i2s0_tx", mux_i2s0_tx_rx_p, CLK_SET_RATE_PARENT, 606 PX30_CLKSEL_CON(28), 12, 1, MFLAGS, 607 PX30_CLKGATE_CON(9), 14, GFLAGS), 608 COMPOSITE_NODIV(0, "clk_i2s0_tx_out_pre", mux_i2s0_tx_out_p, 0, 609 PX30_CLKSEL_CON(28), 14, 2, MFLAGS, 610 PX30_CLKGATE_CON(9), 15, GFLAGS), 611 GATE(SCLK_I2S0_TX_OUT, "clk_i2s0_tx_out", "clk_i2s0_tx_out_pre", CLK_SET_RATE_PARENT, 612 PX30_CLKGATE_CON(10), 8, CLK_GATE_HIWORD_MASK), 613 614 COMPOSITE(0, "clk_i2s0_rx_src", mux_gpll_npll_p, 0, 615 PX30_CLKSEL_CON(58), 8, 1, MFLAGS, 0, 7, DFLAGS, 616 PX30_CLKGATE_CON(17), 0, GFLAGS), 617 COMPOSITE_FRACMUX(0, "clk_i2s0_rx_frac", "clk_i2s0_rx_src", CLK_SET_RATE_PARENT, 618 PX30_CLKSEL_CON(59), 0, 619 PX30_CLKGATE_CON(17), 1, GFLAGS, 620 &px30_i2s0_rx_fracmux), 621 COMPOSITE_NODIV(SCLK_I2S0_RX, "clk_i2s0_rx", mux_i2s0_rx_tx_p, CLK_SET_RATE_PARENT, 622 PX30_CLKSEL_CON(58), 12, 1, MFLAGS, 623 PX30_CLKGATE_CON(17), 2, GFLAGS), 624 COMPOSITE_NODIV(0, "clk_i2s0_rx_out_pre", mux_i2s0_rx_out_p, 0, 625 PX30_CLKSEL_CON(58), 14, 2, MFLAGS, 626 PX30_CLKGATE_CON(17), 3, GFLAGS), 627 GATE(SCLK_I2S0_RX_OUT, "clk_i2s0_rx_out", "clk_i2s0_rx_out_pre", CLK_SET_RATE_PARENT, 628 PX30_CLKGATE_CON(10), 11, CLK_GATE_HIWORD_MASK), 629 630 COMPOSITE(0, "clk_i2s1_src", mux_gpll_npll_p, 0, 631 PX30_CLKSEL_CON(30), 8, 1, MFLAGS, 0, 7, DFLAGS, 632 PX30_CLKGATE_CON(10), 0, GFLAGS), 633 COMPOSITE_FRACMUX(0, "clk_i2s1_frac", "clk_i2s1_src", CLK_SET_RATE_PARENT, 634 PX30_CLKSEL_CON(31), 0, 635 PX30_CLKGATE_CON(10), 1, GFLAGS, 636 &px30_i2s1_fracmux), 637 GATE(SCLK_I2S1, "clk_i2s1", "clk_i2s1_mux", CLK_SET_RATE_PARENT, 638 PX30_CLKGATE_CON(10), 2, GFLAGS), 639 COMPOSITE_NODIV(0, "clk_i2s1_out_pre", mux_i2s1_out_p, 0, 640 PX30_CLKSEL_CON(30), 15, 1, MFLAGS, 641 PX30_CLKGATE_CON(10), 3, GFLAGS), 642 GATE(SCLK_I2S1_OUT, "clk_i2s1_out", "clk_i2s1_out_pre", CLK_SET_RATE_PARENT, 643 PX30_CLKGATE_CON(10), 9, CLK_GATE_HIWORD_MASK), 644 645 COMPOSITE(0, "clk_i2s2_src", mux_gpll_npll_p, 0, 646 PX30_CLKSEL_CON(32), 8, 1, MFLAGS, 0, 7, DFLAGS, 647 PX30_CLKGATE_CON(10), 4, GFLAGS), 648 COMPOSITE_FRACMUX(0, "clk_i2s2_frac", "clk_i2s2_src", CLK_SET_RATE_PARENT, 649 PX30_CLKSEL_CON(33), 0, 650 PX30_CLKGATE_CON(10), 5, GFLAGS, 651 &px30_i2s2_fracmux), 652 GATE(SCLK_I2S2, "clk_i2s2", "clk_i2s2_mux", CLK_SET_RATE_PARENT, 653 PX30_CLKGATE_CON(10), 6, GFLAGS), 654 COMPOSITE_NODIV(0, "clk_i2s2_out_pre", mux_i2s2_out_p, 0, 655 PX30_CLKSEL_CON(32), 15, 1, MFLAGS, 656 PX30_CLKGATE_CON(10), 7, GFLAGS), 657 GATE(SCLK_I2S2_OUT, "clk_i2s2_out", "clk_i2s2_out_pre", CLK_SET_RATE_PARENT, 658 PX30_CLKGATE_CON(10), 10, CLK_GATE_HIWORD_MASK), 659 660 COMPOSITE(SCLK_UART1_SRC, "clk_uart1_src", mux_uart_src_p, CLK_SET_RATE_NO_REPARENT, 661 PX30_CLKSEL_CON(34), 14, 2, MFLAGS, 0, 5, DFLAGS, 662 PX30_CLKGATE_CON(10), 12, GFLAGS), 663 COMPOSITE_NOMUX_HALFDIV(0, "clk_uart1_np5", "clk_uart1_src", 0, 664 PX30_CLKSEL_CON(35), 0, 5, DFLAGS, 665 PX30_CLKGATE_CON(10), 13, GFLAGS), 666 COMPOSITE_FRACMUX(0, "clk_uart1_frac", "clk_uart1_src", CLK_SET_RATE_PARENT, 667 PX30_CLKSEL_CON(36), 0, 668 PX30_CLKGATE_CON(10), 14, GFLAGS, 669 &px30_uart1_fracmux), 670 GATE(SCLK_UART1, "clk_uart1", "clk_uart1_mux", CLK_SET_RATE_PARENT, 671 PX30_CLKGATE_CON(10), 15, GFLAGS), 672 673 COMPOSITE(SCLK_UART2_SRC, "clk_uart2_src", mux_uart_src_p, 0, 674 PX30_CLKSEL_CON(37), 14, 2, MFLAGS, 0, 5, DFLAGS, 675 PX30_CLKGATE_CON(11), 0, GFLAGS), 676 COMPOSITE_NOMUX_HALFDIV(0, "clk_uart2_np5", "clk_uart2_src", 0, 677 PX30_CLKSEL_CON(38), 0, 5, DFLAGS, 678 PX30_CLKGATE_CON(11), 1, GFLAGS), 679 COMPOSITE_FRACMUX(0, "clk_uart2_frac", "clk_uart2_src", CLK_SET_RATE_PARENT, 680 PX30_CLKSEL_CON(39), 0, 681 PX30_CLKGATE_CON(11), 2, GFLAGS, 682 &px30_uart2_fracmux), 683 GATE(SCLK_UART2, "clk_uart2", "clk_uart2_mux", CLK_SET_RATE_PARENT, 684 PX30_CLKGATE_CON(11), 3, GFLAGS), 685 686 COMPOSITE(0, "clk_uart3_src", mux_uart_src_p, 0, 687 PX30_CLKSEL_CON(40), 14, 2, MFLAGS, 0, 5, DFLAGS, 688 PX30_CLKGATE_CON(11), 4, GFLAGS), 689 COMPOSITE_NOMUX_HALFDIV(0, "clk_uart3_np5", "clk_uart3_src", 0, 690 PX30_CLKSEL_CON(41), 0, 5, DFLAGS, 691 PX30_CLKGATE_CON(11), 5, GFLAGS), 692 COMPOSITE_FRACMUX(0, "clk_uart3_frac", "clk_uart3_src", CLK_SET_RATE_PARENT, 693 PX30_CLKSEL_CON(42), 0, 694 PX30_CLKGATE_CON(11), 6, GFLAGS, 695 &px30_uart3_fracmux), 696 GATE(SCLK_UART3, "clk_uart3", "clk_uart3_mux", CLK_SET_RATE_PARENT, 697 PX30_CLKGATE_CON(11), 7, GFLAGS), 698 699 COMPOSITE(0, "clk_uart4_src", mux_uart_src_p, 0, 700 PX30_CLKSEL_CON(43), 14, 2, MFLAGS, 0, 5, DFLAGS, 701 PX30_CLKGATE_CON(11), 8, GFLAGS), 702 COMPOSITE_NOMUX_HALFDIV(0, "clk_uart4_np5", "clk_uart4_src", 0, 703 PX30_CLKSEL_CON(44), 0, 5, DFLAGS, 704 PX30_CLKGATE_CON(11), 9, GFLAGS), 705 COMPOSITE_FRACMUX(0, "clk_uart4_frac", "clk_uart4_src", CLK_SET_RATE_PARENT, 706 PX30_CLKSEL_CON(45), 0, 707 PX30_CLKGATE_CON(11), 10, GFLAGS, 708 &px30_uart4_fracmux), 709 GATE(SCLK_UART4, "clk_uart4", "clk_uart4_mux", CLK_SET_RATE_PARENT, 710 PX30_CLKGATE_CON(11), 11, GFLAGS), 711 712 COMPOSITE(0, "clk_uart5_src", mux_uart_src_p, 0, 713 PX30_CLKSEL_CON(46), 14, 2, MFLAGS, 0, 5, DFLAGS, 714 PX30_CLKGATE_CON(11), 12, GFLAGS), 715 COMPOSITE_NOMUX_HALFDIV(0, "clk_uart5_np5", "clk_uart5_src", 0, 716 PX30_CLKSEL_CON(47), 0, 5, DFLAGS, 717 PX30_CLKGATE_CON(11), 13, GFLAGS), 718 COMPOSITE_FRACMUX(0, "clk_uart5_frac", "clk_uart5_src", CLK_SET_RATE_PARENT, 719 PX30_CLKSEL_CON(48), 0, 720 PX30_CLKGATE_CON(11), 14, GFLAGS, 721 &px30_uart5_fracmux), 722 GATE(SCLK_UART5, "clk_uart5", "clk_uart5_mux", CLK_SET_RATE_PARENT, 723 PX30_CLKGATE_CON(11), 15, GFLAGS), 724 725 COMPOSITE(SCLK_I2C0, "clk_i2c0", mux_gpll_xin24m_p, 0, 726 PX30_CLKSEL_CON(49), 7, 1, MFLAGS, 0, 7, DFLAGS, 727 PX30_CLKGATE_CON(12), 0, GFLAGS), 728 COMPOSITE(SCLK_I2C1, "clk_i2c1", mux_gpll_xin24m_p, 0, 729 PX30_CLKSEL_CON(49), 15, 1, MFLAGS, 8, 7, DFLAGS, 730 PX30_CLKGATE_CON(12), 1, GFLAGS), 731 COMPOSITE(SCLK_I2C2, "clk_i2c2", mux_gpll_xin24m_p, 0, 732 PX30_CLKSEL_CON(50), 7, 1, MFLAGS, 0, 7, DFLAGS, 733 PX30_CLKGATE_CON(12), 2, GFLAGS), 734 COMPOSITE(SCLK_I2C3, "clk_i2c3", mux_gpll_xin24m_p, 0, 735 PX30_CLKSEL_CON(50), 15, 1, MFLAGS, 8, 7, DFLAGS, 736 PX30_CLKGATE_CON(12), 3, GFLAGS), 737 COMPOSITE(SCLK_PWM0, "clk_pwm0", mux_gpll_xin24m_p, 0, 738 PX30_CLKSEL_CON(52), 7, 1, MFLAGS, 0, 7, DFLAGS, 739 PX30_CLKGATE_CON(12), 5, GFLAGS), 740 COMPOSITE(SCLK_PWM1, "clk_pwm1", mux_gpll_xin24m_p, 0, 741 PX30_CLKSEL_CON(52), 15, 1, MFLAGS, 8, 7, DFLAGS, 742 PX30_CLKGATE_CON(12), 6, GFLAGS), 743 COMPOSITE(SCLK_SPI0, "clk_spi0", mux_gpll_xin24m_p, 0, 744 PX30_CLKSEL_CON(53), 7, 1, MFLAGS, 0, 7, DFLAGS, 745 PX30_CLKGATE_CON(12), 7, GFLAGS), 746 COMPOSITE(SCLK_SPI1, "clk_spi1", mux_gpll_xin24m_p, 0, 747 PX30_CLKSEL_CON(53), 15, 1, MFLAGS, 8, 7, DFLAGS, 748 PX30_CLKGATE_CON(12), 8, GFLAGS), 749 750 GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0, 751 PX30_CLKGATE_CON(13), 0, GFLAGS), 752 GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0, 753 PX30_CLKGATE_CON(13), 1, GFLAGS), 754 GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0, 755 PX30_CLKGATE_CON(13), 2, GFLAGS), 756 GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 0, 757 PX30_CLKGATE_CON(13), 3, GFLAGS), 758 GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 0, 759 PX30_CLKGATE_CON(13), 4, GFLAGS), 760 GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 0, 761 PX30_CLKGATE_CON(13), 5, GFLAGS), 762 763 COMPOSITE_NOMUX(SCLK_TSADC, "clk_tsadc", "xin24m", 0, 764 PX30_CLKSEL_CON(54), 0, 11, DFLAGS, 765 PX30_CLKGATE_CON(12), 9, GFLAGS), 766 COMPOSITE_NOMUX(SCLK_SARADC, "clk_saradc", "xin24m", 0, 767 PX30_CLKSEL_CON(55), 0, 11, DFLAGS, 768 PX30_CLKGATE_CON(12), 10, GFLAGS), 769 COMPOSITE_NOMUX(SCLK_OTP, "clk_otp", "xin24m", 0, 770 PX30_CLKSEL_CON(56), 0, 3, DFLAGS, 771 PX30_CLKGATE_CON(12), 11, GFLAGS), 772 COMPOSITE_NOMUX(SCLK_OTP_USR, "clk_otp_usr", "clk_otp", 0, 773 PX30_CLKSEL_CON(56), 4, 2, DFLAGS, 774 PX30_CLKGATE_CON(13), 6, GFLAGS), 775 776 GATE(0, "clk_cpu_boost", "xin24m", CLK_IGNORE_UNUSED, 777 PX30_CLKGATE_CON(12), 12, GFLAGS), 778 779 /* PD_CRYPTO */ 780 GATE(0, "aclk_crypto_pre", "aclk_bus_pre", 0, 781 PX30_CLKGATE_CON(8), 12, GFLAGS), 782 GATE(0, "hclk_crypto_pre", "hclk_bus_pre", 0, 783 PX30_CLKGATE_CON(8), 13, GFLAGS), 784 COMPOSITE(SCLK_CRYPTO, "clk_crypto", mux_gpll_cpll_npll_p, 0, 785 PX30_CLKSEL_CON(25), 6, 2, MFLAGS, 0, 5, DFLAGS, 786 PX30_CLKGATE_CON(8), 14, GFLAGS), 787 COMPOSITE(SCLK_CRYPTO_APK, "clk_crypto_apk", mux_gpll_cpll_npll_p, 0, 788 PX30_CLKSEL_CON(25), 14, 2, MFLAGS, 8, 5, DFLAGS, 789 PX30_CLKGATE_CON(8), 15, GFLAGS), 790 791 /* 792 * Clock-Architecture Diagram 9 793 */ 794 795 /* PD_BUS_TOP */ 796 GATE(0, "pclk_top_niu", "pclk_top_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(16), 0, GFLAGS), 797 GATE(0, "pclk_top_cru", "pclk_top_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(16), 1, GFLAGS), 798 GATE(PCLK_OTP_PHY, "pclk_otp_phy", "pclk_top_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(16), 2, GFLAGS), 799 GATE(0, "pclk_ddrphy", "pclk_top_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(16), 3, GFLAGS), 800 GATE(PCLK_MIPIDSIPHY, "pclk_mipidsiphy", "pclk_top_pre", 0, PX30_CLKGATE_CON(16), 4, GFLAGS), 801 GATE(PCLK_MIPICSIPHY, "pclk_mipicsiphy", "pclk_top_pre", 0, PX30_CLKGATE_CON(16), 5, GFLAGS), 802 GATE(PCLK_USB_GRF, "pclk_usb_grf", "pclk_top_pre", 0, PX30_CLKGATE_CON(16), 6, GFLAGS), 803 GATE(0, "pclk_cpu_hoost", "pclk_top_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(16), 7, GFLAGS), 804 805 /* PD_VI */ 806 GATE(0, "aclk_vi_niu", "aclk_vi_pre", 0, PX30_CLKGATE_CON(4), 15, GFLAGS), 807 GATE(ACLK_CIF, "aclk_cif", "aclk_vi_pre", 0, PX30_CLKGATE_CON(5), 1, GFLAGS), 808 GATE(ACLK_ISP, "aclk_isp", "aclk_vi_pre", 0, PX30_CLKGATE_CON(5), 3, GFLAGS), 809 GATE(0, "hclk_vi_niu", "hclk_vi_pre", 0, PX30_CLKGATE_CON(5), 0, GFLAGS), 810 GATE(HCLK_CIF, "hclk_cif", "hclk_vi_pre", 0, PX30_CLKGATE_CON(5), 2, GFLAGS), 811 GATE(HCLK_ISP, "hclk_isp", "hclk_vi_pre", 0, PX30_CLKGATE_CON(5), 4, GFLAGS), 812 813 /* PD_VO */ 814 GATE(0, "aclk_vo_niu", "aclk_vo_pre", 0, PX30_CLKGATE_CON(3), 0, GFLAGS), 815 GATE(ACLK_VOPB, "aclk_vopb", "aclk_vo_pre", 0, PX30_CLKGATE_CON(3), 3, GFLAGS), 816 GATE(ACLK_RGA, "aclk_rga", "aclk_vo_pre", 0, PX30_CLKGATE_CON(3), 7, GFLAGS), 817 GATE(ACLK_VOPL, "aclk_vopl", "aclk_vo_pre", 0, PX30_CLKGATE_CON(3), 5, GFLAGS), 818 819 GATE(0, "hclk_vo_niu", "hclk_vo_pre", 0, PX30_CLKGATE_CON(3), 1, GFLAGS), 820 GATE(HCLK_VOPB, "hclk_vopb", "hclk_vo_pre", 0, PX30_CLKGATE_CON(3), 4, GFLAGS), 821 GATE(HCLK_RGA, "hclk_rga", "hclk_vo_pre", 0, PX30_CLKGATE_CON(3), 8, GFLAGS), 822 GATE(HCLK_VOPL, "hclk_vopl", "hclk_vo_pre", 0, PX30_CLKGATE_CON(3), 6, GFLAGS), 823 824 GATE(0, "pclk_vo_niu", "pclk_vo_pre", 0, PX30_CLKGATE_CON(3), 2, GFLAGS), 825 GATE(PCLK_MIPI_DSI, "pclk_mipi_dsi", "pclk_vo_pre", 0, PX30_CLKGATE_CON(3), 9, GFLAGS), 826 827 /* PD_BUS */ 828 GATE(0, "aclk_bus_niu", "aclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13), 8, GFLAGS), 829 GATE(0, "aclk_intmem", "aclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13), 11, GFLAGS), 830 GATE(ACLK_GIC, "aclk_gic", "aclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13), 12, GFLAGS), 831 GATE(ACLK_DCF, "aclk_dcf", "aclk_bus_pre", 0, PX30_CLKGATE_CON(13), 15, GFLAGS), 832 833 /* aclk_dmac is controlled by sgrf_soc_con1[11]. */ 834 SGRF_GATE(ACLK_DMAC, "aclk_dmac", "aclk_bus_pre"), 835 836 GATE(0, "hclk_bus_niu", "hclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13), 9, GFLAGS), 837 GATE(0, "hclk_rom", "hclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13), 14, GFLAGS), 838 GATE(HCLK_PDM, "hclk_pdm", "hclk_bus_pre", 0, PX30_CLKGATE_CON(14), 1, GFLAGS), 839 GATE(HCLK_I2S0, "hclk_i2s0", "hclk_bus_pre", 0, PX30_CLKGATE_CON(14), 2, GFLAGS), 840 GATE(HCLK_I2S1, "hclk_i2s1", "hclk_bus_pre", 0, PX30_CLKGATE_CON(14), 3, GFLAGS), 841 GATE(HCLK_I2S2, "hclk_i2s2", "hclk_bus_pre", 0, PX30_CLKGATE_CON(14), 4, GFLAGS), 842 843 GATE(0, "pclk_bus_niu", "pclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13), 10, GFLAGS), 844 GATE(PCLK_DCF, "pclk_dcf", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 0, GFLAGS), 845 GATE(PCLK_UART1, "pclk_uart1", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 5, GFLAGS), 846 GATE(PCLK_UART2, "pclk_uart2", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 6, GFLAGS), 847 GATE(PCLK_UART3, "pclk_uart3", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 7, GFLAGS), 848 GATE(PCLK_UART4, "pclk_uart4", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 8, GFLAGS), 849 GATE(PCLK_UART5, "pclk_uart5", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 9, GFLAGS), 850 GATE(PCLK_I2C0, "pclk_i2c0", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 10, GFLAGS), 851 GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 11, GFLAGS), 852 GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 12, GFLAGS), 853 GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 13, GFLAGS), 854 GATE(PCLK_I2C4, "pclk_i2c4", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 14, GFLAGS), 855 GATE(PCLK_PWM0, "pclk_pwm0", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 15, GFLAGS), 856 GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 0, GFLAGS), 857 GATE(PCLK_SPI0, "pclk_spi0", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 1, GFLAGS), 858 GATE(PCLK_SPI1, "pclk_spi1", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 2, GFLAGS), 859 GATE(PCLK_SARADC, "pclk_saradc", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 3, GFLAGS), 860 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 4, GFLAGS), 861 GATE(PCLK_TIMER, "pclk_timer", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 5, GFLAGS), 862 GATE(PCLK_OTP_NS, "pclk_otp_ns", "pclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(15), 6, GFLAGS), 863 GATE(PCLK_WDT_NS, "pclk_wdt_ns", "pclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(15), 7, GFLAGS), 864 GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 8, GFLAGS), 865 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 9, GFLAGS), 866 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 10, GFLAGS), 867 GATE(0, "pclk_grf", "pclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(15), 11, GFLAGS), 868 GATE(0, "pclk_sgrf", "pclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(15), 12, GFLAGS), 869 870 /* PD_VPU */ 871 GATE(0, "hclk_vpu_niu", "hclk_vpu_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(4), 7, GFLAGS), 872 GATE(HCLK_VPU, "hclk_vpu", "hclk_vpu_pre", 0, PX30_CLKGATE_CON(4), 6, GFLAGS), 873 GATE(0, "aclk_vpu_niu", "aclk_vpu_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(4), 5, GFLAGS), 874 GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_pre", 0, PX30_CLKGATE_CON(4), 4, GFLAGS), 875 876 /* PD_CRYPTO */ 877 GATE(0, "hclk_crypto_niu", "hclk_crypto_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(9), 3, GFLAGS), 878 GATE(HCLK_CRYPTO, "hclk_crypto", "hclk_crypto_pre", 0, PX30_CLKGATE_CON(9), 5, GFLAGS), 879 GATE(0, "aclk_crypto_niu", "aclk_crypto_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(9), 2, GFLAGS), 880 GATE(ACLK_CRYPTO, "aclk_crypto", "aclk_crypto_pre", 0, PX30_CLKGATE_CON(9), 4, GFLAGS), 881 882 /* PD_SDCARD */ 883 GATE(0, "hclk_sdmmc_niu", "hclk_sdmmc_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(7), 0, GFLAGS), 884 GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_sdmmc_pre", 0, PX30_CLKGATE_CON(7), 1, GFLAGS), 885 886 /* PD_PERI */ 887 GATE(0, "aclk_peri_niu", "aclk_peri_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(5), 9, GFLAGS), 888 889 /* PD_MMC_NAND */ 890 GATE(HCLK_NANDC, "hclk_nandc", "hclk_mmc_nand", 0, PX30_CLKGATE_CON(5), 15, GFLAGS), 891 GATE(0, "hclk_mmc_nand_niu", "hclk_mmc_nand", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(6), 8, GFLAGS), 892 GATE(HCLK_SDIO, "hclk_sdio", "hclk_mmc_nand", 0, PX30_CLKGATE_CON(6), 9, GFLAGS), 893 GATE(HCLK_EMMC, "hclk_emmc", "hclk_mmc_nand", 0, PX30_CLKGATE_CON(6), 10, GFLAGS), 894 GATE(HCLK_SFC, "hclk_sfc", "hclk_mmc_nand", 0, PX30_CLKGATE_CON(6), 11, GFLAGS), 895 896 /* PD_USB */ 897 GATE(0, "hclk_usb_niu", "hclk_usb", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(7), 4, GFLAGS), 898 GATE(HCLK_OTG, "hclk_otg", "hclk_usb", 0, PX30_CLKGATE_CON(7), 5, GFLAGS), 899 GATE(HCLK_HOST, "hclk_host", "hclk_usb", 0, PX30_CLKGATE_CON(7), 6, GFLAGS), 900 GATE(HCLK_HOST_ARB, "hclk_host_arb", "hclk_usb", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(7), 8, GFLAGS), 901 902 /* PD_GMAC */ 903 GATE(0, "aclk_gmac_niu", "aclk_gmac_pre", CLK_IGNORE_UNUSED, 904 PX30_CLKGATE_CON(8), 0, GFLAGS), 905 GATE(ACLK_GMAC, "aclk_gmac", "aclk_gmac_pre", 0, 906 PX30_CLKGATE_CON(8), 2, GFLAGS), 907 GATE(0, "pclk_gmac_niu", "pclk_gmac_pre", CLK_IGNORE_UNUSED, 908 PX30_CLKGATE_CON(8), 1, GFLAGS), 909 GATE(PCLK_GMAC, "pclk_gmac", "pclk_gmac_pre", 0, 910 PX30_CLKGATE_CON(8), 3, GFLAGS), 911}; 912 913static struct rockchip_clk_branch px30_clk_pmu_branches[] __initdata = { 914 /* 915 * Clock-Architecture Diagram 2 916 */ 917 918 COMPOSITE_FRACMUX(0, "clk_rtc32k_frac", "xin24m", CLK_IGNORE_UNUSED, 919 PX30_PMU_CLKSEL_CON(1), 0, 920 PX30_PMU_CLKGATE_CON(0), 13, GFLAGS, 921 &px30_rtc32k_pmu_fracmux), 922 923 COMPOSITE_NOMUX(XIN24M_DIV, "xin24m_div", "xin24m", CLK_IGNORE_UNUSED, 924 PX30_PMU_CLKSEL_CON(0), 8, 5, DFLAGS, 925 PX30_PMU_CLKGATE_CON(0), 12, GFLAGS), 926 927 COMPOSITE_NOMUX(0, "clk_wifi_pmu_src", "gpll", 0, 928 PX30_PMU_CLKSEL_CON(2), 8, 6, DFLAGS, 929 PX30_PMU_CLKGATE_CON(0), 14, GFLAGS), 930 COMPOSITE_NODIV(SCLK_WIFI_PMU, "clk_wifi_pmu", mux_wifi_pmu_p, CLK_SET_RATE_PARENT, 931 PX30_PMU_CLKSEL_CON(2), 15, 1, MFLAGS, 932 PX30_PMU_CLKGATE_CON(0), 15, GFLAGS), 933 934 COMPOSITE(0, "clk_uart0_pmu_src", mux_uart_src_p, 0, 935 PX30_PMU_CLKSEL_CON(3), 14, 2, MFLAGS, 0, 5, DFLAGS, 936 PX30_PMU_CLKGATE_CON(1), 0, GFLAGS), 937 COMPOSITE_NOMUX_HALFDIV(0, "clk_uart0_np5", "clk_uart0_pmu_src", 0, 938 PX30_PMU_CLKSEL_CON(4), 0, 5, DFLAGS, 939 PX30_PMU_CLKGATE_CON(1), 1, GFLAGS), 940 COMPOSITE_FRACMUX(0, "clk_uart0_frac", "clk_uart0_pmu_src", CLK_SET_RATE_PARENT, 941 PX30_PMU_CLKSEL_CON(5), 0, 942 PX30_PMU_CLKGATE_CON(1), 2, GFLAGS, 943 &px30_uart0_pmu_fracmux), 944 GATE(SCLK_UART0_PMU, "clk_uart0_pmu", "clk_uart0_pmu_mux", CLK_SET_RATE_PARENT, 945 PX30_PMU_CLKGATE_CON(1), 3, GFLAGS), 946 947 GATE(SCLK_PVTM_PMU, "clk_pvtm_pmu", "xin24m", 0, 948 PX30_PMU_CLKGATE_CON(1), 4, GFLAGS), 949 950 COMPOSITE_NOMUX(PCLK_PMU_PRE, "pclk_pmu_pre", "gpll", 0, 951 PX30_PMU_CLKSEL_CON(0), 0, 5, DFLAGS, 952 PX30_PMU_CLKGATE_CON(0), 0, GFLAGS), 953 954 COMPOSITE_NOMUX(SCLK_REF24M_PMU, "clk_ref24m_pmu", "gpll", 0, 955 PX30_PMU_CLKSEL_CON(2), 0, 6, DFLAGS, 956 PX30_PMU_CLKGATE_CON(1), 8, GFLAGS), 957 COMPOSITE_NODIV(SCLK_USBPHY_REF, "clk_usbphy_ref", mux_usbphy_ref_p, CLK_SET_RATE_PARENT, 958 PX30_PMU_CLKSEL_CON(2), 6, 1, MFLAGS, 959 PX30_PMU_CLKGATE_CON(1), 9, GFLAGS), 960 COMPOSITE_NODIV(SCLK_MIPIDSIPHY_REF, "clk_mipidsiphy_ref", mux_mipidsiphy_ref_p, CLK_SET_RATE_PARENT, 961 PX30_PMU_CLKSEL_CON(2), 7, 1, MFLAGS, 962 PX30_PMU_CLKGATE_CON(1), 10, GFLAGS), 963 964 /* 965 * Clock-Architecture Diagram 9 966 */ 967 968 /* PD_PMU */ 969 GATE(0, "pclk_pmu_niu", "pclk_pmu_pre", CLK_IGNORE_UNUSED, PX30_PMU_CLKGATE_CON(0), 1, GFLAGS), 970 GATE(0, "pclk_pmu_sgrf", "pclk_pmu_pre", CLK_IGNORE_UNUSED, PX30_PMU_CLKGATE_CON(0), 2, GFLAGS), 971 GATE(0, "pclk_pmu_grf", "pclk_pmu_pre", CLK_IGNORE_UNUSED, PX30_PMU_CLKGATE_CON(0), 3, GFLAGS), 972 GATE(0, "pclk_pmu", "pclk_pmu_pre", CLK_IGNORE_UNUSED, PX30_PMU_CLKGATE_CON(0), 4, GFLAGS), 973 GATE(0, "pclk_pmu_mem", "pclk_pmu_pre", CLK_IGNORE_UNUSED, PX30_PMU_CLKGATE_CON(0), 5, GFLAGS), 974 GATE(PCLK_GPIO0_PMU, "pclk_gpio0_pmu", "pclk_pmu_pre", 0, PX30_PMU_CLKGATE_CON(0), 6, GFLAGS), 975 GATE(PCLK_UART0_PMU, "pclk_uart0_pmu", "pclk_pmu_pre", 0, PX30_PMU_CLKGATE_CON(0), 7, GFLAGS), 976 GATE(0, "pclk_cru_pmu", "pclk_pmu_pre", CLK_IGNORE_UNUSED, PX30_PMU_CLKGATE_CON(0), 8, GFLAGS), 977}; 978 979static const char *const px30_cru_critical_clocks[] __initconst = { 980 "aclk_bus_pre", 981 "pclk_bus_pre", 982 "hclk_bus_pre", 983 "aclk_peri_pre", 984 "hclk_peri_pre", 985 "aclk_gpu_niu", 986 "pclk_top_pre", 987 "pclk_pmu_pre", 988 "hclk_usb_niu", 989 "pclk_vo_niu", 990 "aclk_vo_niu", 991 "hclk_vo_niu", 992 "aclk_vi_niu", 993 "hclk_vi_niu", 994 "pll_npll", 995 "usb480m", 996 "clk_uart2", 997 "pclk_uart2", 998 "pclk_usb_grf", 999}; 1000 1001static void __init px30_clk_init(struct device_node *np) 1002{ 1003 struct rockchip_clk_provider *ctx; 1004 void __iomem *reg_base; 1005 1006 reg_base = of_iomap(np, 0); 1007 if (!reg_base) { 1008 pr_err("%s: could not map cru region\n", __func__); 1009 return; 1010 } 1011 1012 ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS); 1013 if (IS_ERR(ctx)) { 1014 pr_err("%s: rockchip clk init failed\n", __func__); 1015 iounmap(reg_base); 1016 return; 1017 } 1018 1019 rockchip_clk_register_plls(ctx, px30_pll_clks, 1020 ARRAY_SIZE(px30_pll_clks), 1021 PX30_GRF_SOC_STATUS0); 1022 rockchip_clk_register_branches(ctx, px30_clk_branches, 1023 ARRAY_SIZE(px30_clk_branches)); 1024 1025 rockchip_clk_register_armclk(ctx, ARMCLK, "armclk", 1026 mux_armclk_p, ARRAY_SIZE(mux_armclk_p), 1027 &px30_cpuclk_data, px30_cpuclk_rates, 1028 ARRAY_SIZE(px30_cpuclk_rates)); 1029 1030 rockchip_clk_protect_critical(px30_cru_critical_clocks, 1031 ARRAY_SIZE(px30_cru_critical_clocks)); 1032 1033 rockchip_register_softrst(np, 12, reg_base + PX30_SOFTRST_CON(0), 1034 ROCKCHIP_SOFTRST_HIWORD_MASK); 1035 1036 rockchip_register_restart_notifier(ctx, PX30_GLB_SRST_FST, NULL); 1037 1038 rockchip_clk_of_add_provider(np, ctx); 1039} 1040CLK_OF_DECLARE(px30_cru, "rockchip,px30-cru", px30_clk_init); 1041 1042static void __init px30_pmu_clk_init(struct device_node *np) 1043{ 1044 struct rockchip_clk_provider *ctx; 1045 void __iomem *reg_base; 1046 1047 reg_base = of_iomap(np, 0); 1048 if (!reg_base) { 1049 pr_err("%s: could not map cru pmu region\n", __func__); 1050 return; 1051 } 1052 1053 ctx = rockchip_clk_init(np, reg_base, CLKPMU_NR_CLKS); 1054 if (IS_ERR(ctx)) { 1055 pr_err("%s: rockchip pmu clk init failed\n", __func__); 1056 return; 1057 } 1058 1059 rockchip_clk_register_plls(ctx, px30_pmu_pll_clks, 1060 ARRAY_SIZE(px30_pmu_pll_clks), PX30_GRF_SOC_STATUS0); 1061 1062 rockchip_clk_register_branches(ctx, px30_clk_pmu_branches, 1063 ARRAY_SIZE(px30_clk_pmu_branches)); 1064 1065 rockchip_clk_of_add_provider(np, ctx); 1066} 1067CLK_OF_DECLARE(px30_cru_pmu, "rockchip,px30-pmucru", px30_pmu_clk_init); 1068