18c2ecf20Sopenharmony_ci# SPDX-License-Identifier: GPL-2.0
28c2ecf20Sopenharmony_ci#
38c2ecf20Sopenharmony_ci# Rockchip Clock specific Makefile
48c2ecf20Sopenharmony_ci#
58c2ecf20Sopenharmony_ci
68c2ecf20Sopenharmony_ciobj-$(CONFIG_COMMON_CLK_ROCKCHIP) += clk-rockchip.o
78c2ecf20Sopenharmony_ci
88c2ecf20Sopenharmony_ciclk-rockchip-y += clk.o
98c2ecf20Sopenharmony_ciclk-rockchip-y += clk-pll.o
108c2ecf20Sopenharmony_ciclk-rockchip-y += clk-cpu.o
118c2ecf20Sopenharmony_ciclk-rockchip-y += clk-half-divider.o
128c2ecf20Sopenharmony_ciclk-rockchip-y += clk-inverter.o
138c2ecf20Sopenharmony_ciclk-rockchip-y += clk-mmc-phase.o
148c2ecf20Sopenharmony_ciclk-rockchip-y += clk-muxgrf.o
158c2ecf20Sopenharmony_ciclk-rockchip-y += clk-ddr.o
168c2ecf20Sopenharmony_ciclk-rockchip-$(CONFIG_RESET_CONTROLLER) += softrst.o
178c2ecf20Sopenharmony_ci
188c2ecf20Sopenharmony_ciobj-$(CONFIG_CLK_PX30)          += clk-px30.o
198c2ecf20Sopenharmony_ciobj-$(CONFIG_CLK_RV110X)        += clk-rv1108.o
208c2ecf20Sopenharmony_ciobj-$(CONFIG_CLK_RK3036)        += clk-rk3036.o
218c2ecf20Sopenharmony_ciobj-$(CONFIG_CLK_RK312X)        += clk-rk3128.o
228c2ecf20Sopenharmony_ciobj-$(CONFIG_CLK_RK3188)        += clk-rk3188.o
238c2ecf20Sopenharmony_ciobj-$(CONFIG_CLK_RK322X)        += clk-rk3228.o
248c2ecf20Sopenharmony_ciobj-$(CONFIG_CLK_RK3288)        += clk-rk3288.o
258c2ecf20Sopenharmony_ciobj-$(CONFIG_CLK_RK3308)        += clk-rk3308.o
268c2ecf20Sopenharmony_ciobj-$(CONFIG_CLK_RK3328)        += clk-rk3328.o
278c2ecf20Sopenharmony_ciobj-$(CONFIG_CLK_RK3368)        += clk-rk3368.o
288c2ecf20Sopenharmony_ciobj-$(CONFIG_CLK_RK3399)        += clk-rk3399.o
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