18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0 */ 28c2ecf20Sopenharmony_ci/* 38c2ecf20Sopenharmony_ci * R-Car Gen2 Clock Pulse Generator 48c2ecf20Sopenharmony_ci * 58c2ecf20Sopenharmony_ci * Copyright (C) 2016 Cogent Embedded Inc. 68c2ecf20Sopenharmony_ci */ 78c2ecf20Sopenharmony_ci 88c2ecf20Sopenharmony_ci#ifndef __CLK_RENESAS_RCAR_GEN2_CPG_H__ 98c2ecf20Sopenharmony_ci#define __CLK_RENESAS_RCAR_GEN2_CPG_H__ 108c2ecf20Sopenharmony_ci 118c2ecf20Sopenharmony_cienum rcar_gen2_clk_types { 128c2ecf20Sopenharmony_ci CLK_TYPE_GEN2_MAIN = CLK_TYPE_CUSTOM, 138c2ecf20Sopenharmony_ci CLK_TYPE_GEN2_PLL0, 148c2ecf20Sopenharmony_ci CLK_TYPE_GEN2_PLL1, 158c2ecf20Sopenharmony_ci CLK_TYPE_GEN2_PLL3, 168c2ecf20Sopenharmony_ci CLK_TYPE_GEN2_Z, 178c2ecf20Sopenharmony_ci CLK_TYPE_GEN2_LB, 188c2ecf20Sopenharmony_ci CLK_TYPE_GEN2_ADSP, 198c2ecf20Sopenharmony_ci CLK_TYPE_GEN2_SDH, 208c2ecf20Sopenharmony_ci CLK_TYPE_GEN2_SD0, 218c2ecf20Sopenharmony_ci CLK_TYPE_GEN2_SD1, 228c2ecf20Sopenharmony_ci CLK_TYPE_GEN2_QSPI, 238c2ecf20Sopenharmony_ci CLK_TYPE_GEN2_RCAN, 248c2ecf20Sopenharmony_ci}; 258c2ecf20Sopenharmony_ci 268c2ecf20Sopenharmony_cistruct rcar_gen2_cpg_pll_config { 278c2ecf20Sopenharmony_ci u8 extal_div; 288c2ecf20Sopenharmony_ci u8 pll1_mult; 298c2ecf20Sopenharmony_ci u8 pll3_mult; 308c2ecf20Sopenharmony_ci u8 pll0_mult; /* leave as zero if PLL0CR exists */ 318c2ecf20Sopenharmony_ci}; 328c2ecf20Sopenharmony_ci 338c2ecf20Sopenharmony_cistruct clk *rcar_gen2_cpg_clk_register(struct device *dev, 348c2ecf20Sopenharmony_ci const struct cpg_core_clk *core, const struct cpg_mssr_info *info, 358c2ecf20Sopenharmony_ci struct clk **clks, void __iomem *base, 368c2ecf20Sopenharmony_ci struct raw_notifier_head *notifiers); 378c2ecf20Sopenharmony_ciint rcar_gen2_cpg_init(const struct rcar_gen2_cpg_pll_config *config, 388c2ecf20Sopenharmony_ci unsigned int pll0_div, u32 mode); 398c2ecf20Sopenharmony_ci 408c2ecf20Sopenharmony_ci#endif 41