1// SPDX-License-Identifier: GPL-2.0 2/* 3 * R-Car Gen2 Clock Pulse Generator 4 * 5 * Copyright (C) 2016 Cogent Embedded Inc. 6 */ 7 8#include <linux/bug.h> 9#include <linux/clk.h> 10#include <linux/clk-provider.h> 11#include <linux/device.h> 12#include <linux/err.h> 13#include <linux/init.h> 14#include <linux/io.h> 15#include <linux/slab.h> 16#include <linux/sys_soc.h> 17 18#include "renesas-cpg-mssr.h" 19#include "rcar-gen2-cpg.h" 20 21#define CPG_FRQCRB 0x0004 22#define CPG_FRQCRB_KICK BIT(31) 23#define CPG_SDCKCR 0x0074 24#define CPG_PLL0CR 0x00d8 25#define CPG_PLL0CR_STC_SHIFT 24 26#define CPG_PLL0CR_STC_MASK (0x7f << CPG_PLL0CR_STC_SHIFT) 27#define CPG_FRQCRC 0x00e0 28#define CPG_FRQCRC_ZFC_SHIFT 8 29#define CPG_FRQCRC_ZFC_MASK (0x1f << CPG_FRQCRC_ZFC_SHIFT) 30#define CPG_ADSPCKCR 0x025c 31#define CPG_RCANCKCR 0x0270 32 33static spinlock_t cpg_lock; 34 35/* 36 * Z Clock 37 * 38 * Traits of this clock: 39 * prepare - clk_prepare only ensures that parents are prepared 40 * enable - clk_enable only ensures that parents are enabled 41 * rate - rate is adjustable. clk->rate = parent->rate * mult / 32 42 * parent - fixed parent. No clk_set_parent support 43 */ 44 45struct cpg_z_clk { 46 struct clk_hw hw; 47 void __iomem *reg; 48 void __iomem *kick_reg; 49}; 50 51#define to_z_clk(_hw) container_of(_hw, struct cpg_z_clk, hw) 52 53static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw, 54 unsigned long parent_rate) 55{ 56 struct cpg_z_clk *zclk = to_z_clk(hw); 57 unsigned int mult; 58 unsigned int val; 59 60 val = (readl(zclk->reg) & CPG_FRQCRC_ZFC_MASK) >> CPG_FRQCRC_ZFC_SHIFT; 61 mult = 32 - val; 62 63 return div_u64((u64)parent_rate * mult, 32); 64} 65 66static int cpg_z_clk_determine_rate(struct clk_hw *hw, 67 struct clk_rate_request *req) 68{ 69 unsigned long prate = req->best_parent_rate; 70 unsigned int min_mult, max_mult, mult; 71 72 min_mult = max(div64_ul(req->min_rate * 32ULL, prate), 1ULL); 73 max_mult = min(div64_ul(req->max_rate * 32ULL, prate), 32ULL); 74 if (max_mult < min_mult) 75 return -EINVAL; 76 77 mult = div64_ul(req->rate * 32ULL, prate); 78 mult = clamp(mult, min_mult, max_mult); 79 80 req->rate = div_u64((u64)prate * mult, 32); 81 return 0; 82} 83 84static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate, 85 unsigned long parent_rate) 86{ 87 struct cpg_z_clk *zclk = to_z_clk(hw); 88 unsigned int mult; 89 u32 val, kick; 90 unsigned int i; 91 92 mult = div64_ul(rate * 32ULL, parent_rate); 93 mult = clamp(mult, 1U, 32U); 94 95 if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK) 96 return -EBUSY; 97 98 val = readl(zclk->reg); 99 val &= ~CPG_FRQCRC_ZFC_MASK; 100 val |= (32 - mult) << CPG_FRQCRC_ZFC_SHIFT; 101 writel(val, zclk->reg); 102 103 /* 104 * Set KICK bit in FRQCRB to update hardware setting and wait for 105 * clock change completion. 106 */ 107 kick = readl(zclk->kick_reg); 108 kick |= CPG_FRQCRB_KICK; 109 writel(kick, zclk->kick_reg); 110 111 /* 112 * Note: There is no HW information about the worst case latency. 113 * 114 * Using experimental measurements, it seems that no more than 115 * ~10 iterations are needed, independently of the CPU rate. 116 * Since this value might be dependent on external xtal rate, pll1 117 * rate or even the other emulation clocks rate, use 1000 as a 118 * "super" safe value. 119 */ 120 for (i = 1000; i; i--) { 121 if (!(readl(zclk->kick_reg) & CPG_FRQCRB_KICK)) 122 return 0; 123 124 cpu_relax(); 125 } 126 127 return -ETIMEDOUT; 128} 129 130static const struct clk_ops cpg_z_clk_ops = { 131 .recalc_rate = cpg_z_clk_recalc_rate, 132 .determine_rate = cpg_z_clk_determine_rate, 133 .set_rate = cpg_z_clk_set_rate, 134}; 135 136static struct clk * __init cpg_z_clk_register(const char *name, 137 const char *parent_name, 138 void __iomem *base) 139{ 140 struct clk_init_data init; 141 struct cpg_z_clk *zclk; 142 struct clk *clk; 143 144 zclk = kzalloc(sizeof(*zclk), GFP_KERNEL); 145 if (!zclk) 146 return ERR_PTR(-ENOMEM); 147 148 init.name = name; 149 init.ops = &cpg_z_clk_ops; 150 init.flags = 0; 151 init.parent_names = &parent_name; 152 init.num_parents = 1; 153 154 zclk->reg = base + CPG_FRQCRC; 155 zclk->kick_reg = base + CPG_FRQCRB; 156 zclk->hw.init = &init; 157 158 clk = clk_register(NULL, &zclk->hw); 159 if (IS_ERR(clk)) 160 kfree(zclk); 161 162 return clk; 163} 164 165static struct clk * __init cpg_rcan_clk_register(const char *name, 166 const char *parent_name, 167 void __iomem *base) 168{ 169 struct clk_fixed_factor *fixed; 170 struct clk_gate *gate; 171 struct clk *clk; 172 173 fixed = kzalloc(sizeof(*fixed), GFP_KERNEL); 174 if (!fixed) 175 return ERR_PTR(-ENOMEM); 176 177 fixed->mult = 1; 178 fixed->div = 6; 179 180 gate = kzalloc(sizeof(*gate), GFP_KERNEL); 181 if (!gate) { 182 kfree(fixed); 183 return ERR_PTR(-ENOMEM); 184 } 185 186 gate->reg = base + CPG_RCANCKCR; 187 gate->bit_idx = 8; 188 gate->flags = CLK_GATE_SET_TO_DISABLE; 189 gate->lock = &cpg_lock; 190 191 clk = clk_register_composite(NULL, name, &parent_name, 1, NULL, NULL, 192 &fixed->hw, &clk_fixed_factor_ops, 193 &gate->hw, &clk_gate_ops, 0); 194 if (IS_ERR(clk)) { 195 kfree(gate); 196 kfree(fixed); 197 } 198 199 return clk; 200} 201 202/* ADSP divisors */ 203static const struct clk_div_table cpg_adsp_div_table[] = { 204 { 1, 3 }, { 2, 4 }, { 3, 6 }, { 4, 8 }, 205 { 5, 12 }, { 6, 16 }, { 7, 18 }, { 8, 24 }, 206 { 10, 36 }, { 11, 48 }, { 0, 0 }, 207}; 208 209static struct clk * __init cpg_adsp_clk_register(const char *name, 210 const char *parent_name, 211 void __iomem *base) 212{ 213 struct clk_divider *div; 214 struct clk_gate *gate; 215 struct clk *clk; 216 217 div = kzalloc(sizeof(*div), GFP_KERNEL); 218 if (!div) 219 return ERR_PTR(-ENOMEM); 220 221 div->reg = base + CPG_ADSPCKCR; 222 div->width = 4; 223 div->table = cpg_adsp_div_table; 224 div->lock = &cpg_lock; 225 226 gate = kzalloc(sizeof(*gate), GFP_KERNEL); 227 if (!gate) { 228 kfree(div); 229 return ERR_PTR(-ENOMEM); 230 } 231 232 gate->reg = base + CPG_ADSPCKCR; 233 gate->bit_idx = 8; 234 gate->flags = CLK_GATE_SET_TO_DISABLE; 235 gate->lock = &cpg_lock; 236 237 clk = clk_register_composite(NULL, name, &parent_name, 1, NULL, NULL, 238 &div->hw, &clk_divider_ops, 239 &gate->hw, &clk_gate_ops, 0); 240 if (IS_ERR(clk)) { 241 kfree(gate); 242 kfree(div); 243 } 244 245 return clk; 246} 247 248/* SDHI divisors */ 249static const struct clk_div_table cpg_sdh_div_table[] = { 250 { 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 }, 251 { 4, 8 }, { 5, 12 }, { 6, 16 }, { 7, 18 }, 252 { 8, 24 }, { 10, 36 }, { 11, 48 }, { 0, 0 }, 253}; 254 255static const struct clk_div_table cpg_sd01_div_table[] = { 256 { 4, 8 }, { 5, 12 }, { 6, 16 }, { 7, 18 }, 257 { 8, 24 }, { 10, 36 }, { 11, 48 }, { 12, 10 }, 258 { 0, 0 }, 259}; 260 261static const struct rcar_gen2_cpg_pll_config *cpg_pll_config __initdata; 262static unsigned int cpg_pll0_div __initdata; 263static u32 cpg_mode __initdata; 264static u32 cpg_quirks __initdata; 265 266#define SD_SKIP_FIRST BIT(0) /* Skip first clock in SD table */ 267 268static const struct soc_device_attribute cpg_quirks_match[] __initconst = { 269 { 270 .soc_id = "r8a77470", 271 .data = (void *)SD_SKIP_FIRST, 272 }, 273 { /* sentinel */ } 274}; 275 276struct clk * __init rcar_gen2_cpg_clk_register(struct device *dev, 277 const struct cpg_core_clk *core, const struct cpg_mssr_info *info, 278 struct clk **clks, void __iomem *base, 279 struct raw_notifier_head *notifiers) 280{ 281 const struct clk_div_table *table = NULL; 282 const struct clk *parent; 283 const char *parent_name; 284 unsigned int mult = 1; 285 unsigned int div = 1; 286 unsigned int shift; 287 288 parent = clks[core->parent]; 289 if (IS_ERR(parent)) 290 return ERR_CAST(parent); 291 292 parent_name = __clk_get_name(parent); 293 294 switch (core->type) { 295 /* R-Car Gen2 */ 296 case CLK_TYPE_GEN2_MAIN: 297 div = cpg_pll_config->extal_div; 298 break; 299 300 case CLK_TYPE_GEN2_PLL0: 301 /* 302 * PLL0 is a configurable multiplier clock except on R-Car 303 * V2H/E2. Register the PLL0 clock as a fixed factor clock for 304 * now as there's no generic multiplier clock implementation and 305 * we currently have no need to change the multiplier value. 306 */ 307 mult = cpg_pll_config->pll0_mult; 308 div = cpg_pll0_div; 309 if (!mult) { 310 u32 pll0cr = readl(base + CPG_PLL0CR); 311 312 mult = (((pll0cr & CPG_PLL0CR_STC_MASK) >> 313 CPG_PLL0CR_STC_SHIFT) + 1) * 2; 314 } 315 break; 316 317 case CLK_TYPE_GEN2_PLL1: 318 mult = cpg_pll_config->pll1_mult / 2; 319 break; 320 321 case CLK_TYPE_GEN2_PLL3: 322 mult = cpg_pll_config->pll3_mult; 323 break; 324 325 case CLK_TYPE_GEN2_Z: 326 return cpg_z_clk_register(core->name, parent_name, base); 327 328 case CLK_TYPE_GEN2_LB: 329 div = cpg_mode & BIT(18) ? 36 : 24; 330 break; 331 332 case CLK_TYPE_GEN2_ADSP: 333 return cpg_adsp_clk_register(core->name, parent_name, base); 334 335 case CLK_TYPE_GEN2_SDH: 336 table = cpg_sdh_div_table; 337 shift = 8; 338 break; 339 340 case CLK_TYPE_GEN2_SD0: 341 table = cpg_sd01_div_table; 342 if (cpg_quirks & SD_SKIP_FIRST) 343 table++; 344 345 shift = 4; 346 break; 347 348 case CLK_TYPE_GEN2_SD1: 349 table = cpg_sd01_div_table; 350 if (cpg_quirks & SD_SKIP_FIRST) 351 table++; 352 353 shift = 0; 354 break; 355 356 case CLK_TYPE_GEN2_QSPI: 357 div = (cpg_mode & (BIT(3) | BIT(2) | BIT(1))) == BIT(2) ? 358 8 : 10; 359 break; 360 361 case CLK_TYPE_GEN2_RCAN: 362 return cpg_rcan_clk_register(core->name, parent_name, base); 363 364 default: 365 return ERR_PTR(-EINVAL); 366 } 367 368 if (!table) 369 return clk_register_fixed_factor(NULL, core->name, parent_name, 370 0, mult, div); 371 else 372 return clk_register_divider_table(NULL, core->name, 373 parent_name, 0, 374 base + CPG_SDCKCR, shift, 4, 375 0, table, &cpg_lock); 376} 377 378int __init rcar_gen2_cpg_init(const struct rcar_gen2_cpg_pll_config *config, 379 unsigned int pll0_div, u32 mode) 380{ 381 const struct soc_device_attribute *attr; 382 383 cpg_pll_config = config; 384 cpg_pll0_div = pll0_div; 385 cpg_mode = mode; 386 attr = soc_device_match(cpg_quirks_match); 387 if (attr) 388 cpg_quirks = (uintptr_t)attr->data; 389 pr_debug("%s: mode = 0x%x quirks = 0x%x\n", __func__, mode, cpg_quirks); 390 391 spin_lock_init(&cpg_lock); 392 393 return 0; 394} 395