1// SPDX-License-Identifier: GPL-2.0 2/* 3 * r8a779a0 Clock Pulse Generator / Module Standby and Software Reset 4 * 5 * Copyright (C) 2020 Renesas Electronics Corp. 6 * 7 * Based on r8a7795-cpg-mssr.c 8 * 9 * Copyright (C) 2015 Glider bvba 10 * Copyright (C) 2015 Renesas Electronics Corp. 11 */ 12 13#include <linux/bug.h> 14#include <linux/bitfield.h> 15#include <linux/clk.h> 16#include <linux/clk-provider.h> 17#include <linux/device.h> 18#include <linux/err.h> 19#include <linux/init.h> 20#include <linux/io.h> 21#include <linux/kernel.h> 22#include <linux/pm.h> 23#include <linux/slab.h> 24#include <linux/soc/renesas/rcar-rst.h> 25 26#include <dt-bindings/clock/r8a779a0-cpg-mssr.h> 27 28#include "renesas-cpg-mssr.h" 29 30enum rcar_r8a779a0_clk_types { 31 CLK_TYPE_R8A779A0_MAIN = CLK_TYPE_CUSTOM, 32 CLK_TYPE_R8A779A0_PLL1, 33 CLK_TYPE_R8A779A0_PLL2X_3X, /* PLL[23][01] */ 34 CLK_TYPE_R8A779A0_PLL5, 35 CLK_TYPE_R8A779A0_MDSEL, /* Select parent/divider using mode pin */ 36 CLK_TYPE_R8A779A0_OSC, /* OSC EXTAL predivider and fixed divider */ 37}; 38 39struct rcar_r8a779a0_cpg_pll_config { 40 u8 extal_div; 41 u8 pll1_mult; 42 u8 pll1_div; 43 u8 pll5_mult; 44 u8 pll5_div; 45 u8 osc_prediv; 46}; 47 48enum clk_ids { 49 /* Core Clock Outputs exported to DT */ 50 LAST_DT_CORE_CLK = R8A779A0_CLK_OSC, 51 52 /* External Input Clocks */ 53 CLK_EXTAL, 54 CLK_EXTALR, 55 56 /* Internal Core Clocks */ 57 CLK_MAIN, 58 CLK_PLL1, 59 CLK_PLL20, 60 CLK_PLL21, 61 CLK_PLL30, 62 CLK_PLL31, 63 CLK_PLL5, 64 CLK_PLL1_DIV2, 65 CLK_PLL20_DIV2, 66 CLK_PLL21_DIV2, 67 CLK_PLL30_DIV2, 68 CLK_PLL31_DIV2, 69 CLK_PLL5_DIV2, 70 CLK_PLL5_DIV4, 71 CLK_S1, 72 CLK_S3, 73 CLK_SDSRC, 74 CLK_RPCSRC, 75 CLK_OCO, 76 77 /* Module Clocks */ 78 MOD_CLK_BASE 79}; 80 81#define DEF_PLL(_name, _id, _offset) \ 82 DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_PLL2X_3X, CLK_MAIN, \ 83 .offset = _offset) 84 85#define DEF_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \ 86 DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_MDSEL, \ 87 (_parent0) << 16 | (_parent1), \ 88 .div = (_div0) << 16 | (_div1), .offset = _md) 89 90#define DEF_OSC(_name, _id, _parent, _div) \ 91 DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_OSC, _parent, .div = _div) 92 93static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = { 94 /* External Clock Inputs */ 95 DEF_INPUT("extal", CLK_EXTAL), 96 DEF_INPUT("extalr", CLK_EXTALR), 97 98 /* Internal Core Clocks */ 99 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_R8A779A0_MAIN, CLK_EXTAL), 100 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_R8A779A0_PLL1, CLK_MAIN), 101 DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_R8A779A0_PLL5, CLK_MAIN), 102 DEF_PLL(".pll20", CLK_PLL20, 0x0834), 103 DEF_PLL(".pll21", CLK_PLL21, 0x0838), 104 DEF_PLL(".pll30", CLK_PLL30, 0x083c), 105 DEF_PLL(".pll31", CLK_PLL31, 0x0840), 106 107 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1), 108 DEF_FIXED(".pll20_div2", CLK_PLL20_DIV2, CLK_PLL20, 2, 1), 109 DEF_FIXED(".pll21_div2", CLK_PLL21_DIV2, CLK_PLL21, 2, 1), 110 DEF_FIXED(".pll30_div2", CLK_PLL30_DIV2, CLK_PLL30, 2, 1), 111 DEF_FIXED(".pll31_div2", CLK_PLL31_DIV2, CLK_PLL31, 2, 1), 112 DEF_FIXED(".pll5_div2", CLK_PLL5_DIV2, CLK_PLL5, 2, 1), 113 DEF_FIXED(".pll5_div4", CLK_PLL5_DIV4, CLK_PLL5_DIV2, 2, 1), 114 DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 2, 1), 115 DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 4, 1), 116 DEF_RATE(".oco", CLK_OCO, 32768), 117 118 /* Core Clock Outputs */ 119 DEF_FIXED("zx", R8A779A0_CLK_ZX, CLK_PLL20_DIV2, 2, 1), 120 DEF_FIXED("s1d1", R8A779A0_CLK_S1D1, CLK_S1, 1, 1), 121 DEF_FIXED("s1d2", R8A779A0_CLK_S1D2, CLK_S1, 2, 1), 122 DEF_FIXED("s1d4", R8A779A0_CLK_S1D4, CLK_S1, 4, 1), 123 DEF_FIXED("s1d8", R8A779A0_CLK_S1D8, CLK_S1, 8, 1), 124 DEF_FIXED("s1d12", R8A779A0_CLK_S1D12, CLK_S1, 12, 1), 125 DEF_FIXED("s3d1", R8A779A0_CLK_S3D1, CLK_S3, 1, 1), 126 DEF_FIXED("s3d2", R8A779A0_CLK_S3D2, CLK_S3, 2, 1), 127 DEF_FIXED("s3d4", R8A779A0_CLK_S3D4, CLK_S3, 4, 1), 128 DEF_FIXED("zs", R8A779A0_CLK_ZS, CLK_PLL1_DIV2, 4, 1), 129 DEF_FIXED("zt", R8A779A0_CLK_ZT, CLK_PLL1_DIV2, 2, 1), 130 DEF_FIXED("ztr", R8A779A0_CLK_ZTR, CLK_PLL1_DIV2, 2, 1), 131 DEF_FIXED("zr", R8A779A0_CLK_ZR, CLK_PLL1_DIV2, 1, 1), 132 DEF_FIXED("dsi", R8A779A0_CLK_DSI, CLK_PLL5_DIV4, 1, 1), 133 DEF_FIXED("cnndsp", R8A779A0_CLK_CNNDSP, CLK_PLL5_DIV4, 1, 1), 134 DEF_FIXED("vip", R8A779A0_CLK_VIP, CLK_PLL5, 5, 1), 135 DEF_FIXED("adgh", R8A779A0_CLK_ADGH, CLK_PLL5_DIV4, 1, 1), 136 DEF_FIXED("icu", R8A779A0_CLK_ICU, CLK_PLL5_DIV4, 2, 1), 137 DEF_FIXED("icud2", R8A779A0_CLK_ICUD2, CLK_PLL5_DIV4, 4, 1), 138 DEF_FIXED("vcbus", R8A779A0_CLK_VCBUS, CLK_PLL5_DIV4, 1, 1), 139 DEF_FIXED("cbfusa", R8A779A0_CLK_CBFUSA, CLK_EXTAL, 2, 1), 140 141 DEF_DIV6P1("mso", R8A779A0_CLK_MSO, CLK_PLL5_DIV4, 0x87c), 142 DEF_DIV6P1("canfd", R8A779A0_CLK_CANFD, CLK_PLL5_DIV4, 0x878), 143 DEF_DIV6P1("csi0", R8A779A0_CLK_CSI0, CLK_PLL5_DIV4, 0x880), 144 145 DEF_OSC("osc", R8A779A0_CLK_OSC, CLK_EXTAL, 8), 146 DEF_MDSEL("r", R8A779A0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1), 147}; 148 149static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = { 150 DEF_MOD("scif0", 702, R8A779A0_CLK_S1D8), 151 DEF_MOD("scif1", 703, R8A779A0_CLK_S1D8), 152 DEF_MOD("scif3", 704, R8A779A0_CLK_S1D8), 153 DEF_MOD("scif4", 705, R8A779A0_CLK_S1D8), 154}; 155 156static spinlock_t cpg_lock; 157 158static const struct rcar_r8a779a0_cpg_pll_config *cpg_pll_config __initdata; 159static unsigned int cpg_clk_extalr __initdata; 160static u32 cpg_mode __initdata; 161 162struct clk * __init rcar_r8a779a0_cpg_clk_register(struct device *dev, 163 const struct cpg_core_clk *core, const struct cpg_mssr_info *info, 164 struct clk **clks, void __iomem *base, 165 struct raw_notifier_head *notifiers) 166{ 167 const struct clk *parent; 168 unsigned int mult = 1; 169 unsigned int div = 1; 170 u32 value; 171 172 parent = clks[core->parent & 0xffff]; /* some types use high bits */ 173 if (IS_ERR(parent)) 174 return ERR_CAST(parent); 175 176 switch (core->type) { 177 case CLK_TYPE_R8A779A0_MAIN: 178 div = cpg_pll_config->extal_div; 179 break; 180 181 case CLK_TYPE_R8A779A0_PLL1: 182 mult = cpg_pll_config->pll1_mult; 183 div = cpg_pll_config->pll1_div; 184 break; 185 186 case CLK_TYPE_R8A779A0_PLL2X_3X: 187 value = readl(base + core->offset); 188 mult = (((value >> 24) & 0x7f) + 1) * 2; 189 break; 190 191 case CLK_TYPE_R8A779A0_PLL5: 192 mult = cpg_pll_config->pll5_mult; 193 div = cpg_pll_config->pll5_div; 194 break; 195 196 case CLK_TYPE_R8A779A0_MDSEL: 197 /* 198 * Clock selectable between two parents and two fixed dividers 199 * using a mode pin 200 */ 201 if (cpg_mode & BIT(core->offset)) { 202 div = core->div & 0xffff; 203 } else { 204 parent = clks[core->parent >> 16]; 205 if (IS_ERR(parent)) 206 return ERR_CAST(parent); 207 div = core->div >> 16; 208 } 209 mult = 1; 210 break; 211 212 case CLK_TYPE_R8A779A0_OSC: 213 /* 214 * Clock combining OSC EXTAL predivider and a fixed divider 215 */ 216 div = cpg_pll_config->osc_prediv * core->div; 217 break; 218 219 default: 220 return ERR_PTR(-EINVAL); 221 } 222 223 return clk_register_fixed_factor(NULL, core->name, 224 __clk_get_name(parent), 0, mult, div); 225} 226 227/* 228 * CPG Clock Data 229 */ 230/* 231 * MD EXTAL PLL1 PLL20 PLL30 PLL4 PLL5 OSC 232 * 14 13 (MHz) 21 31 233 * -------------------------------------------------------- 234 * 0 0 16.66 x 1 x128 x216 x128 x144 x192 /16 235 * 0 1 20 x 1 x106 x180 x106 x120 x160 /19 236 * 1 0 Prohibited setting 237 * 1 1 33.33 / 2 x128 x216 x128 x144 x192 /32 238 */ 239#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \ 240 (((md) & BIT(13)) >> 13)) 241 242static const struct rcar_r8a779a0_cpg_pll_config cpg_pll_configs[4] = { 243 /* EXTAL div PLL1 mult/div PLL5 mult/div OSC prediv */ 244 { 1, 128, 1, 192, 1, 16, }, 245 { 1, 106, 1, 160, 1, 19, }, 246 { 0, 0, 0, 0, 0, 0, }, 247 { 2, 128, 1, 192, 1, 32, }, 248}; 249 250static int __init r8a779a0_cpg_mssr_init(struct device *dev) 251{ 252 int error; 253 254 error = rcar_rst_read_mode_pins(&cpg_mode); 255 if (error) 256 return error; 257 258 cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)]; 259 cpg_clk_extalr = CLK_EXTALR; 260 spin_lock_init(&cpg_lock); 261 262 return 0; 263} 264 265const struct cpg_mssr_info r8a779a0_cpg_mssr_info __initconst = { 266 /* Core Clocks */ 267 .core_clks = r8a779a0_core_clks, 268 .num_core_clks = ARRAY_SIZE(r8a779a0_core_clks), 269 .last_dt_core_clk = LAST_DT_CORE_CLK, 270 .num_total_core_clks = MOD_CLK_BASE, 271 272 /* Module Clocks */ 273 .mod_clks = r8a779a0_mod_clks, 274 .num_mod_clks = ARRAY_SIZE(r8a779a0_mod_clks), 275 .num_hw_mod_clks = 15 * 32, 276 277 /* Callbacks */ 278 .init = r8a779a0_cpg_mssr_init, 279 .cpg_clk_register = rcar_r8a779a0_cpg_clk_register, 280 281 .reg_layout = CLK_REG_LAYOUT_RCAR_V3U, 282}; 283