1// SPDX-License-Identifier: GPL-2.0
2/*
3 * r8a7779 Core CPG Clocks
4 *
5 * Copyright (C) 2013, 2014 Horms Solutions Ltd.
6 *
7 * Contact: Simon Horman <horms@verge.net.au>
8 */
9
10#include <linux/clk-provider.h>
11#include <linux/clk/renesas.h>
12#include <linux/init.h>
13#include <linux/kernel.h>
14#include <linux/of.h>
15#include <linux/of_address.h>
16#include <linux/slab.h>
17#include <linux/spinlock.h>
18#include <linux/soc/renesas/rcar-rst.h>
19
20#include <dt-bindings/clock/r8a7779-clock.h>
21
22#define CPG_NUM_CLOCKS			(R8A7779_CLK_OUT + 1)
23
24struct r8a7779_cpg {
25	struct clk_onecell_data data;
26	spinlock_t lock;
27	void __iomem *reg;
28};
29
30/* -----------------------------------------------------------------------------
31 * CPG Clock Data
32 */
33
34/*
35 *		MD1 = 1			MD1 = 0
36 *		(PLLA = 1500)		(PLLA = 1600)
37 *		(MHz)			(MHz)
38 *------------------------------------------------+--------------------
39 * clkz		1000   (2/3)		800   (1/2)
40 * clkzs	 250   (1/6)		200   (1/8)
41 * clki		 750   (1/2)		800   (1/2)
42 * clks		 250   (1/6)		200   (1/8)
43 * clks1	 125   (1/12)		100   (1/16)
44 * clks3	 187.5 (1/8)		200   (1/8)
45 * clks4	  93.7 (1/16)		100   (1/16)
46 * clkp		  62.5 (1/24)		 50   (1/32)
47 * clkg		  62.5 (1/24)		 66.6 (1/24)
48 * clkb, CLKOUT
49 * (MD2 = 0)	  62.5 (1/24)		 66.6 (1/24)
50 * (MD2 = 1)	  41.6 (1/36)		 50   (1/32)
51 */
52
53#define CPG_CLK_CONFIG_INDEX(md)	(((md) & (BIT(2)|BIT(1))) >> 1)
54
55struct cpg_clk_config {
56	unsigned int z_mult;
57	unsigned int z_div;
58	unsigned int zs_and_s_div;
59	unsigned int s1_div;
60	unsigned int p_div;
61	unsigned int b_and_out_div;
62};
63
64static const struct cpg_clk_config cpg_clk_configs[4] __initconst = {
65	{ 1, 2, 8, 16, 32, 24 },
66	{ 2, 3, 6, 12, 24, 24 },
67	{ 1, 2, 8, 16, 32, 32 },
68	{ 2, 3, 6, 12, 24, 36 },
69};
70
71/*
72 *   MD		PLLA Ratio
73 * 12 11
74 *------------------------
75 * 0  0		x42
76 * 0  1		x48
77 * 1  0		x56
78 * 1  1		x64
79 */
80
81#define CPG_PLLA_MULT_INDEX(md)	(((md) & (BIT(12)|BIT(11))) >> 11)
82
83static const unsigned int cpg_plla_mult[4] __initconst = { 42, 48, 56, 64 };
84
85/* -----------------------------------------------------------------------------
86 * Initialization
87 */
88
89static struct clk * __init
90r8a7779_cpg_register_clock(struct device_node *np, struct r8a7779_cpg *cpg,
91			   const struct cpg_clk_config *config,
92			   unsigned int plla_mult, const char *name)
93{
94	const char *parent_name = "plla";
95	unsigned int mult = 1;
96	unsigned int div = 1;
97
98	if (!strcmp(name, "plla")) {
99		parent_name = of_clk_get_parent_name(np, 0);
100		mult = plla_mult;
101	} else if (!strcmp(name, "z")) {
102		div = config->z_div;
103		mult = config->z_mult;
104	} else if (!strcmp(name, "zs") || !strcmp(name, "s")) {
105		div = config->zs_and_s_div;
106	} else if (!strcmp(name, "s1")) {
107		div = config->s1_div;
108	} else if (!strcmp(name, "p")) {
109		div = config->p_div;
110	} else if (!strcmp(name, "b") || !strcmp(name, "out")) {
111		div = config->b_and_out_div;
112	} else {
113		return ERR_PTR(-EINVAL);
114	}
115
116	return clk_register_fixed_factor(NULL, name, parent_name, 0, mult, div);
117}
118
119static void __init r8a7779_cpg_clocks_init(struct device_node *np)
120{
121	const struct cpg_clk_config *config;
122	struct r8a7779_cpg *cpg;
123	struct clk **clks;
124	unsigned int i, plla_mult;
125	int num_clks;
126	u32 mode;
127
128	if (rcar_rst_read_mode_pins(&mode))
129		return;
130
131	num_clks = of_property_count_strings(np, "clock-output-names");
132	if (num_clks < 0) {
133		pr_err("%s: failed to count clocks\n", __func__);
134		return;
135	}
136
137	cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
138	clks = kcalloc(CPG_NUM_CLOCKS, sizeof(*clks), GFP_KERNEL);
139	if (cpg == NULL || clks == NULL) {
140		/* We're leaking memory on purpose, there's no point in cleaning
141		 * up as the system won't boot anyway.
142		 */
143		return;
144	}
145
146	spin_lock_init(&cpg->lock);
147
148	cpg->data.clks = clks;
149	cpg->data.clk_num = num_clks;
150
151	config = &cpg_clk_configs[CPG_CLK_CONFIG_INDEX(mode)];
152	plla_mult = cpg_plla_mult[CPG_PLLA_MULT_INDEX(mode)];
153
154	for (i = 0; i < num_clks; ++i) {
155		const char *name;
156		struct clk *clk;
157
158		of_property_read_string_index(np, "clock-output-names", i,
159					      &name);
160
161		clk = r8a7779_cpg_register_clock(np, cpg, config,
162						 plla_mult, name);
163		if (IS_ERR(clk))
164			pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
165			       __func__, np, name, PTR_ERR(clk));
166		else
167			cpg->data.clks[i] = clk;
168	}
169
170	of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
171
172	cpg_mstp_add_clk_domain(np);
173}
174CLK_OF_DECLARE(r8a7779_cpg_clks, "renesas,r8a7779-cpg-clocks",
175	       r8a7779_cpg_clocks_init);
176