1// SPDX-License-Identifier: GPL-2.0
2/*
3 * r8a7790 Common Clock Framework support
4 *
5 * Copyright (C) 2013  Renesas Solutions Corp.
6 *
7 * Contact: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
8 */
9
10#include <linux/clk-provider.h>
11#include <linux/init.h>
12#include <linux/io.h>
13#include <linux/kernel.h>
14#include <linux/notifier.h>
15#include <linux/of.h>
16#include <linux/of_address.h>
17#include <linux/pm.h>
18#include <linux/slab.h>
19
20#include "clk-div6.h"
21
22#define CPG_DIV6_CKSTP		BIT(8)
23#define CPG_DIV6_DIV(d)		((d) & 0x3f)
24#define CPG_DIV6_DIV_MASK	0x3f
25
26/**
27 * struct div6_clock - CPG 6 bit divider clock
28 * @hw: handle between common and hardware-specific interfaces
29 * @reg: IO-remapped register
30 * @div: divisor value (1-64)
31 * @src_shift: Shift to access the register bits to select the parent clock
32 * @src_width: Number of register bits to select the parent clock (may be 0)
33 * @nb: Notifier block to save/restore clock state for system resume
34 * @parents: Array to map from valid parent clocks indices to hardware indices
35 */
36struct div6_clock {
37	struct clk_hw hw;
38	void __iomem *reg;
39	unsigned int div;
40	u32 src_shift;
41	u32 src_width;
42	struct notifier_block nb;
43	u8 parents[];
44};
45
46#define to_div6_clock(_hw) container_of(_hw, struct div6_clock, hw)
47
48static int cpg_div6_clock_enable(struct clk_hw *hw)
49{
50	struct div6_clock *clock = to_div6_clock(hw);
51	u32 val;
52
53	val = (readl(clock->reg) & ~(CPG_DIV6_DIV_MASK | CPG_DIV6_CKSTP))
54	    | CPG_DIV6_DIV(clock->div - 1);
55	writel(val, clock->reg);
56
57	return 0;
58}
59
60static void cpg_div6_clock_disable(struct clk_hw *hw)
61{
62	struct div6_clock *clock = to_div6_clock(hw);
63	u32 val;
64
65	val = readl(clock->reg);
66	val |= CPG_DIV6_CKSTP;
67	/*
68	 * DIV6 clocks require the divisor field to be non-zero when stopping
69	 * the clock. However, some clocks (e.g. ZB on sh73a0) fail to be
70	 * re-enabled later if the divisor field is changed when stopping the
71	 * clock
72	 */
73	if (!(val & CPG_DIV6_DIV_MASK))
74		val |= CPG_DIV6_DIV_MASK;
75	writel(val, clock->reg);
76}
77
78static int cpg_div6_clock_is_enabled(struct clk_hw *hw)
79{
80	struct div6_clock *clock = to_div6_clock(hw);
81
82	return !(readl(clock->reg) & CPG_DIV6_CKSTP);
83}
84
85static unsigned long cpg_div6_clock_recalc_rate(struct clk_hw *hw,
86						unsigned long parent_rate)
87{
88	struct div6_clock *clock = to_div6_clock(hw);
89
90	return parent_rate / clock->div;
91}
92
93static unsigned int cpg_div6_clock_calc_div(unsigned long rate,
94					    unsigned long parent_rate)
95{
96	unsigned int div;
97
98	if (!rate)
99		rate = 1;
100
101	div = DIV_ROUND_CLOSEST(parent_rate, rate);
102	return clamp_t(unsigned int, div, 1, 64);
103}
104
105static long cpg_div6_clock_round_rate(struct clk_hw *hw, unsigned long rate,
106				      unsigned long *parent_rate)
107{
108	unsigned int div = cpg_div6_clock_calc_div(rate, *parent_rate);
109
110	return *parent_rate / div;
111}
112
113static int cpg_div6_clock_set_rate(struct clk_hw *hw, unsigned long rate,
114				   unsigned long parent_rate)
115{
116	struct div6_clock *clock = to_div6_clock(hw);
117	unsigned int div = cpg_div6_clock_calc_div(rate, parent_rate);
118	u32 val;
119
120	clock->div = div;
121
122	val = readl(clock->reg) & ~CPG_DIV6_DIV_MASK;
123	/* Only program the new divisor if the clock isn't stopped. */
124	if (!(val & CPG_DIV6_CKSTP))
125		writel(val | CPG_DIV6_DIV(clock->div - 1), clock->reg);
126
127	return 0;
128}
129
130static u8 cpg_div6_clock_get_parent(struct clk_hw *hw)
131{
132	struct div6_clock *clock = to_div6_clock(hw);
133	unsigned int i;
134	u8 hw_index;
135
136	if (clock->src_width == 0)
137		return 0;
138
139	hw_index = (readl(clock->reg) >> clock->src_shift) &
140		   (BIT(clock->src_width) - 1);
141	for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
142		if (clock->parents[i] == hw_index)
143			return i;
144	}
145
146	pr_err("%s: %s DIV6 clock set to invalid parent %u\n",
147	       __func__, clk_hw_get_name(hw), hw_index);
148	return 0;
149}
150
151static int cpg_div6_clock_set_parent(struct clk_hw *hw, u8 index)
152{
153	struct div6_clock *clock = to_div6_clock(hw);
154	u8 hw_index;
155	u32 mask;
156
157	if (index >= clk_hw_get_num_parents(hw))
158		return -EINVAL;
159
160	mask = ~((BIT(clock->src_width) - 1) << clock->src_shift);
161	hw_index = clock->parents[index];
162
163	writel((readl(clock->reg) & mask) | (hw_index << clock->src_shift),
164	       clock->reg);
165
166	return 0;
167}
168
169static const struct clk_ops cpg_div6_clock_ops = {
170	.enable = cpg_div6_clock_enable,
171	.disable = cpg_div6_clock_disable,
172	.is_enabled = cpg_div6_clock_is_enabled,
173	.get_parent = cpg_div6_clock_get_parent,
174	.set_parent = cpg_div6_clock_set_parent,
175	.recalc_rate = cpg_div6_clock_recalc_rate,
176	.round_rate = cpg_div6_clock_round_rate,
177	.set_rate = cpg_div6_clock_set_rate,
178};
179
180static int cpg_div6_clock_notifier_call(struct notifier_block *nb,
181					unsigned long action, void *data)
182{
183	struct div6_clock *clock = container_of(nb, struct div6_clock, nb);
184
185	switch (action) {
186	case PM_EVENT_RESUME:
187		/*
188		 * TODO: This does not yet support DIV6 clocks with multiple
189		 * parents, as the parent selection bits are not restored.
190		 * Fortunately so far such DIV6 clocks are found only on
191		 * R/SH-Mobile SoCs, while the resume functionality is only
192		 * needed on R-Car Gen3.
193		 */
194		if (__clk_get_enable_count(clock->hw.clk))
195			cpg_div6_clock_enable(&clock->hw);
196		else
197			cpg_div6_clock_disable(&clock->hw);
198		return NOTIFY_OK;
199	}
200
201	return NOTIFY_DONE;
202}
203
204/**
205 * cpg_div6_register - Register a DIV6 clock
206 * @name: Name of the DIV6 clock
207 * @num_parents: Number of parent clocks of the DIV6 clock (1, 4, or 8)
208 * @parent_names: Array containing the names of the parent clocks
209 * @reg: Mapped register used to control the DIV6 clock
210 * @notifiers: Optional notifier chain to save/restore state for system resume
211 */
212struct clk * __init cpg_div6_register(const char *name,
213				      unsigned int num_parents,
214				      const char **parent_names,
215				      void __iomem *reg,
216				      struct raw_notifier_head *notifiers)
217{
218	unsigned int valid_parents;
219	struct clk_init_data init;
220	struct div6_clock *clock;
221	struct clk *clk;
222	unsigned int i;
223
224	clock = kzalloc(struct_size(clock, parents, num_parents), GFP_KERNEL);
225	if (!clock)
226		return ERR_PTR(-ENOMEM);
227
228	clock->reg = reg;
229
230	/*
231	 * Read the divisor. Disabling the clock overwrites the divisor, so we
232	 * need to cache its value for the enable operation.
233	 */
234	clock->div = (readl(clock->reg) & CPG_DIV6_DIV_MASK) + 1;
235
236	switch (num_parents) {
237	case 1:
238		/* fixed parent clock */
239		clock->src_shift = clock->src_width = 0;
240		break;
241	case 4:
242		/* clock with EXSRC bits 6-7 */
243		clock->src_shift = 6;
244		clock->src_width = 2;
245		break;
246	case 8:
247		/* VCLK with EXSRC bits 12-14 */
248		clock->src_shift = 12;
249		clock->src_width = 3;
250		break;
251	default:
252		pr_err("%s: invalid number of parents for DIV6 clock %s\n",
253		       __func__, name);
254		clk = ERR_PTR(-EINVAL);
255		goto free_clock;
256	}
257
258	/* Filter out invalid parents */
259	for (i = 0, valid_parents = 0; i < num_parents; i++) {
260		if (parent_names[i]) {
261			parent_names[valid_parents] = parent_names[i];
262			clock->parents[valid_parents] = i;
263			valid_parents++;
264		}
265	}
266
267	/* Register the clock. */
268	init.name = name;
269	init.ops = &cpg_div6_clock_ops;
270	init.flags = 0;
271	init.parent_names = parent_names;
272	init.num_parents = valid_parents;
273
274	clock->hw.init = &init;
275
276	clk = clk_register(NULL, &clock->hw);
277	if (IS_ERR(clk))
278		goto free_clock;
279
280	if (notifiers) {
281		clock->nb.notifier_call = cpg_div6_clock_notifier_call;
282		raw_notifier_chain_register(notifiers, &clock->nb);
283	}
284
285	return clk;
286
287free_clock:
288	kfree(clock);
289	return clk;
290}
291
292static void __init cpg_div6_clock_init(struct device_node *np)
293{
294	unsigned int num_parents;
295	const char **parent_names;
296	const char *clk_name = np->name;
297	void __iomem *reg;
298	struct clk *clk;
299	unsigned int i;
300
301	num_parents = of_clk_get_parent_count(np);
302	if (num_parents < 1) {
303		pr_err("%s: no parent found for %pOFn DIV6 clock\n",
304		       __func__, np);
305		return;
306	}
307
308	parent_names = kmalloc_array(num_parents, sizeof(*parent_names),
309				GFP_KERNEL);
310	if (!parent_names)
311		return;
312
313	reg = of_iomap(np, 0);
314	if (reg == NULL) {
315		pr_err("%s: failed to map %pOFn DIV6 clock register\n",
316		       __func__, np);
317		goto error;
318	}
319
320	/* Parse the DT properties. */
321	of_property_read_string(np, "clock-output-names", &clk_name);
322
323	for (i = 0; i < num_parents; i++)
324		parent_names[i] = of_clk_get_parent_name(np, i);
325
326	clk = cpg_div6_register(clk_name, num_parents, parent_names, reg, NULL);
327	if (IS_ERR(clk)) {
328		pr_err("%s: failed to register %pOFn DIV6 clock (%ld)\n",
329		       __func__, np, PTR_ERR(clk));
330		goto error;
331	}
332
333	of_clk_add_provider(np, of_clk_src_simple_get, clk);
334
335	kfree(parent_names);
336	return;
337
338error:
339	if (reg)
340		iounmap(reg);
341	kfree(parent_names);
342}
343CLK_OF_DECLARE(cpg_div6_clk, "renesas,cpg-div6-clock", cpg_div6_clock_init);
344