1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. 4 */ 5 6#include <linux/clk-provider.h> 7#include <linux/module.h> 8#include <linux/platform_device.h> 9#include <linux/regmap.h> 10 11#include <dt-bindings/clock/qcom,videocc-sm8250.h> 12 13#include "clk-alpha-pll.h" 14#include "clk-branch.h" 15#include "clk-rcg.h" 16#include "clk-regmap.h" 17#include "clk-regmap-divider.h" 18#include "common.h" 19#include "reset.h" 20#include "gdsc.h" 21 22enum { 23 P_BI_TCXO, 24 P_CHIP_SLEEP_CLK, 25 P_CORE_BI_PLL_TEST_SE, 26 P_VIDEO_PLL0_OUT_MAIN, 27 P_VIDEO_PLL1_OUT_MAIN, 28}; 29 30static struct pll_vco lucid_vco[] = { 31 { 249600000, 2000000000, 0 }, 32}; 33 34static const struct alpha_pll_config video_pll0_config = { 35 .l = 0x25, 36 .alpha = 0x8000, 37 .config_ctl_val = 0x20485699, 38 .config_ctl_hi_val = 0x00002261, 39 .config_ctl_hi1_val = 0x329A699C, 40 .user_ctl_val = 0x00000000, 41 .user_ctl_hi_val = 0x00000805, 42 .user_ctl_hi1_val = 0x00000000, 43}; 44 45static struct clk_alpha_pll video_pll0 = { 46 .offset = 0x42c, 47 .vco_table = lucid_vco, 48 .num_vco = ARRAY_SIZE(lucid_vco), 49 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 50 .clkr = { 51 .hw.init = &(struct clk_init_data){ 52 .name = "video_pll0", 53 .parent_data = &(const struct clk_parent_data){ 54 .fw_name = "bi_tcxo", 55 }, 56 .num_parents = 1, 57 .ops = &clk_alpha_pll_lucid_ops, 58 }, 59 }, 60}; 61 62static const struct alpha_pll_config video_pll1_config = { 63 .l = 0x2B, 64 .alpha = 0xC000, 65 .config_ctl_val = 0x20485699, 66 .config_ctl_hi_val = 0x00002261, 67 .config_ctl_hi1_val = 0x329A699C, 68 .user_ctl_val = 0x00000000, 69 .user_ctl_hi_val = 0x00000805, 70 .user_ctl_hi1_val = 0x00000000, 71}; 72 73static struct clk_alpha_pll video_pll1 = { 74 .offset = 0x7d0, 75 .vco_table = lucid_vco, 76 .num_vco = ARRAY_SIZE(lucid_vco), 77 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 78 .clkr = { 79 .hw.init = &(struct clk_init_data){ 80 .name = "video_pll1", 81 .parent_data = &(const struct clk_parent_data){ 82 .fw_name = "bi_tcxo", 83 }, 84 .num_parents = 1, 85 .ops = &clk_alpha_pll_lucid_ops, 86 }, 87 }, 88}; 89 90static const struct parent_map video_cc_parent_map_1[] = { 91 { P_BI_TCXO, 0 }, 92 { P_VIDEO_PLL0_OUT_MAIN, 1 }, 93}; 94 95static const struct clk_parent_data video_cc_parent_data_1[] = { 96 { .fw_name = "bi_tcxo" }, 97 { .hw = &video_pll0.clkr.hw }, 98}; 99 100static const struct parent_map video_cc_parent_map_2[] = { 101 { P_BI_TCXO, 0 }, 102 { P_VIDEO_PLL1_OUT_MAIN, 1 }, 103}; 104 105static const struct clk_parent_data video_cc_parent_data_2[] = { 106 { .fw_name = "bi_tcxo" }, 107 { .hw = &video_pll1.clkr.hw }, 108}; 109 110static const struct freq_tbl ftbl_video_cc_mvs0_clk_src[] = { 111 F(19200000, P_BI_TCXO, 1, 0, 0), 112 F(720000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0), 113 F(1014000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0), 114 F(1098000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0), 115 F(1332000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0), 116 { } 117}; 118 119static struct clk_rcg2 video_cc_mvs0_clk_src = { 120 .cmd_rcgr = 0xb94, 121 .mnd_width = 0, 122 .hid_width = 5, 123 .parent_map = video_cc_parent_map_1, 124 .freq_tbl = ftbl_video_cc_mvs0_clk_src, 125 .clkr.hw.init = &(struct clk_init_data){ 126 .name = "video_cc_mvs0_clk_src", 127 .parent_data = video_cc_parent_data_1, 128 .num_parents = ARRAY_SIZE(video_cc_parent_data_1), 129 .flags = CLK_SET_RATE_PARENT, 130 .ops = &clk_rcg2_shared_ops, 131 }, 132}; 133 134static const struct freq_tbl ftbl_video_cc_mvs1_clk_src[] = { 135 F(19200000, P_BI_TCXO, 1, 0, 0), 136 F(840000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0), 137 F(1098000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0), 138 F(1332000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0), 139 { } 140}; 141 142static struct clk_rcg2 video_cc_mvs1_clk_src = { 143 .cmd_rcgr = 0xbb4, 144 .mnd_width = 0, 145 .hid_width = 5, 146 .parent_map = video_cc_parent_map_2, 147 .freq_tbl = ftbl_video_cc_mvs1_clk_src, 148 .clkr.hw.init = &(struct clk_init_data){ 149 .name = "video_cc_mvs1_clk_src", 150 .parent_data = video_cc_parent_data_2, 151 .num_parents = ARRAY_SIZE(video_cc_parent_data_2), 152 .flags = CLK_SET_RATE_PARENT, 153 .ops = &clk_rcg2_shared_ops, 154 }, 155}; 156 157static struct clk_regmap_div video_cc_mvs0c_div2_div_clk_src = { 158 .reg = 0xc54, 159 .shift = 0, 160 .width = 2, 161 .clkr.hw.init = &(struct clk_init_data) { 162 .name = "video_cc_mvs0c_div2_div_clk_src", 163 .parent_data = &(const struct clk_parent_data){ 164 .hw = &video_cc_mvs0_clk_src.clkr.hw, 165 }, 166 .num_parents = 1, 167 .flags = CLK_SET_RATE_PARENT, 168 .ops = &clk_regmap_div_ro_ops, 169 }, 170}; 171 172static struct clk_regmap_div video_cc_mvs1c_div2_div_clk_src = { 173 .reg = 0xcf4, 174 .shift = 0, 175 .width = 2, 176 .clkr.hw.init = &(struct clk_init_data) { 177 .name = "video_cc_mvs1c_div2_div_clk_src", 178 .parent_data = &(const struct clk_parent_data){ 179 .hw = &video_cc_mvs1_clk_src.clkr.hw, 180 }, 181 .num_parents = 1, 182 .flags = CLK_SET_RATE_PARENT, 183 .ops = &clk_regmap_div_ro_ops, 184 }, 185}; 186 187static struct clk_branch video_cc_mvs0c_clk = { 188 .halt_reg = 0xc34, 189 .halt_check = BRANCH_HALT, 190 .clkr = { 191 .enable_reg = 0xc34, 192 .enable_mask = BIT(0), 193 .hw.init = &(struct clk_init_data){ 194 .name = "video_cc_mvs0c_clk", 195 .parent_data = &(const struct clk_parent_data){ 196 .hw = &video_cc_mvs0c_div2_div_clk_src.clkr.hw, 197 }, 198 .num_parents = 1, 199 .flags = CLK_SET_RATE_PARENT, 200 .ops = &clk_branch2_ops, 201 }, 202 }, 203}; 204 205static struct clk_branch video_cc_mvs1_div2_clk = { 206 .halt_reg = 0xdf4, 207 .halt_check = BRANCH_HALT_VOTED, 208 .clkr = { 209 .enable_reg = 0xdf4, 210 .enable_mask = BIT(0), 211 .hw.init = &(struct clk_init_data){ 212 .name = "video_cc_mvs1_div2_clk", 213 .parent_data = &(const struct clk_parent_data){ 214 .hw = &video_cc_mvs1c_div2_div_clk_src.clkr.hw, 215 }, 216 .num_parents = 1, 217 .flags = CLK_SET_RATE_PARENT, 218 .ops = &clk_branch2_ops, 219 }, 220 }, 221}; 222 223static struct clk_branch video_cc_mvs1c_clk = { 224 .halt_reg = 0xcd4, 225 .halt_check = BRANCH_HALT_VOTED, 226 .clkr = { 227 .enable_reg = 0xcd4, 228 .enable_mask = BIT(0), 229 .hw.init = &(struct clk_init_data){ 230 .name = "video_cc_mvs1c_clk", 231 .parent_data = &(const struct clk_parent_data){ 232 .hw = &video_cc_mvs1c_div2_div_clk_src.clkr.hw, 233 }, 234 .num_parents = 1, 235 .flags = CLK_SET_RATE_PARENT, 236 .ops = &clk_branch2_ops, 237 }, 238 }, 239}; 240 241static struct gdsc mvs0c_gdsc = { 242 .gdscr = 0xbf8, 243 .pd = { 244 .name = "mvs0c_gdsc", 245 }, 246 .flags = 0, 247 .pwrsts = PWRSTS_OFF_ON, 248}; 249 250static struct gdsc mvs1c_gdsc = { 251 .gdscr = 0xc98, 252 .pd = { 253 .name = "mvs1c_gdsc", 254 }, 255 .flags = 0, 256 .pwrsts = PWRSTS_OFF_ON, 257}; 258 259static struct gdsc mvs0_gdsc = { 260 .gdscr = 0xd18, 261 .pd = { 262 .name = "mvs0_gdsc", 263 }, 264 .flags = HW_CTRL, 265 .pwrsts = PWRSTS_OFF_ON, 266}; 267 268static struct gdsc mvs1_gdsc = { 269 .gdscr = 0xd98, 270 .pd = { 271 .name = "mvs1_gdsc", 272 }, 273 .flags = HW_CTRL, 274 .pwrsts = PWRSTS_OFF_ON, 275}; 276 277static struct clk_regmap *video_cc_sm8250_clocks[] = { 278 [VIDEO_CC_MVS0_CLK_SRC] = &video_cc_mvs0_clk_src.clkr, 279 [VIDEO_CC_MVS0C_CLK] = &video_cc_mvs0c_clk.clkr, 280 [VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC] = &video_cc_mvs0c_div2_div_clk_src.clkr, 281 [VIDEO_CC_MVS1_CLK_SRC] = &video_cc_mvs1_clk_src.clkr, 282 [VIDEO_CC_MVS1_DIV2_CLK] = &video_cc_mvs1_div2_clk.clkr, 283 [VIDEO_CC_MVS1C_CLK] = &video_cc_mvs1c_clk.clkr, 284 [VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC] = &video_cc_mvs1c_div2_div_clk_src.clkr, 285 [VIDEO_CC_PLL0] = &video_pll0.clkr, 286 [VIDEO_CC_PLL1] = &video_pll1.clkr, 287}; 288 289static const struct qcom_reset_map video_cc_sm8250_resets[] = { 290 [VIDEO_CC_CVP_INTERFACE_BCR] = { 0xe54 }, 291 [VIDEO_CC_CVP_MVS0_BCR] = { 0xd14 }, 292 [VIDEO_CC_MVS0C_CLK_ARES] = { 0xc34, 2 }, 293 [VIDEO_CC_CVP_MVS0C_BCR] = { 0xbf4 }, 294 [VIDEO_CC_CVP_MVS1_BCR] = { 0xd94 }, 295 [VIDEO_CC_MVS1C_CLK_ARES] = { 0xcd4, 2 }, 296 [VIDEO_CC_CVP_MVS1C_BCR] = { 0xc94 }, 297}; 298 299static struct gdsc *video_cc_sm8250_gdscs[] = { 300 [MVS0C_GDSC] = &mvs0c_gdsc, 301 [MVS1C_GDSC] = &mvs1c_gdsc, 302 [MVS0_GDSC] = &mvs0_gdsc, 303 [MVS1_GDSC] = &mvs1_gdsc, 304}; 305 306static const struct regmap_config video_cc_sm8250_regmap_config = { 307 .reg_bits = 32, 308 .reg_stride = 4, 309 .val_bits = 32, 310 .max_register = 0xf4c, 311 .fast_io = true, 312}; 313 314static const struct qcom_cc_desc video_cc_sm8250_desc = { 315 .config = &video_cc_sm8250_regmap_config, 316 .clks = video_cc_sm8250_clocks, 317 .num_clks = ARRAY_SIZE(video_cc_sm8250_clocks), 318 .resets = video_cc_sm8250_resets, 319 .num_resets = ARRAY_SIZE(video_cc_sm8250_resets), 320 .gdscs = video_cc_sm8250_gdscs, 321 .num_gdscs = ARRAY_SIZE(video_cc_sm8250_gdscs), 322}; 323 324static const struct of_device_id video_cc_sm8250_match_table[] = { 325 { .compatible = "qcom,sm8250-videocc" }, 326 { } 327}; 328MODULE_DEVICE_TABLE(of, video_cc_sm8250_match_table); 329 330static int video_cc_sm8250_probe(struct platform_device *pdev) 331{ 332 struct regmap *regmap; 333 334 regmap = qcom_cc_map(pdev, &video_cc_sm8250_desc); 335 if (IS_ERR(regmap)) 336 return PTR_ERR(regmap); 337 338 clk_lucid_pll_configure(&video_pll0, regmap, &video_pll0_config); 339 clk_lucid_pll_configure(&video_pll1, regmap, &video_pll1_config); 340 341 /* Keep VIDEO_CC_AHB_CLK and VIDEO_CC_XO_CLK ALWAYS-ON */ 342 regmap_update_bits(regmap, 0xe58, BIT(0), BIT(0)); 343 regmap_update_bits(regmap, 0xeec, BIT(0), BIT(0)); 344 345 return qcom_cc_really_probe(pdev, &video_cc_sm8250_desc, regmap); 346} 347 348static struct platform_driver video_cc_sm8250_driver = { 349 .probe = video_cc_sm8250_probe, 350 .driver = { 351 .name = "sm8250-videocc", 352 .of_match_table = video_cc_sm8250_match_table, 353 }, 354}; 355 356static int __init video_cc_sm8250_init(void) 357{ 358 return platform_driver_register(&video_cc_sm8250_driver); 359} 360subsys_initcall(video_cc_sm8250_init); 361 362static void __exit video_cc_sm8250_exit(void) 363{ 364 platform_driver_unregister(&video_cc_sm8250_driver); 365} 366module_exit(video_cc_sm8250_exit); 367 368MODULE_LICENSE("GPL v2"); 369MODULE_DESCRIPTION("QTI VIDEOCC SM8250 Driver"); 370