1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
4 */
5
6#include <linux/clk-provider.h>
7#include <linux/module.h>
8#include <linux/platform_device.h>
9#include <linux/regmap.h>
10
11#include <dt-bindings/clock/qcom,videocc-sm8150.h>
12
13#include "common.h"
14#include "clk-alpha-pll.h"
15#include "clk-branch.h"
16#include "clk-rcg.h"
17#include "clk-regmap.h"
18#include "reset.h"
19#include "gdsc.h"
20
21enum {
22	P_BI_TCXO,
23	P_CHIP_SLEEP_CLK,
24	P_CORE_BI_PLL_TEST_SE,
25	P_VIDEO_PLL0_OUT_EVEN,
26	P_VIDEO_PLL0_OUT_MAIN,
27	P_VIDEO_PLL0_OUT_ODD,
28};
29
30static struct pll_vco trion_vco[] = {
31	{ 249600000, 2000000000, 0 },
32};
33
34static struct alpha_pll_config video_pll0_config = {
35	.l = 0x14,
36	.alpha = 0xD555,
37	.config_ctl_val = 0x20485699,
38	.config_ctl_hi_val = 0x00002267,
39	.config_ctl_hi1_val = 0x00000024,
40	.test_ctl_hi1_val = 0x00000020,
41	.user_ctl_val = 0x00000000,
42	.user_ctl_hi_val = 0x00000805,
43	.user_ctl_hi1_val = 0x000000D0,
44};
45
46static struct clk_alpha_pll video_pll0 = {
47	.offset = 0x42c,
48	.vco_table = trion_vco,
49	.num_vco = ARRAY_SIZE(trion_vco),
50	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
51	.clkr = {
52		.hw.init = &(struct clk_init_data){
53			.name = "video_pll0",
54			.parent_data = &(const struct clk_parent_data){
55				.fw_name = "bi_tcxo",
56			},
57			.num_parents = 1,
58			.ops = &clk_alpha_pll_trion_ops,
59		},
60	},
61};
62
63static const struct parent_map video_cc_parent_map_0[] = {
64	{ P_BI_TCXO, 0 },
65	{ P_VIDEO_PLL0_OUT_MAIN, 1 },
66};
67
68static const struct clk_parent_data video_cc_parent_data_0[] = {
69	{ .fw_name = "bi_tcxo" },
70	{ .hw = &video_pll0.clkr.hw },
71};
72
73static const struct freq_tbl ftbl_video_cc_iris_clk_src[] = {
74	F(19200000, P_BI_TCXO, 1, 0, 0),
75	F(200000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
76	F(240000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
77	F(338000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
78	F(365000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
79	F(444000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
80	F(533000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
81	{ }
82};
83
84static struct clk_rcg2 video_cc_iris_clk_src = {
85	.cmd_rcgr = 0x7f0,
86	.mnd_width = 0,
87	.hid_width = 5,
88	.parent_map = video_cc_parent_map_0,
89	.freq_tbl = ftbl_video_cc_iris_clk_src,
90	.clkr.hw.init = &(struct clk_init_data){
91		.name = "video_cc_iris_clk_src",
92		.parent_data = video_cc_parent_data_0,
93		.num_parents = ARRAY_SIZE(video_cc_parent_data_0),
94		.flags = CLK_SET_RATE_PARENT,
95		.ops = &clk_rcg2_shared_ops,
96	},
97};
98
99static struct clk_branch video_cc_iris_ahb_clk = {
100	.halt_reg = 0x8f4,
101	.halt_check = BRANCH_VOTED,
102	.clkr = {
103		.enable_reg = 0x8f4,
104		.enable_mask = BIT(0),
105		.hw.init = &(struct clk_init_data){
106			.name = "video_cc_iris_ahb_clk",
107			.parent_data = &(const struct clk_parent_data){
108				.hw = &video_cc_iris_clk_src.clkr.hw,
109			},
110			.num_parents = 1,
111			.flags = CLK_SET_RATE_PARENT,
112			.ops = &clk_branch2_ops,
113		},
114	},
115};
116
117static struct clk_branch video_cc_mvs0_core_clk = {
118	.halt_reg = 0x890,
119	.halt_check = BRANCH_VOTED,
120	.clkr = {
121		.enable_reg = 0x890,
122		.enable_mask = BIT(0),
123		.hw.init = &(struct clk_init_data){
124			.name = "video_cc_mvs0_core_clk",
125			.parent_data = &(const struct clk_parent_data){
126				.hw = &video_cc_iris_clk_src.clkr.hw,
127			},
128			.num_parents = 1,
129			.flags = CLK_SET_RATE_PARENT,
130			.ops = &clk_branch2_ops,
131		},
132	},
133};
134
135static struct clk_branch video_cc_mvs1_core_clk = {
136	.halt_reg = 0x8d0,
137	.halt_check = BRANCH_VOTED,
138	.clkr = {
139		.enable_reg = 0x8d0,
140		.enable_mask = BIT(0),
141		.hw.init = &(struct clk_init_data){
142			.name = "video_cc_mvs1_core_clk",
143			.parent_data = &(const struct clk_parent_data){
144				.hw = &video_cc_iris_clk_src.clkr.hw,
145			},
146			.num_parents = 1,
147			.flags = CLK_SET_RATE_PARENT,
148			.ops = &clk_branch2_ops,
149		},
150	},
151};
152
153static struct clk_branch video_cc_mvsc_core_clk = {
154	.halt_reg = 0x850,
155	.halt_check = BRANCH_HALT,
156	.clkr = {
157		.enable_reg = 0x850,
158		.enable_mask = BIT(0),
159		.hw.init = &(struct clk_init_data){
160			.name = "video_cc_mvsc_core_clk",
161			.parent_data = &(const struct clk_parent_data){
162				.hw = &video_cc_iris_clk_src.clkr.hw,
163			},
164			.num_parents = 1,
165			.flags = CLK_SET_RATE_PARENT,
166			.ops = &clk_branch2_ops,
167		},
168	},
169};
170
171static struct gdsc venus_gdsc = {
172	.gdscr = 0x814,
173	.pd = {
174		.name = "venus_gdsc",
175	},
176	.flags = 0,
177	.pwrsts = PWRSTS_OFF_ON,
178};
179
180static struct gdsc vcodec0_gdsc = {
181	.gdscr = 0x874,
182	.pd = {
183		.name = "vcodec0_gdsc",
184	},
185	.flags = HW_CTRL,
186	.pwrsts = PWRSTS_OFF_ON,
187};
188
189static struct gdsc vcodec1_gdsc = {
190	.gdscr = 0x8b4,
191	.pd = {
192		.name = "vcodec1_gdsc",
193	},
194	.flags = HW_CTRL,
195	.pwrsts = PWRSTS_OFF_ON,
196};
197static struct clk_regmap *video_cc_sm8150_clocks[] = {
198	[VIDEO_CC_IRIS_AHB_CLK] = &video_cc_iris_ahb_clk.clkr,
199	[VIDEO_CC_IRIS_CLK_SRC] = &video_cc_iris_clk_src.clkr,
200	[VIDEO_CC_MVS0_CORE_CLK] = &video_cc_mvs0_core_clk.clkr,
201	[VIDEO_CC_MVS1_CORE_CLK] = &video_cc_mvs1_core_clk.clkr,
202	[VIDEO_CC_MVSC_CORE_CLK] = &video_cc_mvsc_core_clk.clkr,
203	[VIDEO_CC_PLL0] = &video_pll0.clkr,
204};
205
206static struct gdsc *video_cc_sm8150_gdscs[] = {
207	[VENUS_GDSC] = &venus_gdsc,
208	[VCODEC0_GDSC] = &vcodec0_gdsc,
209	[VCODEC1_GDSC] = &vcodec1_gdsc,
210};
211
212static const struct regmap_config video_cc_sm8150_regmap_config = {
213	.reg_bits	= 32,
214	.reg_stride	= 4,
215	.val_bits	= 32,
216	.max_register	= 0xb94,
217	.fast_io	= true,
218};
219
220static const struct qcom_reset_map video_cc_sm8150_resets[] = {
221	[VIDEO_CC_MVSC_CORE_CLK_BCR] = { 0x850, 2 },
222	[VIDEO_CC_INTERFACE_BCR] = { 0x8f0 },
223	[VIDEO_CC_MVS0_BCR] = { 0x870 },
224	[VIDEO_CC_MVS1_BCR] = { 0x8b0 },
225	[VIDEO_CC_MVSC_BCR] = { 0x810 },
226};
227
228static const struct qcom_cc_desc video_cc_sm8150_desc = {
229	.config = &video_cc_sm8150_regmap_config,
230	.clks = video_cc_sm8150_clocks,
231	.num_clks = ARRAY_SIZE(video_cc_sm8150_clocks),
232	.resets = video_cc_sm8150_resets,
233	.num_resets = ARRAY_SIZE(video_cc_sm8150_resets),
234	.gdscs = video_cc_sm8150_gdscs,
235	.num_gdscs = ARRAY_SIZE(video_cc_sm8150_gdscs),
236};
237
238static const struct of_device_id video_cc_sm8150_match_table[] = {
239	{ .compatible = "qcom,sm8150-videocc" },
240	{ }
241};
242MODULE_DEVICE_TABLE(of, video_cc_sm8150_match_table);
243
244static int video_cc_sm8150_probe(struct platform_device *pdev)
245{
246	struct regmap *regmap;
247
248	regmap = qcom_cc_map(pdev, &video_cc_sm8150_desc);
249	if (IS_ERR(regmap))
250		return PTR_ERR(regmap);
251
252	clk_trion_pll_configure(&video_pll0, regmap, &video_pll0_config);
253
254	/* Keep VIDEO_CC_XO_CLK ALWAYS-ON */
255	regmap_update_bits(regmap, 0x984, 0x1, 0x1);
256
257	return qcom_cc_really_probe(pdev, &video_cc_sm8150_desc, regmap);
258}
259
260static struct platform_driver video_cc_sm8150_driver = {
261	.probe = video_cc_sm8150_probe,
262	.driver = {
263		.name	= "video_cc-sm8150",
264		.of_match_table = video_cc_sm8150_match_table,
265	},
266};
267
268static int __init video_cc_sm8150_init(void)
269{
270	return platform_driver_register(&video_cc_sm8150_driver);
271}
272subsys_initcall(video_cc_sm8150_init);
273
274static void __exit video_cc_sm8150_exit(void)
275{
276	platform_driver_unregister(&video_cc_sm8150_driver);
277}
278module_exit(video_cc_sm8150_exit);
279
280MODULE_LICENSE("GPL v2");
281MODULE_DESCRIPTION("QTI VIDEOCC SM8150 Driver");
282