1// SPDX-License-Identifier: GPL-2.0-only 2/*x 3 * Copyright (c) 2015, The Linux Foundation. All rights reserved. 4 */ 5 6#include <linux/kernel.h> 7#include <linux/bitops.h> 8#include <linux/err.h> 9#include <linux/platform_device.h> 10#include <linux/module.h> 11#include <linux/of.h> 12#include <linux/of_device.h> 13#include <linux/clk-provider.h> 14#include <linux/regmap.h> 15#include <linux/reset-controller.h> 16#include <linux/clk.h> 17 18#include <dt-bindings/clock/qcom,mmcc-msm8996.h> 19 20#include "common.h" 21#include "clk-regmap.h" 22#include "clk-regmap-divider.h" 23#include "clk-alpha-pll.h" 24#include "clk-rcg.h" 25#include "clk-branch.h" 26#include "reset.h" 27#include "gdsc.h" 28 29enum { 30 P_XO, 31 P_MMPLL0, 32 P_GPLL0, 33 P_GPLL0_DIV, 34 P_MMPLL1, 35 P_MMPLL9, 36 P_MMPLL2, 37 P_MMPLL8, 38 P_MMPLL3, 39 P_DSI0PLL, 40 P_DSI1PLL, 41 P_MMPLL5, 42 P_HDMIPLL, 43 P_DSI0PLL_BYTE, 44 P_DSI1PLL_BYTE, 45 P_MMPLL4, 46}; 47 48static const struct parent_map mmss_xo_hdmi_map[] = { 49 { P_XO, 0 }, 50 { P_HDMIPLL, 1 } 51}; 52 53static const char * const mmss_xo_hdmi[] = { 54 "xo", 55 "hdmipll" 56}; 57 58static const struct parent_map mmss_xo_dsi0pll_dsi1pll_map[] = { 59 { P_XO, 0 }, 60 { P_DSI0PLL, 1 }, 61 { P_DSI1PLL, 2 } 62}; 63 64static const char * const mmss_xo_dsi0pll_dsi1pll[] = { 65 "xo", 66 "dsi0pll", 67 "dsi1pll" 68}; 69 70static const struct parent_map mmss_xo_gpll0_gpll0_div_map[] = { 71 { P_XO, 0 }, 72 { P_GPLL0, 5 }, 73 { P_GPLL0_DIV, 6 } 74}; 75 76static const char * const mmss_xo_gpll0_gpll0_div[] = { 77 "xo", 78 "gpll0", 79 "gpll0_div" 80}; 81 82static const struct parent_map mmss_xo_dsibyte_map[] = { 83 { P_XO, 0 }, 84 { P_DSI0PLL_BYTE, 1 }, 85 { P_DSI1PLL_BYTE, 2 } 86}; 87 88static const char * const mmss_xo_dsibyte[] = { 89 "xo", 90 "dsi0pllbyte", 91 "dsi1pllbyte" 92}; 93 94static const struct parent_map mmss_xo_mmpll0_gpll0_gpll0_div_map[] = { 95 { P_XO, 0 }, 96 { P_MMPLL0, 1 }, 97 { P_GPLL0, 5 }, 98 { P_GPLL0_DIV, 6 } 99}; 100 101static const char * const mmss_xo_mmpll0_gpll0_gpll0_div[] = { 102 "xo", 103 "mmpll0", 104 "gpll0", 105 "gpll0_div" 106}; 107 108static const struct parent_map mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map[] = { 109 { P_XO, 0 }, 110 { P_MMPLL0, 1 }, 111 { P_MMPLL1, 2 }, 112 { P_GPLL0, 5 }, 113 { P_GPLL0_DIV, 6 } 114}; 115 116static const char * const mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div[] = { 117 "xo", 118 "mmpll0", 119 "mmpll1", 120 "gpll0", 121 "gpll0_div" 122}; 123 124static const struct parent_map mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div_map[] = { 125 { P_XO, 0 }, 126 { P_MMPLL0, 1 }, 127 { P_MMPLL3, 3 }, 128 { P_GPLL0, 5 }, 129 { P_GPLL0_DIV, 6 } 130}; 131 132static const char * const mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div[] = { 133 "xo", 134 "mmpll0", 135 "mmpll3", 136 "gpll0", 137 "gpll0_div" 138}; 139 140static const struct parent_map mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map[] = { 141 { P_XO, 0 }, 142 { P_MMPLL0, 1 }, 143 { P_MMPLL5, 2 }, 144 { P_GPLL0, 5 }, 145 { P_GPLL0_DIV, 6 } 146}; 147 148static const char * const mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div[] = { 149 "xo", 150 "mmpll0", 151 "mmpll5", 152 "gpll0", 153 "gpll0_div" 154}; 155 156static const struct parent_map mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map[] = { 157 { P_XO, 0 }, 158 { P_MMPLL0, 1 }, 159 { P_MMPLL4, 3 }, 160 { P_GPLL0, 5 }, 161 { P_GPLL0_DIV, 6 } 162}; 163 164static const char * const mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div[] = { 165 "xo", 166 "mmpll0", 167 "mmpll4", 168 "gpll0", 169 "gpll0_div" 170}; 171 172static const struct parent_map mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_map[] = { 173 { P_XO, 0 }, 174 { P_MMPLL0, 1 }, 175 { P_MMPLL9, 2 }, 176 { P_MMPLL2, 3 }, 177 { P_MMPLL8, 4 }, 178 { P_GPLL0, 5 } 179}; 180 181static const char * const mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0[] = { 182 "xo", 183 "mmpll0", 184 "mmpll9", 185 "mmpll2", 186 "mmpll8", 187 "gpll0" 188}; 189 190static const struct parent_map mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div_map[] = { 191 { P_XO, 0 }, 192 { P_MMPLL0, 1 }, 193 { P_MMPLL9, 2 }, 194 { P_MMPLL2, 3 }, 195 { P_MMPLL8, 4 }, 196 { P_GPLL0, 5 }, 197 { P_GPLL0_DIV, 6 } 198}; 199 200static const char * const mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div[] = { 201 "xo", 202 "mmpll0", 203 "mmpll9", 204 "mmpll2", 205 "mmpll8", 206 "gpll0", 207 "gpll0_div" 208}; 209 210static const struct parent_map mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map[] = { 211 { P_XO, 0 }, 212 { P_MMPLL0, 1 }, 213 { P_MMPLL1, 2 }, 214 { P_MMPLL4, 3 }, 215 { P_MMPLL3, 4 }, 216 { P_GPLL0, 5 }, 217 { P_GPLL0_DIV, 6 } 218}; 219 220static const char * const mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div[] = { 221 "xo", 222 "mmpll0", 223 "mmpll1", 224 "mmpll4", 225 "mmpll3", 226 "gpll0", 227 "gpll0_div" 228}; 229 230static struct clk_fixed_factor gpll0_div = { 231 .mult = 1, 232 .div = 2, 233 .hw.init = &(struct clk_init_data){ 234 .name = "gpll0_div", 235 .parent_names = (const char *[]){ "gpll0" }, 236 .num_parents = 1, 237 .ops = &clk_fixed_factor_ops, 238 }, 239}; 240 241static struct pll_vco mmpll_p_vco[] = { 242 { 250000000, 500000000, 3 }, 243 { 500000000, 1000000000, 2 }, 244 { 1000000000, 1500000000, 1 }, 245 { 1500000000, 2000000000, 0 }, 246}; 247 248static struct pll_vco mmpll_gfx_vco[] = { 249 { 400000000, 1000000000, 2 }, 250 { 1000000000, 1500000000, 1 }, 251 { 1500000000, 2000000000, 0 }, 252}; 253 254static struct pll_vco mmpll_t_vco[] = { 255 { 500000000, 1500000000, 0 }, 256}; 257 258static struct clk_alpha_pll mmpll0_early = { 259 .offset = 0x0, 260 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 261 .vco_table = mmpll_p_vco, 262 .num_vco = ARRAY_SIZE(mmpll_p_vco), 263 .clkr = { 264 .enable_reg = 0x100, 265 .enable_mask = BIT(0), 266 .hw.init = &(struct clk_init_data){ 267 .name = "mmpll0_early", 268 .parent_names = (const char *[]){ "xo" }, 269 .num_parents = 1, 270 .ops = &clk_alpha_pll_ops, 271 }, 272 }, 273}; 274 275static struct clk_alpha_pll_postdiv mmpll0 = { 276 .offset = 0x0, 277 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 278 .width = 4, 279 .clkr.hw.init = &(struct clk_init_data){ 280 .name = "mmpll0", 281 .parent_names = (const char *[]){ "mmpll0_early" }, 282 .num_parents = 1, 283 .ops = &clk_alpha_pll_postdiv_ops, 284 .flags = CLK_SET_RATE_PARENT, 285 }, 286}; 287 288static struct clk_alpha_pll mmpll1_early = { 289 .offset = 0x30, 290 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 291 .vco_table = mmpll_p_vco, 292 .num_vco = ARRAY_SIZE(mmpll_p_vco), 293 .clkr = { 294 .enable_reg = 0x100, 295 .enable_mask = BIT(1), 296 .hw.init = &(struct clk_init_data){ 297 .name = "mmpll1_early", 298 .parent_names = (const char *[]){ "xo" }, 299 .num_parents = 1, 300 .ops = &clk_alpha_pll_ops, 301 } 302 }, 303}; 304 305static struct clk_alpha_pll_postdiv mmpll1 = { 306 .offset = 0x30, 307 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 308 .width = 4, 309 .clkr.hw.init = &(struct clk_init_data){ 310 .name = "mmpll1", 311 .parent_names = (const char *[]){ "mmpll1_early" }, 312 .num_parents = 1, 313 .ops = &clk_alpha_pll_postdiv_ops, 314 .flags = CLK_SET_RATE_PARENT, 315 }, 316}; 317 318static struct clk_alpha_pll mmpll2_early = { 319 .offset = 0x4100, 320 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 321 .vco_table = mmpll_gfx_vco, 322 .num_vco = ARRAY_SIZE(mmpll_gfx_vco), 323 .clkr.hw.init = &(struct clk_init_data){ 324 .name = "mmpll2_early", 325 .parent_names = (const char *[]){ "xo" }, 326 .num_parents = 1, 327 .ops = &clk_alpha_pll_ops, 328 }, 329}; 330 331static struct clk_alpha_pll_postdiv mmpll2 = { 332 .offset = 0x4100, 333 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 334 .width = 4, 335 .clkr.hw.init = &(struct clk_init_data){ 336 .name = "mmpll2", 337 .parent_names = (const char *[]){ "mmpll2_early" }, 338 .num_parents = 1, 339 .ops = &clk_alpha_pll_postdiv_ops, 340 .flags = CLK_SET_RATE_PARENT, 341 }, 342}; 343 344static struct clk_alpha_pll mmpll3_early = { 345 .offset = 0x60, 346 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 347 .vco_table = mmpll_p_vco, 348 .num_vco = ARRAY_SIZE(mmpll_p_vco), 349 .clkr.hw.init = &(struct clk_init_data){ 350 .name = "mmpll3_early", 351 .parent_names = (const char *[]){ "xo" }, 352 .num_parents = 1, 353 .ops = &clk_alpha_pll_ops, 354 }, 355}; 356 357static struct clk_alpha_pll_postdiv mmpll3 = { 358 .offset = 0x60, 359 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 360 .width = 4, 361 .clkr.hw.init = &(struct clk_init_data){ 362 .name = "mmpll3", 363 .parent_names = (const char *[]){ "mmpll3_early" }, 364 .num_parents = 1, 365 .ops = &clk_alpha_pll_postdiv_ops, 366 .flags = CLK_SET_RATE_PARENT, 367 }, 368}; 369 370static struct clk_alpha_pll mmpll4_early = { 371 .offset = 0x90, 372 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 373 .vco_table = mmpll_t_vco, 374 .num_vco = ARRAY_SIZE(mmpll_t_vco), 375 .clkr.hw.init = &(struct clk_init_data){ 376 .name = "mmpll4_early", 377 .parent_names = (const char *[]){ "xo" }, 378 .num_parents = 1, 379 .ops = &clk_alpha_pll_ops, 380 }, 381}; 382 383static struct clk_alpha_pll_postdiv mmpll4 = { 384 .offset = 0x90, 385 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 386 .width = 2, 387 .clkr.hw.init = &(struct clk_init_data){ 388 .name = "mmpll4", 389 .parent_names = (const char *[]){ "mmpll4_early" }, 390 .num_parents = 1, 391 .ops = &clk_alpha_pll_postdiv_ops, 392 .flags = CLK_SET_RATE_PARENT, 393 }, 394}; 395 396static struct clk_alpha_pll mmpll5_early = { 397 .offset = 0xc0, 398 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 399 .vco_table = mmpll_p_vco, 400 .num_vco = ARRAY_SIZE(mmpll_p_vco), 401 .clkr.hw.init = &(struct clk_init_data){ 402 .name = "mmpll5_early", 403 .parent_names = (const char *[]){ "xo" }, 404 .num_parents = 1, 405 .ops = &clk_alpha_pll_ops, 406 }, 407}; 408 409static struct clk_alpha_pll_postdiv mmpll5 = { 410 .offset = 0xc0, 411 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 412 .width = 4, 413 .clkr.hw.init = &(struct clk_init_data){ 414 .name = "mmpll5", 415 .parent_names = (const char *[]){ "mmpll5_early" }, 416 .num_parents = 1, 417 .ops = &clk_alpha_pll_postdiv_ops, 418 .flags = CLK_SET_RATE_PARENT, 419 }, 420}; 421 422static struct clk_alpha_pll mmpll8_early = { 423 .offset = 0x4130, 424 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 425 .vco_table = mmpll_gfx_vco, 426 .num_vco = ARRAY_SIZE(mmpll_gfx_vco), 427 .clkr.hw.init = &(struct clk_init_data){ 428 .name = "mmpll8_early", 429 .parent_names = (const char *[]){ "xo" }, 430 .num_parents = 1, 431 .ops = &clk_alpha_pll_ops, 432 }, 433}; 434 435static struct clk_alpha_pll_postdiv mmpll8 = { 436 .offset = 0x4130, 437 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 438 .width = 4, 439 .clkr.hw.init = &(struct clk_init_data){ 440 .name = "mmpll8", 441 .parent_names = (const char *[]){ "mmpll8_early" }, 442 .num_parents = 1, 443 .ops = &clk_alpha_pll_postdiv_ops, 444 .flags = CLK_SET_RATE_PARENT, 445 }, 446}; 447 448static struct clk_alpha_pll mmpll9_early = { 449 .offset = 0x4200, 450 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 451 .vco_table = mmpll_t_vco, 452 .num_vco = ARRAY_SIZE(mmpll_t_vco), 453 .clkr.hw.init = &(struct clk_init_data){ 454 .name = "mmpll9_early", 455 .parent_names = (const char *[]){ "xo" }, 456 .num_parents = 1, 457 .ops = &clk_alpha_pll_ops, 458 }, 459}; 460 461static struct clk_alpha_pll_postdiv mmpll9 = { 462 .offset = 0x4200, 463 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 464 .width = 2, 465 .clkr.hw.init = &(struct clk_init_data){ 466 .name = "mmpll9", 467 .parent_names = (const char *[]){ "mmpll9_early" }, 468 .num_parents = 1, 469 .ops = &clk_alpha_pll_postdiv_ops, 470 .flags = CLK_SET_RATE_PARENT, 471 }, 472}; 473 474static const struct freq_tbl ftbl_ahb_clk_src[] = { 475 F(19200000, P_XO, 1, 0, 0), 476 F(40000000, P_GPLL0_DIV, 7.5, 0, 0), 477 F(80000000, P_MMPLL0, 10, 0, 0), 478 { } 479}; 480 481static struct clk_rcg2 ahb_clk_src = { 482 .cmd_rcgr = 0x5000, 483 .hid_width = 5, 484 .parent_map = mmss_xo_mmpll0_gpll0_gpll0_div_map, 485 .freq_tbl = ftbl_ahb_clk_src, 486 .clkr.hw.init = &(struct clk_init_data){ 487 .name = "ahb_clk_src", 488 .parent_names = mmss_xo_mmpll0_gpll0_gpll0_div, 489 .num_parents = 4, 490 .ops = &clk_rcg2_ops, 491 }, 492}; 493 494static const struct freq_tbl ftbl_axi_clk_src[] = { 495 F(19200000, P_XO, 1, 0, 0), 496 F(75000000, P_GPLL0_DIV, 4, 0, 0), 497 F(100000000, P_GPLL0, 6, 0, 0), 498 F(171430000, P_GPLL0, 3.5, 0, 0), 499 F(200000000, P_GPLL0, 3, 0, 0), 500 F(320000000, P_MMPLL0, 2.5, 0, 0), 501 F(400000000, P_MMPLL0, 2, 0, 0), 502 { } 503}; 504 505static struct clk_rcg2 axi_clk_src = { 506 .cmd_rcgr = 0x5040, 507 .hid_width = 5, 508 .parent_map = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map, 509 .freq_tbl = ftbl_axi_clk_src, 510 .clkr.hw.init = &(struct clk_init_data){ 511 .name = "axi_clk_src", 512 .parent_names = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div, 513 .num_parents = 5, 514 .ops = &clk_rcg2_ops, 515 }, 516}; 517 518static struct clk_rcg2 maxi_clk_src = { 519 .cmd_rcgr = 0x5090, 520 .hid_width = 5, 521 .parent_map = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map, 522 .freq_tbl = ftbl_axi_clk_src, 523 .clkr.hw.init = &(struct clk_init_data){ 524 .name = "maxi_clk_src", 525 .parent_names = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div, 526 .num_parents = 5, 527 .ops = &clk_rcg2_ops, 528 }, 529}; 530 531static struct clk_rcg2 gfx3d_clk_src = { 532 .cmd_rcgr = 0x4000, 533 .hid_width = 5, 534 .parent_map = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_map, 535 .clkr.hw.init = &(struct clk_init_data){ 536 .name = "gfx3d_clk_src", 537 .parent_names = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0, 538 .num_parents = 6, 539 .ops = &clk_gfx3d_ops, 540 .flags = CLK_SET_RATE_PARENT, 541 }, 542}; 543 544static const struct freq_tbl ftbl_rbbmtimer_clk_src[] = { 545 F(19200000, P_XO, 1, 0, 0), 546 { } 547}; 548 549static struct clk_rcg2 rbbmtimer_clk_src = { 550 .cmd_rcgr = 0x4090, 551 .hid_width = 5, 552 .parent_map = mmss_xo_mmpll0_gpll0_gpll0_div_map, 553 .freq_tbl = ftbl_rbbmtimer_clk_src, 554 .clkr.hw.init = &(struct clk_init_data){ 555 .name = "rbbmtimer_clk_src", 556 .parent_names = mmss_xo_mmpll0_gpll0_gpll0_div, 557 .num_parents = 4, 558 .ops = &clk_rcg2_ops, 559 }, 560}; 561 562static struct clk_rcg2 isense_clk_src = { 563 .cmd_rcgr = 0x4010, 564 .hid_width = 5, 565 .parent_map = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div_map, 566 .clkr.hw.init = &(struct clk_init_data){ 567 .name = "isense_clk_src", 568 .parent_names = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div, 569 .num_parents = 7, 570 .ops = &clk_rcg2_ops, 571 }, 572}; 573 574static const struct freq_tbl ftbl_rbcpr_clk_src[] = { 575 F(19200000, P_XO, 1, 0, 0), 576 F(50000000, P_GPLL0, 12, 0, 0), 577 { } 578}; 579 580static struct clk_rcg2 rbcpr_clk_src = { 581 .cmd_rcgr = 0x4060, 582 .hid_width = 5, 583 .parent_map = mmss_xo_mmpll0_gpll0_gpll0_div_map, 584 .freq_tbl = ftbl_rbcpr_clk_src, 585 .clkr.hw.init = &(struct clk_init_data){ 586 .name = "rbcpr_clk_src", 587 .parent_names = mmss_xo_mmpll0_gpll0_gpll0_div, 588 .num_parents = 4, 589 .ops = &clk_rcg2_ops, 590 }, 591}; 592 593static const struct freq_tbl ftbl_video_core_clk_src[] = { 594 F(75000000, P_GPLL0_DIV, 4, 0, 0), 595 F(150000000, P_GPLL0, 4, 0, 0), 596 F(346666667, P_MMPLL3, 3, 0, 0), 597 F(520000000, P_MMPLL3, 2, 0, 0), 598 { } 599}; 600 601static struct clk_rcg2 video_core_clk_src = { 602 .cmd_rcgr = 0x1000, 603 .mnd_width = 8, 604 .hid_width = 5, 605 .parent_map = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div_map, 606 .freq_tbl = ftbl_video_core_clk_src, 607 .clkr.hw.init = &(struct clk_init_data){ 608 .name = "video_core_clk_src", 609 .parent_names = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div, 610 .num_parents = 5, 611 .ops = &clk_rcg2_ops, 612 }, 613}; 614 615static struct clk_rcg2 video_subcore0_clk_src = { 616 .cmd_rcgr = 0x1060, 617 .mnd_width = 8, 618 .hid_width = 5, 619 .parent_map = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div_map, 620 .freq_tbl = ftbl_video_core_clk_src, 621 .clkr.hw.init = &(struct clk_init_data){ 622 .name = "video_subcore0_clk_src", 623 .parent_names = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div, 624 .num_parents = 5, 625 .ops = &clk_rcg2_ops, 626 }, 627}; 628 629static struct clk_rcg2 video_subcore1_clk_src = { 630 .cmd_rcgr = 0x1080, 631 .mnd_width = 8, 632 .hid_width = 5, 633 .parent_map = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div_map, 634 .freq_tbl = ftbl_video_core_clk_src, 635 .clkr.hw.init = &(struct clk_init_data){ 636 .name = "video_subcore1_clk_src", 637 .parent_names = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div, 638 .num_parents = 5, 639 .ops = &clk_rcg2_ops, 640 }, 641}; 642 643static struct clk_rcg2 pclk0_clk_src = { 644 .cmd_rcgr = 0x2000, 645 .mnd_width = 8, 646 .hid_width = 5, 647 .parent_map = mmss_xo_dsi0pll_dsi1pll_map, 648 .clkr.hw.init = &(struct clk_init_data){ 649 .name = "pclk0_clk_src", 650 .parent_names = mmss_xo_dsi0pll_dsi1pll, 651 .num_parents = 3, 652 .ops = &clk_pixel_ops, 653 .flags = CLK_SET_RATE_PARENT, 654 }, 655}; 656 657static struct clk_rcg2 pclk1_clk_src = { 658 .cmd_rcgr = 0x2020, 659 .mnd_width = 8, 660 .hid_width = 5, 661 .parent_map = mmss_xo_dsi0pll_dsi1pll_map, 662 .clkr.hw.init = &(struct clk_init_data){ 663 .name = "pclk1_clk_src", 664 .parent_names = mmss_xo_dsi0pll_dsi1pll, 665 .num_parents = 3, 666 .ops = &clk_pixel_ops, 667 .flags = CLK_SET_RATE_PARENT, 668 }, 669}; 670 671static const struct freq_tbl ftbl_mdp_clk_src[] = { 672 F(85714286, P_GPLL0, 7, 0, 0), 673 F(100000000, P_GPLL0, 6, 0, 0), 674 F(150000000, P_GPLL0, 4, 0, 0), 675 F(171428571, P_GPLL0, 3.5, 0, 0), 676 F(200000000, P_GPLL0, 3, 0, 0), 677 F(275000000, P_MMPLL5, 3, 0, 0), 678 F(300000000, P_GPLL0, 2, 0, 0), 679 F(330000000, P_MMPLL5, 2.5, 0, 0), 680 F(412500000, P_MMPLL5, 2, 0, 0), 681 { } 682}; 683 684static struct clk_rcg2 mdp_clk_src = { 685 .cmd_rcgr = 0x2040, 686 .hid_width = 5, 687 .parent_map = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map, 688 .freq_tbl = ftbl_mdp_clk_src, 689 .clkr.hw.init = &(struct clk_init_data){ 690 .name = "mdp_clk_src", 691 .parent_names = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div, 692 .num_parents = 5, 693 .ops = &clk_rcg2_ops, 694 }, 695}; 696 697static struct freq_tbl extpclk_freq_tbl[] = { 698 { .src = P_HDMIPLL }, 699 { } 700}; 701 702static struct clk_rcg2 extpclk_clk_src = { 703 .cmd_rcgr = 0x2060, 704 .hid_width = 5, 705 .parent_map = mmss_xo_hdmi_map, 706 .freq_tbl = extpclk_freq_tbl, 707 .clkr.hw.init = &(struct clk_init_data){ 708 .name = "extpclk_clk_src", 709 .parent_names = mmss_xo_hdmi, 710 .num_parents = 2, 711 .ops = &clk_byte_ops, 712 .flags = CLK_SET_RATE_PARENT, 713 }, 714}; 715 716static struct freq_tbl ftbl_mdss_vsync_clk[] = { 717 F(19200000, P_XO, 1, 0, 0), 718 { } 719}; 720 721static struct clk_rcg2 vsync_clk_src = { 722 .cmd_rcgr = 0x2080, 723 .hid_width = 5, 724 .parent_map = mmss_xo_gpll0_gpll0_div_map, 725 .freq_tbl = ftbl_mdss_vsync_clk, 726 .clkr.hw.init = &(struct clk_init_data){ 727 .name = "vsync_clk_src", 728 .parent_names = mmss_xo_gpll0_gpll0_div, 729 .num_parents = 3, 730 .ops = &clk_rcg2_ops, 731 }, 732}; 733 734static struct freq_tbl ftbl_mdss_hdmi_clk[] = { 735 F(19200000, P_XO, 1, 0, 0), 736 { } 737}; 738 739static struct clk_rcg2 hdmi_clk_src = { 740 .cmd_rcgr = 0x2100, 741 .hid_width = 5, 742 .parent_map = mmss_xo_gpll0_gpll0_div_map, 743 .freq_tbl = ftbl_mdss_hdmi_clk, 744 .clkr.hw.init = &(struct clk_init_data){ 745 .name = "hdmi_clk_src", 746 .parent_names = mmss_xo_gpll0_gpll0_div, 747 .num_parents = 3, 748 .ops = &clk_rcg2_ops, 749 }, 750}; 751 752static struct clk_rcg2 byte0_clk_src = { 753 .cmd_rcgr = 0x2120, 754 .hid_width = 5, 755 .parent_map = mmss_xo_dsibyte_map, 756 .clkr.hw.init = &(struct clk_init_data){ 757 .name = "byte0_clk_src", 758 .parent_names = mmss_xo_dsibyte, 759 .num_parents = 3, 760 .ops = &clk_byte2_ops, 761 .flags = CLK_SET_RATE_PARENT, 762 }, 763}; 764 765static struct clk_rcg2 byte1_clk_src = { 766 .cmd_rcgr = 0x2140, 767 .hid_width = 5, 768 .parent_map = mmss_xo_dsibyte_map, 769 .clkr.hw.init = &(struct clk_init_data){ 770 .name = "byte1_clk_src", 771 .parent_names = mmss_xo_dsibyte, 772 .num_parents = 3, 773 .ops = &clk_byte2_ops, 774 .flags = CLK_SET_RATE_PARENT, 775 }, 776}; 777 778static struct freq_tbl ftbl_mdss_esc0_1_clk[] = { 779 F(19200000, P_XO, 1, 0, 0), 780 { } 781}; 782 783static struct clk_rcg2 esc0_clk_src = { 784 .cmd_rcgr = 0x2160, 785 .hid_width = 5, 786 .parent_map = mmss_xo_dsibyte_map, 787 .freq_tbl = ftbl_mdss_esc0_1_clk, 788 .clkr.hw.init = &(struct clk_init_data){ 789 .name = "esc0_clk_src", 790 .parent_names = mmss_xo_dsibyte, 791 .num_parents = 3, 792 .ops = &clk_rcg2_ops, 793 }, 794}; 795 796static struct clk_rcg2 esc1_clk_src = { 797 .cmd_rcgr = 0x2180, 798 .hid_width = 5, 799 .parent_map = mmss_xo_dsibyte_map, 800 .freq_tbl = ftbl_mdss_esc0_1_clk, 801 .clkr.hw.init = &(struct clk_init_data){ 802 .name = "esc1_clk_src", 803 .parent_names = mmss_xo_dsibyte, 804 .num_parents = 3, 805 .ops = &clk_rcg2_ops, 806 }, 807}; 808 809static const struct freq_tbl ftbl_camss_gp0_clk_src[] = { 810 F(10000, P_XO, 16, 1, 120), 811 F(24000, P_XO, 16, 1, 50), 812 F(6000000, P_GPLL0_DIV, 10, 1, 5), 813 F(12000000, P_GPLL0_DIV, 1, 1, 25), 814 F(13000000, P_GPLL0_DIV, 2, 13, 150), 815 F(24000000, P_GPLL0_DIV, 1, 2, 25), 816 { } 817}; 818 819static struct clk_rcg2 camss_gp0_clk_src = { 820 .cmd_rcgr = 0x3420, 821 .mnd_width = 8, 822 .hid_width = 5, 823 .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map, 824 .freq_tbl = ftbl_camss_gp0_clk_src, 825 .clkr.hw.init = &(struct clk_init_data){ 826 .name = "camss_gp0_clk_src", 827 .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, 828 .num_parents = 5, 829 .ops = &clk_rcg2_ops, 830 }, 831}; 832 833static struct clk_rcg2 camss_gp1_clk_src = { 834 .cmd_rcgr = 0x3450, 835 .mnd_width = 8, 836 .hid_width = 5, 837 .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map, 838 .freq_tbl = ftbl_camss_gp0_clk_src, 839 .clkr.hw.init = &(struct clk_init_data){ 840 .name = "camss_gp1_clk_src", 841 .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, 842 .num_parents = 5, 843 .ops = &clk_rcg2_ops, 844 }, 845}; 846 847static const struct freq_tbl ftbl_mclk0_clk_src[] = { 848 F(4800000, P_XO, 4, 0, 0), 849 F(6000000, P_GPLL0_DIV, 10, 1, 5), 850 F(8000000, P_GPLL0_DIV, 1, 2, 75), 851 F(9600000, P_XO, 2, 0, 0), 852 F(16666667, P_GPLL0_DIV, 2, 1, 9), 853 F(19200000, P_XO, 1, 0, 0), 854 F(24000000, P_GPLL0_DIV, 1, 2, 25), 855 F(33333333, P_GPLL0_DIV, 1, 1, 9), 856 F(48000000, P_GPLL0, 1, 2, 25), 857 F(66666667, P_GPLL0, 1, 1, 9), 858 { } 859}; 860 861static struct clk_rcg2 mclk0_clk_src = { 862 .cmd_rcgr = 0x3360, 863 .mnd_width = 8, 864 .hid_width = 5, 865 .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map, 866 .freq_tbl = ftbl_mclk0_clk_src, 867 .clkr.hw.init = &(struct clk_init_data){ 868 .name = "mclk0_clk_src", 869 .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, 870 .num_parents = 5, 871 .ops = &clk_rcg2_ops, 872 }, 873}; 874 875static struct clk_rcg2 mclk1_clk_src = { 876 .cmd_rcgr = 0x3390, 877 .mnd_width = 8, 878 .hid_width = 5, 879 .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map, 880 .freq_tbl = ftbl_mclk0_clk_src, 881 .clkr.hw.init = &(struct clk_init_data){ 882 .name = "mclk1_clk_src", 883 .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, 884 .num_parents = 5, 885 .ops = &clk_rcg2_ops, 886 }, 887}; 888 889static struct clk_rcg2 mclk2_clk_src = { 890 .cmd_rcgr = 0x33c0, 891 .mnd_width = 8, 892 .hid_width = 5, 893 .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map, 894 .freq_tbl = ftbl_mclk0_clk_src, 895 .clkr.hw.init = &(struct clk_init_data){ 896 .name = "mclk2_clk_src", 897 .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, 898 .num_parents = 5, 899 .ops = &clk_rcg2_ops, 900 }, 901}; 902 903static struct clk_rcg2 mclk3_clk_src = { 904 .cmd_rcgr = 0x33f0, 905 .mnd_width = 8, 906 .hid_width = 5, 907 .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map, 908 .freq_tbl = ftbl_mclk0_clk_src, 909 .clkr.hw.init = &(struct clk_init_data){ 910 .name = "mclk3_clk_src", 911 .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, 912 .num_parents = 5, 913 .ops = &clk_rcg2_ops, 914 }, 915}; 916 917static const struct freq_tbl ftbl_cci_clk_src[] = { 918 F(19200000, P_XO, 1, 0, 0), 919 F(37500000, P_GPLL0, 16, 0, 0), 920 F(50000000, P_GPLL0, 12, 0, 0), 921 F(100000000, P_GPLL0, 6, 0, 0), 922 { } 923}; 924 925static struct clk_rcg2 cci_clk_src = { 926 .cmd_rcgr = 0x3300, 927 .mnd_width = 8, 928 .hid_width = 5, 929 .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map, 930 .freq_tbl = ftbl_cci_clk_src, 931 .clkr.hw.init = &(struct clk_init_data){ 932 .name = "cci_clk_src", 933 .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, 934 .num_parents = 5, 935 .ops = &clk_rcg2_ops, 936 }, 937}; 938 939static const struct freq_tbl ftbl_csi0phytimer_clk_src[] = { 940 F(100000000, P_GPLL0_DIV, 3, 0, 0), 941 F(200000000, P_GPLL0, 3, 0, 0), 942 F(266666667, P_MMPLL0, 3, 0, 0), 943 { } 944}; 945 946static struct clk_rcg2 csi0phytimer_clk_src = { 947 .cmd_rcgr = 0x3000, 948 .hid_width = 5, 949 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 950 .freq_tbl = ftbl_csi0phytimer_clk_src, 951 .clkr.hw.init = &(struct clk_init_data){ 952 .name = "csi0phytimer_clk_src", 953 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 954 .num_parents = 7, 955 .ops = &clk_rcg2_ops, 956 }, 957}; 958 959static struct clk_rcg2 csi1phytimer_clk_src = { 960 .cmd_rcgr = 0x3030, 961 .hid_width = 5, 962 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 963 .freq_tbl = ftbl_csi0phytimer_clk_src, 964 .clkr.hw.init = &(struct clk_init_data){ 965 .name = "csi1phytimer_clk_src", 966 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 967 .num_parents = 7, 968 .ops = &clk_rcg2_ops, 969 }, 970}; 971 972static struct clk_rcg2 csi2phytimer_clk_src = { 973 .cmd_rcgr = 0x3060, 974 .hid_width = 5, 975 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 976 .freq_tbl = ftbl_csi0phytimer_clk_src, 977 .clkr.hw.init = &(struct clk_init_data){ 978 .name = "csi2phytimer_clk_src", 979 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 980 .num_parents = 7, 981 .ops = &clk_rcg2_ops, 982 }, 983}; 984 985static const struct freq_tbl ftbl_csiphy0_3p_clk_src[] = { 986 F(100000000, P_GPLL0_DIV, 3, 0, 0), 987 F(200000000, P_GPLL0, 3, 0, 0), 988 F(320000000, P_MMPLL4, 3, 0, 0), 989 F(384000000, P_MMPLL4, 2.5, 0, 0), 990 { } 991}; 992 993static struct clk_rcg2 csiphy0_3p_clk_src = { 994 .cmd_rcgr = 0x3240, 995 .hid_width = 5, 996 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 997 .freq_tbl = ftbl_csiphy0_3p_clk_src, 998 .clkr.hw.init = &(struct clk_init_data){ 999 .name = "csiphy0_3p_clk_src", 1000 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1001 .num_parents = 7, 1002 .ops = &clk_rcg2_ops, 1003 }, 1004}; 1005 1006static struct clk_rcg2 csiphy1_3p_clk_src = { 1007 .cmd_rcgr = 0x3260, 1008 .hid_width = 5, 1009 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1010 .freq_tbl = ftbl_csiphy0_3p_clk_src, 1011 .clkr.hw.init = &(struct clk_init_data){ 1012 .name = "csiphy1_3p_clk_src", 1013 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1014 .num_parents = 7, 1015 .ops = &clk_rcg2_ops, 1016 }, 1017}; 1018 1019static struct clk_rcg2 csiphy2_3p_clk_src = { 1020 .cmd_rcgr = 0x3280, 1021 .hid_width = 5, 1022 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1023 .freq_tbl = ftbl_csiphy0_3p_clk_src, 1024 .clkr.hw.init = &(struct clk_init_data){ 1025 .name = "csiphy2_3p_clk_src", 1026 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1027 .num_parents = 7, 1028 .ops = &clk_rcg2_ops, 1029 }, 1030}; 1031 1032static const struct freq_tbl ftbl_jpeg0_clk_src[] = { 1033 F(75000000, P_GPLL0_DIV, 4, 0, 0), 1034 F(150000000, P_GPLL0, 4, 0, 0), 1035 F(228571429, P_MMPLL0, 3.5, 0, 0), 1036 F(266666667, P_MMPLL0, 3, 0, 0), 1037 F(320000000, P_MMPLL0, 2.5, 0, 0), 1038 F(480000000, P_MMPLL4, 2, 0, 0), 1039 { } 1040}; 1041 1042static struct clk_rcg2 jpeg0_clk_src = { 1043 .cmd_rcgr = 0x3500, 1044 .hid_width = 5, 1045 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1046 .freq_tbl = ftbl_jpeg0_clk_src, 1047 .clkr.hw.init = &(struct clk_init_data){ 1048 .name = "jpeg0_clk_src", 1049 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1050 .num_parents = 7, 1051 .ops = &clk_rcg2_ops, 1052 }, 1053}; 1054 1055static const struct freq_tbl ftbl_jpeg2_clk_src[] = { 1056 F(75000000, P_GPLL0_DIV, 4, 0, 0), 1057 F(150000000, P_GPLL0, 4, 0, 0), 1058 F(228571429, P_MMPLL0, 3.5, 0, 0), 1059 F(266666667, P_MMPLL0, 3, 0, 0), 1060 F(320000000, P_MMPLL0, 2.5, 0, 0), 1061 { } 1062}; 1063 1064static struct clk_rcg2 jpeg2_clk_src = { 1065 .cmd_rcgr = 0x3540, 1066 .hid_width = 5, 1067 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1068 .freq_tbl = ftbl_jpeg2_clk_src, 1069 .clkr.hw.init = &(struct clk_init_data){ 1070 .name = "jpeg2_clk_src", 1071 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1072 .num_parents = 7, 1073 .ops = &clk_rcg2_ops, 1074 }, 1075}; 1076 1077static struct clk_rcg2 jpeg_dma_clk_src = { 1078 .cmd_rcgr = 0x3560, 1079 .hid_width = 5, 1080 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1081 .freq_tbl = ftbl_jpeg0_clk_src, 1082 .clkr.hw.init = &(struct clk_init_data){ 1083 .name = "jpeg_dma_clk_src", 1084 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1085 .num_parents = 7, 1086 .ops = &clk_rcg2_ops, 1087 }, 1088}; 1089 1090static const struct freq_tbl ftbl_vfe0_clk_src[] = { 1091 F(75000000, P_GPLL0_DIV, 4, 0, 0), 1092 F(100000000, P_GPLL0_DIV, 3, 0, 0), 1093 F(300000000, P_GPLL0, 2, 0, 0), 1094 F(320000000, P_MMPLL0, 2.5, 0, 0), 1095 F(480000000, P_MMPLL4, 2, 0, 0), 1096 F(600000000, P_GPLL0, 1, 0, 0), 1097 { } 1098}; 1099 1100static struct clk_rcg2 vfe0_clk_src = { 1101 .cmd_rcgr = 0x3600, 1102 .hid_width = 5, 1103 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1104 .freq_tbl = ftbl_vfe0_clk_src, 1105 .clkr.hw.init = &(struct clk_init_data){ 1106 .name = "vfe0_clk_src", 1107 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1108 .num_parents = 7, 1109 .ops = &clk_rcg2_ops, 1110 }, 1111}; 1112 1113static struct clk_rcg2 vfe1_clk_src = { 1114 .cmd_rcgr = 0x3620, 1115 .hid_width = 5, 1116 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1117 .freq_tbl = ftbl_vfe0_clk_src, 1118 .clkr.hw.init = &(struct clk_init_data){ 1119 .name = "vfe1_clk_src", 1120 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1121 .num_parents = 7, 1122 .ops = &clk_rcg2_ops, 1123 }, 1124}; 1125 1126static const struct freq_tbl ftbl_cpp_clk_src[] = { 1127 F(100000000, P_GPLL0_DIV, 3, 0, 0), 1128 F(200000000, P_GPLL0, 3, 0, 0), 1129 F(320000000, P_MMPLL0, 2.5, 0, 0), 1130 F(480000000, P_MMPLL4, 2, 0, 0), 1131 F(640000000, P_MMPLL4, 1.5, 0, 0), 1132 { } 1133}; 1134 1135static struct clk_rcg2 cpp_clk_src = { 1136 .cmd_rcgr = 0x3640, 1137 .hid_width = 5, 1138 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1139 .freq_tbl = ftbl_cpp_clk_src, 1140 .clkr.hw.init = &(struct clk_init_data){ 1141 .name = "cpp_clk_src", 1142 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1143 .num_parents = 7, 1144 .ops = &clk_rcg2_ops, 1145 }, 1146}; 1147 1148static const struct freq_tbl ftbl_csi0_clk_src[] = { 1149 F(100000000, P_GPLL0_DIV, 3, 0, 0), 1150 F(200000000, P_GPLL0, 3, 0, 0), 1151 F(266666667, P_MMPLL0, 3, 0, 0), 1152 F(480000000, P_MMPLL4, 2, 0, 0), 1153 F(600000000, P_GPLL0, 1, 0, 0), 1154 { } 1155}; 1156 1157static struct clk_rcg2 csi0_clk_src = { 1158 .cmd_rcgr = 0x3090, 1159 .hid_width = 5, 1160 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1161 .freq_tbl = ftbl_csi0_clk_src, 1162 .clkr.hw.init = &(struct clk_init_data){ 1163 .name = "csi0_clk_src", 1164 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1165 .num_parents = 7, 1166 .ops = &clk_rcg2_ops, 1167 }, 1168}; 1169 1170static struct clk_rcg2 csi1_clk_src = { 1171 .cmd_rcgr = 0x3100, 1172 .hid_width = 5, 1173 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1174 .freq_tbl = ftbl_csi0_clk_src, 1175 .clkr.hw.init = &(struct clk_init_data){ 1176 .name = "csi1_clk_src", 1177 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1178 .num_parents = 7, 1179 .ops = &clk_rcg2_ops, 1180 }, 1181}; 1182 1183static struct clk_rcg2 csi2_clk_src = { 1184 .cmd_rcgr = 0x3160, 1185 .hid_width = 5, 1186 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1187 .freq_tbl = ftbl_csi0_clk_src, 1188 .clkr.hw.init = &(struct clk_init_data){ 1189 .name = "csi2_clk_src", 1190 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1191 .num_parents = 7, 1192 .ops = &clk_rcg2_ops, 1193 }, 1194}; 1195 1196static struct clk_rcg2 csi3_clk_src = { 1197 .cmd_rcgr = 0x31c0, 1198 .hid_width = 5, 1199 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1200 .freq_tbl = ftbl_csi0_clk_src, 1201 .clkr.hw.init = &(struct clk_init_data){ 1202 .name = "csi3_clk_src", 1203 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1204 .num_parents = 7, 1205 .ops = &clk_rcg2_ops, 1206 }, 1207}; 1208 1209static const struct freq_tbl ftbl_fd_core_clk_src[] = { 1210 F(100000000, P_GPLL0_DIV, 3, 0, 0), 1211 F(200000000, P_GPLL0, 3, 0, 0), 1212 F(400000000, P_MMPLL0, 2, 0, 0), 1213 { } 1214}; 1215 1216static struct clk_rcg2 fd_core_clk_src = { 1217 .cmd_rcgr = 0x3b00, 1218 .hid_width = 5, 1219 .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map, 1220 .freq_tbl = ftbl_fd_core_clk_src, 1221 .clkr.hw.init = &(struct clk_init_data){ 1222 .name = "fd_core_clk_src", 1223 .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, 1224 .num_parents = 5, 1225 .ops = &clk_rcg2_ops, 1226 }, 1227}; 1228 1229static struct clk_branch mmss_mmagic_ahb_clk = { 1230 .halt_reg = 0x5024, 1231 .clkr = { 1232 .enable_reg = 0x5024, 1233 .enable_mask = BIT(0), 1234 .hw.init = &(struct clk_init_data){ 1235 .name = "mmss_mmagic_ahb_clk", 1236 .parent_names = (const char *[]){ "ahb_clk_src" }, 1237 .num_parents = 1, 1238 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 1239 .ops = &clk_branch2_ops, 1240 }, 1241 }, 1242}; 1243 1244static struct clk_branch mmss_mmagic_cfg_ahb_clk = { 1245 .halt_reg = 0x5054, 1246 .clkr = { 1247 .enable_reg = 0x5054, 1248 .enable_mask = BIT(0), 1249 .hw.init = &(struct clk_init_data){ 1250 .name = "mmss_mmagic_cfg_ahb_clk", 1251 .parent_names = (const char *[]){ "ahb_clk_src" }, 1252 .num_parents = 1, 1253 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 1254 .ops = &clk_branch2_ops, 1255 }, 1256 }, 1257}; 1258 1259static struct clk_branch mmss_misc_ahb_clk = { 1260 .halt_reg = 0x5018, 1261 .clkr = { 1262 .enable_reg = 0x5018, 1263 .enable_mask = BIT(0), 1264 .hw.init = &(struct clk_init_data){ 1265 .name = "mmss_misc_ahb_clk", 1266 .parent_names = (const char *[]){ "ahb_clk_src" }, 1267 .num_parents = 1, 1268 .flags = CLK_SET_RATE_PARENT, 1269 .ops = &clk_branch2_ops, 1270 }, 1271 }, 1272}; 1273 1274static struct clk_branch mmss_misc_cxo_clk = { 1275 .halt_reg = 0x5014, 1276 .clkr = { 1277 .enable_reg = 0x5014, 1278 .enable_mask = BIT(0), 1279 .hw.init = &(struct clk_init_data){ 1280 .name = "mmss_misc_cxo_clk", 1281 .parent_names = (const char *[]){ "xo" }, 1282 .num_parents = 1, 1283 .ops = &clk_branch2_ops, 1284 }, 1285 }, 1286}; 1287 1288static struct clk_branch mmss_mmagic_maxi_clk = { 1289 .halt_reg = 0x5074, 1290 .clkr = { 1291 .enable_reg = 0x5074, 1292 .enable_mask = BIT(0), 1293 .hw.init = &(struct clk_init_data){ 1294 .name = "mmss_mmagic_maxi_clk", 1295 .parent_names = (const char *[]){ "maxi_clk_src" }, 1296 .num_parents = 1, 1297 .flags = CLK_SET_RATE_PARENT, 1298 .ops = &clk_branch2_ops, 1299 }, 1300 }, 1301}; 1302 1303static struct clk_branch mmagic_camss_axi_clk = { 1304 .halt_reg = 0x3c44, 1305 .clkr = { 1306 .enable_reg = 0x3c44, 1307 .enable_mask = BIT(0), 1308 .hw.init = &(struct clk_init_data){ 1309 .name = "mmagic_camss_axi_clk", 1310 .parent_names = (const char *[]){ "axi_clk_src" }, 1311 .num_parents = 1, 1312 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 1313 .ops = &clk_branch2_ops, 1314 }, 1315 }, 1316}; 1317 1318static struct clk_branch mmagic_camss_noc_cfg_ahb_clk = { 1319 .halt_reg = 0x3c48, 1320 .clkr = { 1321 .enable_reg = 0x3c48, 1322 .enable_mask = BIT(0), 1323 .hw.init = &(struct clk_init_data){ 1324 .name = "mmagic_camss_noc_cfg_ahb_clk", 1325 .parent_names = (const char *[]){ "gcc_mmss_noc_cfg_ahb_clk" }, 1326 .num_parents = 1, 1327 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 1328 .ops = &clk_branch2_ops, 1329 }, 1330 }, 1331}; 1332 1333static struct clk_branch smmu_vfe_ahb_clk = { 1334 .halt_reg = 0x3c04, 1335 .clkr = { 1336 .enable_reg = 0x3c04, 1337 .enable_mask = BIT(0), 1338 .hw.init = &(struct clk_init_data){ 1339 .name = "smmu_vfe_ahb_clk", 1340 .parent_names = (const char *[]){ "ahb_clk_src" }, 1341 .num_parents = 1, 1342 .flags = CLK_SET_RATE_PARENT, 1343 .ops = &clk_branch2_ops, 1344 }, 1345 }, 1346}; 1347 1348static struct clk_branch smmu_vfe_axi_clk = { 1349 .halt_reg = 0x3c08, 1350 .clkr = { 1351 .enable_reg = 0x3c08, 1352 .enable_mask = BIT(0), 1353 .hw.init = &(struct clk_init_data){ 1354 .name = "smmu_vfe_axi_clk", 1355 .parent_names = (const char *[]){ "axi_clk_src" }, 1356 .num_parents = 1, 1357 .flags = CLK_SET_RATE_PARENT, 1358 .ops = &clk_branch2_ops, 1359 }, 1360 }, 1361}; 1362 1363static struct clk_branch smmu_cpp_ahb_clk = { 1364 .halt_reg = 0x3c14, 1365 .clkr = { 1366 .enable_reg = 0x3c14, 1367 .enable_mask = BIT(0), 1368 .hw.init = &(struct clk_init_data){ 1369 .name = "smmu_cpp_ahb_clk", 1370 .parent_names = (const char *[]){ "ahb_clk_src" }, 1371 .num_parents = 1, 1372 .flags = CLK_SET_RATE_PARENT, 1373 .ops = &clk_branch2_ops, 1374 }, 1375 }, 1376}; 1377 1378static struct clk_branch smmu_cpp_axi_clk = { 1379 .halt_reg = 0x3c18, 1380 .clkr = { 1381 .enable_reg = 0x3c18, 1382 .enable_mask = BIT(0), 1383 .hw.init = &(struct clk_init_data){ 1384 .name = "smmu_cpp_axi_clk", 1385 .parent_names = (const char *[]){ "axi_clk_src" }, 1386 .num_parents = 1, 1387 .flags = CLK_SET_RATE_PARENT, 1388 .ops = &clk_branch2_ops, 1389 }, 1390 }, 1391}; 1392 1393static struct clk_branch smmu_jpeg_ahb_clk = { 1394 .halt_reg = 0x3c24, 1395 .clkr = { 1396 .enable_reg = 0x3c24, 1397 .enable_mask = BIT(0), 1398 .hw.init = &(struct clk_init_data){ 1399 .name = "smmu_jpeg_ahb_clk", 1400 .parent_names = (const char *[]){ "ahb_clk_src" }, 1401 .num_parents = 1, 1402 .flags = CLK_SET_RATE_PARENT, 1403 .ops = &clk_branch2_ops, 1404 }, 1405 }, 1406}; 1407 1408static struct clk_branch smmu_jpeg_axi_clk = { 1409 .halt_reg = 0x3c28, 1410 .clkr = { 1411 .enable_reg = 0x3c28, 1412 .enable_mask = BIT(0), 1413 .hw.init = &(struct clk_init_data){ 1414 .name = "smmu_jpeg_axi_clk", 1415 .parent_names = (const char *[]){ "axi_clk_src" }, 1416 .num_parents = 1, 1417 .flags = CLK_SET_RATE_PARENT, 1418 .ops = &clk_branch2_ops, 1419 }, 1420 }, 1421}; 1422 1423static struct clk_branch mmagic_mdss_axi_clk = { 1424 .halt_reg = 0x2474, 1425 .clkr = { 1426 .enable_reg = 0x2474, 1427 .enable_mask = BIT(0), 1428 .hw.init = &(struct clk_init_data){ 1429 .name = "mmagic_mdss_axi_clk", 1430 .parent_names = (const char *[]){ "axi_clk_src" }, 1431 .num_parents = 1, 1432 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 1433 .ops = &clk_branch2_ops, 1434 }, 1435 }, 1436}; 1437 1438static struct clk_branch mmagic_mdss_noc_cfg_ahb_clk = { 1439 .halt_reg = 0x2478, 1440 .clkr = { 1441 .enable_reg = 0x2478, 1442 .enable_mask = BIT(0), 1443 .hw.init = &(struct clk_init_data){ 1444 .name = "mmagic_mdss_noc_cfg_ahb_clk", 1445 .parent_names = (const char *[]){ "gcc_mmss_noc_cfg_ahb_clk" }, 1446 .num_parents = 1, 1447 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 1448 .ops = &clk_branch2_ops, 1449 }, 1450 }, 1451}; 1452 1453static struct clk_branch smmu_rot_ahb_clk = { 1454 .halt_reg = 0x2444, 1455 .clkr = { 1456 .enable_reg = 0x2444, 1457 .enable_mask = BIT(0), 1458 .hw.init = &(struct clk_init_data){ 1459 .name = "smmu_rot_ahb_clk", 1460 .parent_names = (const char *[]){ "ahb_clk_src" }, 1461 .num_parents = 1, 1462 .flags = CLK_SET_RATE_PARENT, 1463 .ops = &clk_branch2_ops, 1464 }, 1465 }, 1466}; 1467 1468static struct clk_branch smmu_rot_axi_clk = { 1469 .halt_reg = 0x2448, 1470 .clkr = { 1471 .enable_reg = 0x2448, 1472 .enable_mask = BIT(0), 1473 .hw.init = &(struct clk_init_data){ 1474 .name = "smmu_rot_axi_clk", 1475 .parent_names = (const char *[]){ "axi_clk_src" }, 1476 .num_parents = 1, 1477 .flags = CLK_SET_RATE_PARENT, 1478 .ops = &clk_branch2_ops, 1479 }, 1480 }, 1481}; 1482 1483static struct clk_branch smmu_mdp_ahb_clk = { 1484 .halt_reg = 0x2454, 1485 .clkr = { 1486 .enable_reg = 0x2454, 1487 .enable_mask = BIT(0), 1488 .hw.init = &(struct clk_init_data){ 1489 .name = "smmu_mdp_ahb_clk", 1490 .parent_names = (const char *[]){ "ahb_clk_src" }, 1491 .num_parents = 1, 1492 .flags = CLK_SET_RATE_PARENT, 1493 .ops = &clk_branch2_ops, 1494 }, 1495 }, 1496}; 1497 1498static struct clk_branch smmu_mdp_axi_clk = { 1499 .halt_reg = 0x2458, 1500 .clkr = { 1501 .enable_reg = 0x2458, 1502 .enable_mask = BIT(0), 1503 .hw.init = &(struct clk_init_data){ 1504 .name = "smmu_mdp_axi_clk", 1505 .parent_names = (const char *[]){ "axi_clk_src" }, 1506 .num_parents = 1, 1507 .flags = CLK_SET_RATE_PARENT, 1508 .ops = &clk_branch2_ops, 1509 }, 1510 }, 1511}; 1512 1513static struct clk_branch mmagic_video_axi_clk = { 1514 .halt_reg = 0x1194, 1515 .clkr = { 1516 .enable_reg = 0x1194, 1517 .enable_mask = BIT(0), 1518 .hw.init = &(struct clk_init_data){ 1519 .name = "mmagic_video_axi_clk", 1520 .parent_names = (const char *[]){ "axi_clk_src" }, 1521 .num_parents = 1, 1522 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 1523 .ops = &clk_branch2_ops, 1524 }, 1525 }, 1526}; 1527 1528static struct clk_branch mmagic_video_noc_cfg_ahb_clk = { 1529 .halt_reg = 0x1198, 1530 .clkr = { 1531 .enable_reg = 0x1198, 1532 .enable_mask = BIT(0), 1533 .hw.init = &(struct clk_init_data){ 1534 .name = "mmagic_video_noc_cfg_ahb_clk", 1535 .parent_names = (const char *[]){ "gcc_mmss_noc_cfg_ahb_clk" }, 1536 .num_parents = 1, 1537 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 1538 .ops = &clk_branch2_ops, 1539 }, 1540 }, 1541}; 1542 1543static struct clk_branch smmu_video_ahb_clk = { 1544 .halt_reg = 0x1174, 1545 .clkr = { 1546 .enable_reg = 0x1174, 1547 .enable_mask = BIT(0), 1548 .hw.init = &(struct clk_init_data){ 1549 .name = "smmu_video_ahb_clk", 1550 .parent_names = (const char *[]){ "ahb_clk_src" }, 1551 .num_parents = 1, 1552 .flags = CLK_SET_RATE_PARENT, 1553 .ops = &clk_branch2_ops, 1554 }, 1555 }, 1556}; 1557 1558static struct clk_branch smmu_video_axi_clk = { 1559 .halt_reg = 0x1178, 1560 .clkr = { 1561 .enable_reg = 0x1178, 1562 .enable_mask = BIT(0), 1563 .hw.init = &(struct clk_init_data){ 1564 .name = "smmu_video_axi_clk", 1565 .parent_names = (const char *[]){ "axi_clk_src" }, 1566 .num_parents = 1, 1567 .flags = CLK_SET_RATE_PARENT, 1568 .ops = &clk_branch2_ops, 1569 }, 1570 }, 1571}; 1572 1573static struct clk_branch mmagic_bimc_noc_cfg_ahb_clk = { 1574 .halt_reg = 0x5298, 1575 .clkr = { 1576 .enable_reg = 0x5298, 1577 .enable_mask = BIT(0), 1578 .hw.init = &(struct clk_init_data){ 1579 .name = "mmagic_bimc_noc_cfg_ahb_clk", 1580 .parent_names = (const char *[]){ "gcc_mmss_noc_cfg_ahb_clk" }, 1581 .num_parents = 1, 1582 .flags = CLK_SET_RATE_PARENT, 1583 .ops = &clk_branch2_ops, 1584 }, 1585 }, 1586}; 1587 1588static struct clk_branch gpu_gx_gfx3d_clk = { 1589 .halt_reg = 0x4028, 1590 .clkr = { 1591 .enable_reg = 0x4028, 1592 .enable_mask = BIT(0), 1593 .hw.init = &(struct clk_init_data){ 1594 .name = "gpu_gx_gfx3d_clk", 1595 .parent_names = (const char *[]){ "gfx3d_clk_src" }, 1596 .num_parents = 1, 1597 .flags = CLK_SET_RATE_PARENT, 1598 .ops = &clk_branch2_ops, 1599 }, 1600 }, 1601}; 1602 1603static struct clk_branch gpu_gx_rbbmtimer_clk = { 1604 .halt_reg = 0x40b0, 1605 .clkr = { 1606 .enable_reg = 0x40b0, 1607 .enable_mask = BIT(0), 1608 .hw.init = &(struct clk_init_data){ 1609 .name = "gpu_gx_rbbmtimer_clk", 1610 .parent_names = (const char *[]){ "rbbmtimer_clk_src" }, 1611 .num_parents = 1, 1612 .flags = CLK_SET_RATE_PARENT, 1613 .ops = &clk_branch2_ops, 1614 }, 1615 }, 1616}; 1617 1618static struct clk_branch gpu_ahb_clk = { 1619 .halt_reg = 0x403c, 1620 .clkr = { 1621 .enable_reg = 0x403c, 1622 .enable_mask = BIT(0), 1623 .hw.init = &(struct clk_init_data){ 1624 .name = "gpu_ahb_clk", 1625 .parent_names = (const char *[]){ "ahb_clk_src" }, 1626 .num_parents = 1, 1627 .flags = CLK_SET_RATE_PARENT, 1628 .ops = &clk_branch2_ops, 1629 }, 1630 }, 1631}; 1632 1633static struct clk_branch gpu_aon_isense_clk = { 1634 .halt_reg = 0x4044, 1635 .clkr = { 1636 .enable_reg = 0x4044, 1637 .enable_mask = BIT(0), 1638 .hw.init = &(struct clk_init_data){ 1639 .name = "gpu_aon_isense_clk", 1640 .parent_names = (const char *[]){ "isense_clk_src" }, 1641 .num_parents = 1, 1642 .flags = CLK_SET_RATE_PARENT, 1643 .ops = &clk_branch2_ops, 1644 }, 1645 }, 1646}; 1647 1648static struct clk_branch vmem_maxi_clk = { 1649 .halt_reg = 0x1204, 1650 .clkr = { 1651 .enable_reg = 0x1204, 1652 .enable_mask = BIT(0), 1653 .hw.init = &(struct clk_init_data){ 1654 .name = "vmem_maxi_clk", 1655 .parent_names = (const char *[]){ "maxi_clk_src" }, 1656 .num_parents = 1, 1657 .flags = CLK_SET_RATE_PARENT, 1658 .ops = &clk_branch2_ops, 1659 }, 1660 }, 1661}; 1662 1663static struct clk_branch vmem_ahb_clk = { 1664 .halt_reg = 0x1208, 1665 .clkr = { 1666 .enable_reg = 0x1208, 1667 .enable_mask = BIT(0), 1668 .hw.init = &(struct clk_init_data){ 1669 .name = "vmem_ahb_clk", 1670 .parent_names = (const char *[]){ "ahb_clk_src" }, 1671 .num_parents = 1, 1672 .flags = CLK_SET_RATE_PARENT, 1673 .ops = &clk_branch2_ops, 1674 }, 1675 }, 1676}; 1677 1678static struct clk_branch mmss_rbcpr_clk = { 1679 .halt_reg = 0x4084, 1680 .clkr = { 1681 .enable_reg = 0x4084, 1682 .enable_mask = BIT(0), 1683 .hw.init = &(struct clk_init_data){ 1684 .name = "mmss_rbcpr_clk", 1685 .parent_names = (const char *[]){ "rbcpr_clk_src" }, 1686 .num_parents = 1, 1687 .flags = CLK_SET_RATE_PARENT, 1688 .ops = &clk_branch2_ops, 1689 }, 1690 }, 1691}; 1692 1693static struct clk_branch mmss_rbcpr_ahb_clk = { 1694 .halt_reg = 0x4088, 1695 .clkr = { 1696 .enable_reg = 0x4088, 1697 .enable_mask = BIT(0), 1698 .hw.init = &(struct clk_init_data){ 1699 .name = "mmss_rbcpr_ahb_clk", 1700 .parent_names = (const char *[]){ "ahb_clk_src" }, 1701 .num_parents = 1, 1702 .flags = CLK_SET_RATE_PARENT, 1703 .ops = &clk_branch2_ops, 1704 }, 1705 }, 1706}; 1707 1708static struct clk_branch video_core_clk = { 1709 .halt_reg = 0x1028, 1710 .clkr = { 1711 .enable_reg = 0x1028, 1712 .enable_mask = BIT(0), 1713 .hw.init = &(struct clk_init_data){ 1714 .name = "video_core_clk", 1715 .parent_names = (const char *[]){ "video_core_clk_src" }, 1716 .num_parents = 1, 1717 .flags = CLK_SET_RATE_PARENT, 1718 .ops = &clk_branch2_ops, 1719 }, 1720 }, 1721}; 1722 1723static struct clk_branch video_axi_clk = { 1724 .halt_reg = 0x1034, 1725 .clkr = { 1726 .enable_reg = 0x1034, 1727 .enable_mask = BIT(0), 1728 .hw.init = &(struct clk_init_data){ 1729 .name = "video_axi_clk", 1730 .parent_names = (const char *[]){ "axi_clk_src" }, 1731 .num_parents = 1, 1732 .flags = CLK_SET_RATE_PARENT, 1733 .ops = &clk_branch2_ops, 1734 }, 1735 }, 1736}; 1737 1738static struct clk_branch video_maxi_clk = { 1739 .halt_reg = 0x1038, 1740 .clkr = { 1741 .enable_reg = 0x1038, 1742 .enable_mask = BIT(0), 1743 .hw.init = &(struct clk_init_data){ 1744 .name = "video_maxi_clk", 1745 .parent_names = (const char *[]){ "maxi_clk_src" }, 1746 .num_parents = 1, 1747 .flags = CLK_SET_RATE_PARENT, 1748 .ops = &clk_branch2_ops, 1749 }, 1750 }, 1751}; 1752 1753static struct clk_branch video_ahb_clk = { 1754 .halt_reg = 0x1030, 1755 .clkr = { 1756 .enable_reg = 0x1030, 1757 .enable_mask = BIT(0), 1758 .hw.init = &(struct clk_init_data){ 1759 .name = "video_ahb_clk", 1760 .parent_names = (const char *[]){ "ahb_clk_src" }, 1761 .num_parents = 1, 1762 .flags = CLK_SET_RATE_PARENT, 1763 .ops = &clk_branch2_ops, 1764 }, 1765 }, 1766}; 1767 1768static struct clk_branch video_subcore0_clk = { 1769 .halt_reg = 0x1048, 1770 .clkr = { 1771 .enable_reg = 0x1048, 1772 .enable_mask = BIT(0), 1773 .hw.init = &(struct clk_init_data){ 1774 .name = "video_subcore0_clk", 1775 .parent_names = (const char *[]){ "video_subcore0_clk_src" }, 1776 .num_parents = 1, 1777 .flags = CLK_SET_RATE_PARENT, 1778 .ops = &clk_branch2_ops, 1779 }, 1780 }, 1781}; 1782 1783static struct clk_branch video_subcore1_clk = { 1784 .halt_reg = 0x104c, 1785 .clkr = { 1786 .enable_reg = 0x104c, 1787 .enable_mask = BIT(0), 1788 .hw.init = &(struct clk_init_data){ 1789 .name = "video_subcore1_clk", 1790 .parent_names = (const char *[]){ "video_subcore1_clk_src" }, 1791 .num_parents = 1, 1792 .flags = CLK_SET_RATE_PARENT, 1793 .ops = &clk_branch2_ops, 1794 }, 1795 }, 1796}; 1797 1798static struct clk_branch mdss_ahb_clk = { 1799 .halt_reg = 0x2308, 1800 .clkr = { 1801 .enable_reg = 0x2308, 1802 .enable_mask = BIT(0), 1803 .hw.init = &(struct clk_init_data){ 1804 .name = "mdss_ahb_clk", 1805 .parent_names = (const char *[]){ "ahb_clk_src" }, 1806 .num_parents = 1, 1807 .flags = CLK_SET_RATE_PARENT, 1808 .ops = &clk_branch2_ops, 1809 }, 1810 }, 1811}; 1812 1813static struct clk_branch mdss_hdmi_ahb_clk = { 1814 .halt_reg = 0x230c, 1815 .clkr = { 1816 .enable_reg = 0x230c, 1817 .enable_mask = BIT(0), 1818 .hw.init = &(struct clk_init_data){ 1819 .name = "mdss_hdmi_ahb_clk", 1820 .parent_names = (const char *[]){ "ahb_clk_src" }, 1821 .num_parents = 1, 1822 .flags = CLK_SET_RATE_PARENT, 1823 .ops = &clk_branch2_ops, 1824 }, 1825 }, 1826}; 1827 1828static struct clk_branch mdss_axi_clk = { 1829 .halt_reg = 0x2310, 1830 .clkr = { 1831 .enable_reg = 0x2310, 1832 .enable_mask = BIT(0), 1833 .hw.init = &(struct clk_init_data){ 1834 .name = "mdss_axi_clk", 1835 .parent_names = (const char *[]){ "axi_clk_src" }, 1836 .num_parents = 1, 1837 .flags = CLK_SET_RATE_PARENT, 1838 .ops = &clk_branch2_ops, 1839 }, 1840 }, 1841}; 1842 1843static struct clk_branch mdss_pclk0_clk = { 1844 .halt_reg = 0x2314, 1845 .clkr = { 1846 .enable_reg = 0x2314, 1847 .enable_mask = BIT(0), 1848 .hw.init = &(struct clk_init_data){ 1849 .name = "mdss_pclk0_clk", 1850 .parent_names = (const char *[]){ "pclk0_clk_src" }, 1851 .num_parents = 1, 1852 .flags = CLK_SET_RATE_PARENT, 1853 .ops = &clk_branch2_ops, 1854 }, 1855 }, 1856}; 1857 1858static struct clk_branch mdss_pclk1_clk = { 1859 .halt_reg = 0x2318, 1860 .clkr = { 1861 .enable_reg = 0x2318, 1862 .enable_mask = BIT(0), 1863 .hw.init = &(struct clk_init_data){ 1864 .name = "mdss_pclk1_clk", 1865 .parent_names = (const char *[]){ "pclk1_clk_src" }, 1866 .num_parents = 1, 1867 .flags = CLK_SET_RATE_PARENT, 1868 .ops = &clk_branch2_ops, 1869 }, 1870 }, 1871}; 1872 1873static struct clk_branch mdss_mdp_clk = { 1874 .halt_reg = 0x231c, 1875 .clkr = { 1876 .enable_reg = 0x231c, 1877 .enable_mask = BIT(0), 1878 .hw.init = &(struct clk_init_data){ 1879 .name = "mdss_mdp_clk", 1880 .parent_names = (const char *[]){ "mdp_clk_src" }, 1881 .num_parents = 1, 1882 .flags = CLK_SET_RATE_PARENT, 1883 .ops = &clk_branch2_ops, 1884 }, 1885 }, 1886}; 1887 1888static struct clk_branch mdss_extpclk_clk = { 1889 .halt_reg = 0x2324, 1890 .clkr = { 1891 .enable_reg = 0x2324, 1892 .enable_mask = BIT(0), 1893 .hw.init = &(struct clk_init_data){ 1894 .name = "mdss_extpclk_clk", 1895 .parent_names = (const char *[]){ "extpclk_clk_src" }, 1896 .num_parents = 1, 1897 .flags = CLK_SET_RATE_PARENT, 1898 .ops = &clk_branch2_ops, 1899 }, 1900 }, 1901}; 1902 1903static struct clk_branch mdss_vsync_clk = { 1904 .halt_reg = 0x2328, 1905 .clkr = { 1906 .enable_reg = 0x2328, 1907 .enable_mask = BIT(0), 1908 .hw.init = &(struct clk_init_data){ 1909 .name = "mdss_vsync_clk", 1910 .parent_names = (const char *[]){ "vsync_clk_src" }, 1911 .num_parents = 1, 1912 .flags = CLK_SET_RATE_PARENT, 1913 .ops = &clk_branch2_ops, 1914 }, 1915 }, 1916}; 1917 1918static struct clk_branch mdss_hdmi_clk = { 1919 .halt_reg = 0x2338, 1920 .clkr = { 1921 .enable_reg = 0x2338, 1922 .enable_mask = BIT(0), 1923 .hw.init = &(struct clk_init_data){ 1924 .name = "mdss_hdmi_clk", 1925 .parent_names = (const char *[]){ "hdmi_clk_src" }, 1926 .num_parents = 1, 1927 .flags = CLK_SET_RATE_PARENT, 1928 .ops = &clk_branch2_ops, 1929 }, 1930 }, 1931}; 1932 1933static struct clk_branch mdss_byte0_clk = { 1934 .halt_reg = 0x233c, 1935 .clkr = { 1936 .enable_reg = 0x233c, 1937 .enable_mask = BIT(0), 1938 .hw.init = &(struct clk_init_data){ 1939 .name = "mdss_byte0_clk", 1940 .parent_names = (const char *[]){ "byte0_clk_src" }, 1941 .num_parents = 1, 1942 .flags = CLK_SET_RATE_PARENT, 1943 .ops = &clk_branch2_ops, 1944 }, 1945 }, 1946}; 1947 1948static struct clk_branch mdss_byte1_clk = { 1949 .halt_reg = 0x2340, 1950 .clkr = { 1951 .enable_reg = 0x2340, 1952 .enable_mask = BIT(0), 1953 .hw.init = &(struct clk_init_data){ 1954 .name = "mdss_byte1_clk", 1955 .parent_names = (const char *[]){ "byte1_clk_src" }, 1956 .num_parents = 1, 1957 .flags = CLK_SET_RATE_PARENT, 1958 .ops = &clk_branch2_ops, 1959 }, 1960 }, 1961}; 1962 1963static struct clk_branch mdss_esc0_clk = { 1964 .halt_reg = 0x2344, 1965 .clkr = { 1966 .enable_reg = 0x2344, 1967 .enable_mask = BIT(0), 1968 .hw.init = &(struct clk_init_data){ 1969 .name = "mdss_esc0_clk", 1970 .parent_names = (const char *[]){ "esc0_clk_src" }, 1971 .num_parents = 1, 1972 .flags = CLK_SET_RATE_PARENT, 1973 .ops = &clk_branch2_ops, 1974 }, 1975 }, 1976}; 1977 1978static struct clk_branch mdss_esc1_clk = { 1979 .halt_reg = 0x2348, 1980 .clkr = { 1981 .enable_reg = 0x2348, 1982 .enable_mask = BIT(0), 1983 .hw.init = &(struct clk_init_data){ 1984 .name = "mdss_esc1_clk", 1985 .parent_names = (const char *[]){ "esc1_clk_src" }, 1986 .num_parents = 1, 1987 .flags = CLK_SET_RATE_PARENT, 1988 .ops = &clk_branch2_ops, 1989 }, 1990 }, 1991}; 1992 1993static struct clk_branch camss_top_ahb_clk = { 1994 .halt_reg = 0x3484, 1995 .clkr = { 1996 .enable_reg = 0x3484, 1997 .enable_mask = BIT(0), 1998 .hw.init = &(struct clk_init_data){ 1999 .name = "camss_top_ahb_clk", 2000 .parent_names = (const char *[]){ "ahb_clk_src" }, 2001 .num_parents = 1, 2002 .flags = CLK_SET_RATE_PARENT, 2003 .ops = &clk_branch2_ops, 2004 }, 2005 }, 2006}; 2007 2008static struct clk_branch camss_ahb_clk = { 2009 .halt_reg = 0x348c, 2010 .clkr = { 2011 .enable_reg = 0x348c, 2012 .enable_mask = BIT(0), 2013 .hw.init = &(struct clk_init_data){ 2014 .name = "camss_ahb_clk", 2015 .parent_names = (const char *[]){ "ahb_clk_src" }, 2016 .num_parents = 1, 2017 .flags = CLK_SET_RATE_PARENT, 2018 .ops = &clk_branch2_ops, 2019 }, 2020 }, 2021}; 2022 2023static struct clk_branch camss_micro_ahb_clk = { 2024 .halt_reg = 0x3494, 2025 .clkr = { 2026 .enable_reg = 0x3494, 2027 .enable_mask = BIT(0), 2028 .hw.init = &(struct clk_init_data){ 2029 .name = "camss_micro_ahb_clk", 2030 .parent_names = (const char *[]){ "ahb_clk_src" }, 2031 .num_parents = 1, 2032 .flags = CLK_SET_RATE_PARENT, 2033 .ops = &clk_branch2_ops, 2034 }, 2035 }, 2036}; 2037 2038static struct clk_branch camss_gp0_clk = { 2039 .halt_reg = 0x3444, 2040 .clkr = { 2041 .enable_reg = 0x3444, 2042 .enable_mask = BIT(0), 2043 .hw.init = &(struct clk_init_data){ 2044 .name = "camss_gp0_clk", 2045 .parent_names = (const char *[]){ "camss_gp0_clk_src" }, 2046 .num_parents = 1, 2047 .flags = CLK_SET_RATE_PARENT, 2048 .ops = &clk_branch2_ops, 2049 }, 2050 }, 2051}; 2052 2053static struct clk_branch camss_gp1_clk = { 2054 .halt_reg = 0x3474, 2055 .clkr = { 2056 .enable_reg = 0x3474, 2057 .enable_mask = BIT(0), 2058 .hw.init = &(struct clk_init_data){ 2059 .name = "camss_gp1_clk", 2060 .parent_names = (const char *[]){ "camss_gp1_clk_src" }, 2061 .num_parents = 1, 2062 .flags = CLK_SET_RATE_PARENT, 2063 .ops = &clk_branch2_ops, 2064 }, 2065 }, 2066}; 2067 2068static struct clk_branch camss_mclk0_clk = { 2069 .halt_reg = 0x3384, 2070 .clkr = { 2071 .enable_reg = 0x3384, 2072 .enable_mask = BIT(0), 2073 .hw.init = &(struct clk_init_data){ 2074 .name = "camss_mclk0_clk", 2075 .parent_names = (const char *[]){ "mclk0_clk_src" }, 2076 .num_parents = 1, 2077 .flags = CLK_SET_RATE_PARENT, 2078 .ops = &clk_branch2_ops, 2079 }, 2080 }, 2081}; 2082 2083static struct clk_branch camss_mclk1_clk = { 2084 .halt_reg = 0x33b4, 2085 .clkr = { 2086 .enable_reg = 0x33b4, 2087 .enable_mask = BIT(0), 2088 .hw.init = &(struct clk_init_data){ 2089 .name = "camss_mclk1_clk", 2090 .parent_names = (const char *[]){ "mclk1_clk_src" }, 2091 .num_parents = 1, 2092 .flags = CLK_SET_RATE_PARENT, 2093 .ops = &clk_branch2_ops, 2094 }, 2095 }, 2096}; 2097 2098static struct clk_branch camss_mclk2_clk = { 2099 .halt_reg = 0x33e4, 2100 .clkr = { 2101 .enable_reg = 0x33e4, 2102 .enable_mask = BIT(0), 2103 .hw.init = &(struct clk_init_data){ 2104 .name = "camss_mclk2_clk", 2105 .parent_names = (const char *[]){ "mclk2_clk_src" }, 2106 .num_parents = 1, 2107 .flags = CLK_SET_RATE_PARENT, 2108 .ops = &clk_branch2_ops, 2109 }, 2110 }, 2111}; 2112 2113static struct clk_branch camss_mclk3_clk = { 2114 .halt_reg = 0x3414, 2115 .clkr = { 2116 .enable_reg = 0x3414, 2117 .enable_mask = BIT(0), 2118 .hw.init = &(struct clk_init_data){ 2119 .name = "camss_mclk3_clk", 2120 .parent_names = (const char *[]){ "mclk3_clk_src" }, 2121 .num_parents = 1, 2122 .flags = CLK_SET_RATE_PARENT, 2123 .ops = &clk_branch2_ops, 2124 }, 2125 }, 2126}; 2127 2128static struct clk_branch camss_cci_clk = { 2129 .halt_reg = 0x3344, 2130 .clkr = { 2131 .enable_reg = 0x3344, 2132 .enable_mask = BIT(0), 2133 .hw.init = &(struct clk_init_data){ 2134 .name = "camss_cci_clk", 2135 .parent_names = (const char *[]){ "cci_clk_src" }, 2136 .num_parents = 1, 2137 .flags = CLK_SET_RATE_PARENT, 2138 .ops = &clk_branch2_ops, 2139 }, 2140 }, 2141}; 2142 2143static struct clk_branch camss_cci_ahb_clk = { 2144 .halt_reg = 0x3348, 2145 .clkr = { 2146 .enable_reg = 0x3348, 2147 .enable_mask = BIT(0), 2148 .hw.init = &(struct clk_init_data){ 2149 .name = "camss_cci_ahb_clk", 2150 .parent_names = (const char *[]){ "ahb_clk_src" }, 2151 .num_parents = 1, 2152 .flags = CLK_SET_RATE_PARENT, 2153 .ops = &clk_branch2_ops, 2154 }, 2155 }, 2156}; 2157 2158static struct clk_branch camss_csi0phytimer_clk = { 2159 .halt_reg = 0x3024, 2160 .clkr = { 2161 .enable_reg = 0x3024, 2162 .enable_mask = BIT(0), 2163 .hw.init = &(struct clk_init_data){ 2164 .name = "camss_csi0phytimer_clk", 2165 .parent_names = (const char *[]){ "csi0phytimer_clk_src" }, 2166 .num_parents = 1, 2167 .flags = CLK_SET_RATE_PARENT, 2168 .ops = &clk_branch2_ops, 2169 }, 2170 }, 2171}; 2172 2173static struct clk_branch camss_csi1phytimer_clk = { 2174 .halt_reg = 0x3054, 2175 .clkr = { 2176 .enable_reg = 0x3054, 2177 .enable_mask = BIT(0), 2178 .hw.init = &(struct clk_init_data){ 2179 .name = "camss_csi1phytimer_clk", 2180 .parent_names = (const char *[]){ "csi1phytimer_clk_src" }, 2181 .num_parents = 1, 2182 .flags = CLK_SET_RATE_PARENT, 2183 .ops = &clk_branch2_ops, 2184 }, 2185 }, 2186}; 2187 2188static struct clk_branch camss_csi2phytimer_clk = { 2189 .halt_reg = 0x3084, 2190 .clkr = { 2191 .enable_reg = 0x3084, 2192 .enable_mask = BIT(0), 2193 .hw.init = &(struct clk_init_data){ 2194 .name = "camss_csi2phytimer_clk", 2195 .parent_names = (const char *[]){ "csi2phytimer_clk_src" }, 2196 .num_parents = 1, 2197 .flags = CLK_SET_RATE_PARENT, 2198 .ops = &clk_branch2_ops, 2199 }, 2200 }, 2201}; 2202 2203static struct clk_branch camss_csiphy0_3p_clk = { 2204 .halt_reg = 0x3234, 2205 .clkr = { 2206 .enable_reg = 0x3234, 2207 .enable_mask = BIT(0), 2208 .hw.init = &(struct clk_init_data){ 2209 .name = "camss_csiphy0_3p_clk", 2210 .parent_names = (const char *[]){ "csiphy0_3p_clk_src" }, 2211 .num_parents = 1, 2212 .flags = CLK_SET_RATE_PARENT, 2213 .ops = &clk_branch2_ops, 2214 }, 2215 }, 2216}; 2217 2218static struct clk_branch camss_csiphy1_3p_clk = { 2219 .halt_reg = 0x3254, 2220 .clkr = { 2221 .enable_reg = 0x3254, 2222 .enable_mask = BIT(0), 2223 .hw.init = &(struct clk_init_data){ 2224 .name = "camss_csiphy1_3p_clk", 2225 .parent_names = (const char *[]){ "csiphy1_3p_clk_src" }, 2226 .num_parents = 1, 2227 .flags = CLK_SET_RATE_PARENT, 2228 .ops = &clk_branch2_ops, 2229 }, 2230 }, 2231}; 2232 2233static struct clk_branch camss_csiphy2_3p_clk = { 2234 .halt_reg = 0x3274, 2235 .clkr = { 2236 .enable_reg = 0x3274, 2237 .enable_mask = BIT(0), 2238 .hw.init = &(struct clk_init_data){ 2239 .name = "camss_csiphy2_3p_clk", 2240 .parent_names = (const char *[]){ "csiphy2_3p_clk_src" }, 2241 .num_parents = 1, 2242 .flags = CLK_SET_RATE_PARENT, 2243 .ops = &clk_branch2_ops, 2244 }, 2245 }, 2246}; 2247 2248static struct clk_branch camss_jpeg0_clk = { 2249 .halt_reg = 0x35a8, 2250 .clkr = { 2251 .enable_reg = 0x35a8, 2252 .enable_mask = BIT(0), 2253 .hw.init = &(struct clk_init_data){ 2254 .name = "camss_jpeg0_clk", 2255 .parent_names = (const char *[]){ "jpeg0_clk_src" }, 2256 .num_parents = 1, 2257 .flags = CLK_SET_RATE_PARENT, 2258 .ops = &clk_branch2_ops, 2259 }, 2260 }, 2261}; 2262 2263static struct clk_branch camss_jpeg2_clk = { 2264 .halt_reg = 0x35b0, 2265 .clkr = { 2266 .enable_reg = 0x35b0, 2267 .enable_mask = BIT(0), 2268 .hw.init = &(struct clk_init_data){ 2269 .name = "camss_jpeg2_clk", 2270 .parent_names = (const char *[]){ "jpeg2_clk_src" }, 2271 .num_parents = 1, 2272 .flags = CLK_SET_RATE_PARENT, 2273 .ops = &clk_branch2_ops, 2274 }, 2275 }, 2276}; 2277 2278static struct clk_branch camss_jpeg_dma_clk = { 2279 .halt_reg = 0x35c0, 2280 .clkr = { 2281 .enable_reg = 0x35c0, 2282 .enable_mask = BIT(0), 2283 .hw.init = &(struct clk_init_data){ 2284 .name = "camss_jpeg_dma_clk", 2285 .parent_names = (const char *[]){ "jpeg_dma_clk_src" }, 2286 .num_parents = 1, 2287 .flags = CLK_SET_RATE_PARENT, 2288 .ops = &clk_branch2_ops, 2289 }, 2290 }, 2291}; 2292 2293static struct clk_branch camss_jpeg_ahb_clk = { 2294 .halt_reg = 0x35b4, 2295 .clkr = { 2296 .enable_reg = 0x35b4, 2297 .enable_mask = BIT(0), 2298 .hw.init = &(struct clk_init_data){ 2299 .name = "camss_jpeg_ahb_clk", 2300 .parent_names = (const char *[]){ "ahb_clk_src" }, 2301 .num_parents = 1, 2302 .flags = CLK_SET_RATE_PARENT, 2303 .ops = &clk_branch2_ops, 2304 }, 2305 }, 2306}; 2307 2308static struct clk_branch camss_jpeg_axi_clk = { 2309 .halt_reg = 0x35b8, 2310 .clkr = { 2311 .enable_reg = 0x35b8, 2312 .enable_mask = BIT(0), 2313 .hw.init = &(struct clk_init_data){ 2314 .name = "camss_jpeg_axi_clk", 2315 .parent_names = (const char *[]){ "axi_clk_src" }, 2316 .num_parents = 1, 2317 .flags = CLK_SET_RATE_PARENT, 2318 .ops = &clk_branch2_ops, 2319 }, 2320 }, 2321}; 2322 2323static struct clk_branch camss_vfe_ahb_clk = { 2324 .halt_reg = 0x36b8, 2325 .clkr = { 2326 .enable_reg = 0x36b8, 2327 .enable_mask = BIT(0), 2328 .hw.init = &(struct clk_init_data){ 2329 .name = "camss_vfe_ahb_clk", 2330 .parent_names = (const char *[]){ "ahb_clk_src" }, 2331 .num_parents = 1, 2332 .flags = CLK_SET_RATE_PARENT, 2333 .ops = &clk_branch2_ops, 2334 }, 2335 }, 2336}; 2337 2338static struct clk_branch camss_vfe_axi_clk = { 2339 .halt_reg = 0x36bc, 2340 .clkr = { 2341 .enable_reg = 0x36bc, 2342 .enable_mask = BIT(0), 2343 .hw.init = &(struct clk_init_data){ 2344 .name = "camss_vfe_axi_clk", 2345 .parent_names = (const char *[]){ "axi_clk_src" }, 2346 .num_parents = 1, 2347 .flags = CLK_SET_RATE_PARENT, 2348 .ops = &clk_branch2_ops, 2349 }, 2350 }, 2351}; 2352 2353static struct clk_branch camss_vfe0_clk = { 2354 .halt_reg = 0x36a8, 2355 .clkr = { 2356 .enable_reg = 0x36a8, 2357 .enable_mask = BIT(0), 2358 .hw.init = &(struct clk_init_data){ 2359 .name = "camss_vfe0_clk", 2360 .parent_names = (const char *[]){ "vfe0_clk_src" }, 2361 .num_parents = 1, 2362 .flags = CLK_SET_RATE_PARENT, 2363 .ops = &clk_branch2_ops, 2364 }, 2365 }, 2366}; 2367 2368static struct clk_branch camss_vfe0_stream_clk = { 2369 .halt_reg = 0x3720, 2370 .clkr = { 2371 .enable_reg = 0x3720, 2372 .enable_mask = BIT(0), 2373 .hw.init = &(struct clk_init_data){ 2374 .name = "camss_vfe0_stream_clk", 2375 .parent_names = (const char *[]){ "vfe0_clk_src" }, 2376 .num_parents = 1, 2377 .flags = CLK_SET_RATE_PARENT, 2378 .ops = &clk_branch2_ops, 2379 }, 2380 }, 2381}; 2382 2383static struct clk_branch camss_vfe0_ahb_clk = { 2384 .halt_reg = 0x3668, 2385 .clkr = { 2386 .enable_reg = 0x3668, 2387 .enable_mask = BIT(0), 2388 .hw.init = &(struct clk_init_data){ 2389 .name = "camss_vfe0_ahb_clk", 2390 .parent_names = (const char *[]){ "ahb_clk_src" }, 2391 .num_parents = 1, 2392 .flags = CLK_SET_RATE_PARENT, 2393 .ops = &clk_branch2_ops, 2394 }, 2395 }, 2396}; 2397 2398static struct clk_branch camss_vfe1_clk = { 2399 .halt_reg = 0x36ac, 2400 .clkr = { 2401 .enable_reg = 0x36ac, 2402 .enable_mask = BIT(0), 2403 .hw.init = &(struct clk_init_data){ 2404 .name = "camss_vfe1_clk", 2405 .parent_names = (const char *[]){ "vfe1_clk_src" }, 2406 .num_parents = 1, 2407 .flags = CLK_SET_RATE_PARENT, 2408 .ops = &clk_branch2_ops, 2409 }, 2410 }, 2411}; 2412 2413static struct clk_branch camss_vfe1_stream_clk = { 2414 .halt_reg = 0x3724, 2415 .clkr = { 2416 .enable_reg = 0x3724, 2417 .enable_mask = BIT(0), 2418 .hw.init = &(struct clk_init_data){ 2419 .name = "camss_vfe1_stream_clk", 2420 .parent_names = (const char *[]){ "vfe1_clk_src" }, 2421 .num_parents = 1, 2422 .flags = CLK_SET_RATE_PARENT, 2423 .ops = &clk_branch2_ops, 2424 }, 2425 }, 2426}; 2427 2428static struct clk_branch camss_vfe1_ahb_clk = { 2429 .halt_reg = 0x3678, 2430 .clkr = { 2431 .enable_reg = 0x3678, 2432 .enable_mask = BIT(0), 2433 .hw.init = &(struct clk_init_data){ 2434 .name = "camss_vfe1_ahb_clk", 2435 .parent_names = (const char *[]){ "ahb_clk_src" }, 2436 .num_parents = 1, 2437 .flags = CLK_SET_RATE_PARENT, 2438 .ops = &clk_branch2_ops, 2439 }, 2440 }, 2441}; 2442 2443static struct clk_branch camss_csi_vfe0_clk = { 2444 .halt_reg = 0x3704, 2445 .clkr = { 2446 .enable_reg = 0x3704, 2447 .enable_mask = BIT(0), 2448 .hw.init = &(struct clk_init_data){ 2449 .name = "camss_csi_vfe0_clk", 2450 .parent_names = (const char *[]){ "vfe0_clk_src" }, 2451 .num_parents = 1, 2452 .flags = CLK_SET_RATE_PARENT, 2453 .ops = &clk_branch2_ops, 2454 }, 2455 }, 2456}; 2457 2458static struct clk_branch camss_csi_vfe1_clk = { 2459 .halt_reg = 0x3714, 2460 .clkr = { 2461 .enable_reg = 0x3714, 2462 .enable_mask = BIT(0), 2463 .hw.init = &(struct clk_init_data){ 2464 .name = "camss_csi_vfe1_clk", 2465 .parent_names = (const char *[]){ "vfe1_clk_src" }, 2466 .num_parents = 1, 2467 .flags = CLK_SET_RATE_PARENT, 2468 .ops = &clk_branch2_ops, 2469 }, 2470 }, 2471}; 2472 2473static struct clk_branch camss_cpp_vbif_ahb_clk = { 2474 .halt_reg = 0x36c8, 2475 .clkr = { 2476 .enable_reg = 0x36c8, 2477 .enable_mask = BIT(0), 2478 .hw.init = &(struct clk_init_data){ 2479 .name = "camss_cpp_vbif_ahb_clk", 2480 .parent_names = (const char *[]){ "ahb_clk_src" }, 2481 .num_parents = 1, 2482 .flags = CLK_SET_RATE_PARENT, 2483 .ops = &clk_branch2_ops, 2484 }, 2485 }, 2486}; 2487 2488static struct clk_branch camss_cpp_axi_clk = { 2489 .halt_reg = 0x36c4, 2490 .clkr = { 2491 .enable_reg = 0x36c4, 2492 .enable_mask = BIT(0), 2493 .hw.init = &(struct clk_init_data){ 2494 .name = "camss_cpp_axi_clk", 2495 .parent_names = (const char *[]){ "axi_clk_src" }, 2496 .num_parents = 1, 2497 .flags = CLK_SET_RATE_PARENT, 2498 .ops = &clk_branch2_ops, 2499 }, 2500 }, 2501}; 2502 2503static struct clk_branch camss_cpp_clk = { 2504 .halt_reg = 0x36b0, 2505 .clkr = { 2506 .enable_reg = 0x36b0, 2507 .enable_mask = BIT(0), 2508 .hw.init = &(struct clk_init_data){ 2509 .name = "camss_cpp_clk", 2510 .parent_names = (const char *[]){ "cpp_clk_src" }, 2511 .num_parents = 1, 2512 .flags = CLK_SET_RATE_PARENT, 2513 .ops = &clk_branch2_ops, 2514 }, 2515 }, 2516}; 2517 2518static struct clk_branch camss_cpp_ahb_clk = { 2519 .halt_reg = 0x36b4, 2520 .clkr = { 2521 .enable_reg = 0x36b4, 2522 .enable_mask = BIT(0), 2523 .hw.init = &(struct clk_init_data){ 2524 .name = "camss_cpp_ahb_clk", 2525 .parent_names = (const char *[]){ "ahb_clk_src" }, 2526 .num_parents = 1, 2527 .flags = CLK_SET_RATE_PARENT, 2528 .ops = &clk_branch2_ops, 2529 }, 2530 }, 2531}; 2532 2533static struct clk_branch camss_csi0_clk = { 2534 .halt_reg = 0x30b4, 2535 .clkr = { 2536 .enable_reg = 0x30b4, 2537 .enable_mask = BIT(0), 2538 .hw.init = &(struct clk_init_data){ 2539 .name = "camss_csi0_clk", 2540 .parent_names = (const char *[]){ "csi0_clk_src" }, 2541 .num_parents = 1, 2542 .flags = CLK_SET_RATE_PARENT, 2543 .ops = &clk_branch2_ops, 2544 }, 2545 }, 2546}; 2547 2548static struct clk_branch camss_csi0_ahb_clk = { 2549 .halt_reg = 0x30bc, 2550 .clkr = { 2551 .enable_reg = 0x30bc, 2552 .enable_mask = BIT(0), 2553 .hw.init = &(struct clk_init_data){ 2554 .name = "camss_csi0_ahb_clk", 2555 .parent_names = (const char *[]){ "ahb_clk_src" }, 2556 .num_parents = 1, 2557 .flags = CLK_SET_RATE_PARENT, 2558 .ops = &clk_branch2_ops, 2559 }, 2560 }, 2561}; 2562 2563static struct clk_branch camss_csi0phy_clk = { 2564 .halt_reg = 0x30c4, 2565 .clkr = { 2566 .enable_reg = 0x30c4, 2567 .enable_mask = BIT(0), 2568 .hw.init = &(struct clk_init_data){ 2569 .name = "camss_csi0phy_clk", 2570 .parent_names = (const char *[]){ "csi0_clk_src" }, 2571 .num_parents = 1, 2572 .flags = CLK_SET_RATE_PARENT, 2573 .ops = &clk_branch2_ops, 2574 }, 2575 }, 2576}; 2577 2578static struct clk_branch camss_csi0rdi_clk = { 2579 .halt_reg = 0x30d4, 2580 .clkr = { 2581 .enable_reg = 0x30d4, 2582 .enable_mask = BIT(0), 2583 .hw.init = &(struct clk_init_data){ 2584 .name = "camss_csi0rdi_clk", 2585 .parent_names = (const char *[]){ "csi0_clk_src" }, 2586 .num_parents = 1, 2587 .flags = CLK_SET_RATE_PARENT, 2588 .ops = &clk_branch2_ops, 2589 }, 2590 }, 2591}; 2592 2593static struct clk_branch camss_csi0pix_clk = { 2594 .halt_reg = 0x30e4, 2595 .clkr = { 2596 .enable_reg = 0x30e4, 2597 .enable_mask = BIT(0), 2598 .hw.init = &(struct clk_init_data){ 2599 .name = "camss_csi0pix_clk", 2600 .parent_names = (const char *[]){ "csi0_clk_src" }, 2601 .num_parents = 1, 2602 .flags = CLK_SET_RATE_PARENT, 2603 .ops = &clk_branch2_ops, 2604 }, 2605 }, 2606}; 2607 2608static struct clk_branch camss_csi1_clk = { 2609 .halt_reg = 0x3124, 2610 .clkr = { 2611 .enable_reg = 0x3124, 2612 .enable_mask = BIT(0), 2613 .hw.init = &(struct clk_init_data){ 2614 .name = "camss_csi1_clk", 2615 .parent_names = (const char *[]){ "csi1_clk_src" }, 2616 .num_parents = 1, 2617 .flags = CLK_SET_RATE_PARENT, 2618 .ops = &clk_branch2_ops, 2619 }, 2620 }, 2621}; 2622 2623static struct clk_branch camss_csi1_ahb_clk = { 2624 .halt_reg = 0x3128, 2625 .clkr = { 2626 .enable_reg = 0x3128, 2627 .enable_mask = BIT(0), 2628 .hw.init = &(struct clk_init_data){ 2629 .name = "camss_csi1_ahb_clk", 2630 .parent_names = (const char *[]){ "ahb_clk_src" }, 2631 .num_parents = 1, 2632 .flags = CLK_SET_RATE_PARENT, 2633 .ops = &clk_branch2_ops, 2634 }, 2635 }, 2636}; 2637 2638static struct clk_branch camss_csi1phy_clk = { 2639 .halt_reg = 0x3134, 2640 .clkr = { 2641 .enable_reg = 0x3134, 2642 .enable_mask = BIT(0), 2643 .hw.init = &(struct clk_init_data){ 2644 .name = "camss_csi1phy_clk", 2645 .parent_names = (const char *[]){ "csi1_clk_src" }, 2646 .num_parents = 1, 2647 .flags = CLK_SET_RATE_PARENT, 2648 .ops = &clk_branch2_ops, 2649 }, 2650 }, 2651}; 2652 2653static struct clk_branch camss_csi1rdi_clk = { 2654 .halt_reg = 0x3144, 2655 .clkr = { 2656 .enable_reg = 0x3144, 2657 .enable_mask = BIT(0), 2658 .hw.init = &(struct clk_init_data){ 2659 .name = "camss_csi1rdi_clk", 2660 .parent_names = (const char *[]){ "csi1_clk_src" }, 2661 .num_parents = 1, 2662 .flags = CLK_SET_RATE_PARENT, 2663 .ops = &clk_branch2_ops, 2664 }, 2665 }, 2666}; 2667 2668static struct clk_branch camss_csi1pix_clk = { 2669 .halt_reg = 0x3154, 2670 .clkr = { 2671 .enable_reg = 0x3154, 2672 .enable_mask = BIT(0), 2673 .hw.init = &(struct clk_init_data){ 2674 .name = "camss_csi1pix_clk", 2675 .parent_names = (const char *[]){ "csi1_clk_src" }, 2676 .num_parents = 1, 2677 .flags = CLK_SET_RATE_PARENT, 2678 .ops = &clk_branch2_ops, 2679 }, 2680 }, 2681}; 2682 2683static struct clk_branch camss_csi2_clk = { 2684 .halt_reg = 0x3184, 2685 .clkr = { 2686 .enable_reg = 0x3184, 2687 .enable_mask = BIT(0), 2688 .hw.init = &(struct clk_init_data){ 2689 .name = "camss_csi2_clk", 2690 .parent_names = (const char *[]){ "csi2_clk_src" }, 2691 .num_parents = 1, 2692 .flags = CLK_SET_RATE_PARENT, 2693 .ops = &clk_branch2_ops, 2694 }, 2695 }, 2696}; 2697 2698static struct clk_branch camss_csi2_ahb_clk = { 2699 .halt_reg = 0x3188, 2700 .clkr = { 2701 .enable_reg = 0x3188, 2702 .enable_mask = BIT(0), 2703 .hw.init = &(struct clk_init_data){ 2704 .name = "camss_csi2_ahb_clk", 2705 .parent_names = (const char *[]){ "ahb_clk_src" }, 2706 .num_parents = 1, 2707 .flags = CLK_SET_RATE_PARENT, 2708 .ops = &clk_branch2_ops, 2709 }, 2710 }, 2711}; 2712 2713static struct clk_branch camss_csi2phy_clk = { 2714 .halt_reg = 0x3194, 2715 .clkr = { 2716 .enable_reg = 0x3194, 2717 .enable_mask = BIT(0), 2718 .hw.init = &(struct clk_init_data){ 2719 .name = "camss_csi2phy_clk", 2720 .parent_names = (const char *[]){ "csi2_clk_src" }, 2721 .num_parents = 1, 2722 .flags = CLK_SET_RATE_PARENT, 2723 .ops = &clk_branch2_ops, 2724 }, 2725 }, 2726}; 2727 2728static struct clk_branch camss_csi2rdi_clk = { 2729 .halt_reg = 0x31a4, 2730 .clkr = { 2731 .enable_reg = 0x31a4, 2732 .enable_mask = BIT(0), 2733 .hw.init = &(struct clk_init_data){ 2734 .name = "camss_csi2rdi_clk", 2735 .parent_names = (const char *[]){ "csi2_clk_src" }, 2736 .num_parents = 1, 2737 .flags = CLK_SET_RATE_PARENT, 2738 .ops = &clk_branch2_ops, 2739 }, 2740 }, 2741}; 2742 2743static struct clk_branch camss_csi2pix_clk = { 2744 .halt_reg = 0x31b4, 2745 .clkr = { 2746 .enable_reg = 0x31b4, 2747 .enable_mask = BIT(0), 2748 .hw.init = &(struct clk_init_data){ 2749 .name = "camss_csi2pix_clk", 2750 .parent_names = (const char *[]){ "csi2_clk_src" }, 2751 .num_parents = 1, 2752 .flags = CLK_SET_RATE_PARENT, 2753 .ops = &clk_branch2_ops, 2754 }, 2755 }, 2756}; 2757 2758static struct clk_branch camss_csi3_clk = { 2759 .halt_reg = 0x31e4, 2760 .clkr = { 2761 .enable_reg = 0x31e4, 2762 .enable_mask = BIT(0), 2763 .hw.init = &(struct clk_init_data){ 2764 .name = "camss_csi3_clk", 2765 .parent_names = (const char *[]){ "csi3_clk_src" }, 2766 .num_parents = 1, 2767 .flags = CLK_SET_RATE_PARENT, 2768 .ops = &clk_branch2_ops, 2769 }, 2770 }, 2771}; 2772 2773static struct clk_branch camss_csi3_ahb_clk = { 2774 .halt_reg = 0x31e8, 2775 .clkr = { 2776 .enable_reg = 0x31e8, 2777 .enable_mask = BIT(0), 2778 .hw.init = &(struct clk_init_data){ 2779 .name = "camss_csi3_ahb_clk", 2780 .parent_names = (const char *[]){ "ahb_clk_src" }, 2781 .num_parents = 1, 2782 .flags = CLK_SET_RATE_PARENT, 2783 .ops = &clk_branch2_ops, 2784 }, 2785 }, 2786}; 2787 2788static struct clk_branch camss_csi3phy_clk = { 2789 .halt_reg = 0x31f4, 2790 .clkr = { 2791 .enable_reg = 0x31f4, 2792 .enable_mask = BIT(0), 2793 .hw.init = &(struct clk_init_data){ 2794 .name = "camss_csi3phy_clk", 2795 .parent_names = (const char *[]){ "csi3_clk_src" }, 2796 .num_parents = 1, 2797 .flags = CLK_SET_RATE_PARENT, 2798 .ops = &clk_branch2_ops, 2799 }, 2800 }, 2801}; 2802 2803static struct clk_branch camss_csi3rdi_clk = { 2804 .halt_reg = 0x3204, 2805 .clkr = { 2806 .enable_reg = 0x3204, 2807 .enable_mask = BIT(0), 2808 .hw.init = &(struct clk_init_data){ 2809 .name = "camss_csi3rdi_clk", 2810 .parent_names = (const char *[]){ "csi3_clk_src" }, 2811 .num_parents = 1, 2812 .flags = CLK_SET_RATE_PARENT, 2813 .ops = &clk_branch2_ops, 2814 }, 2815 }, 2816}; 2817 2818static struct clk_branch camss_csi3pix_clk = { 2819 .halt_reg = 0x3214, 2820 .clkr = { 2821 .enable_reg = 0x3214, 2822 .enable_mask = BIT(0), 2823 .hw.init = &(struct clk_init_data){ 2824 .name = "camss_csi3pix_clk", 2825 .parent_names = (const char *[]){ "csi3_clk_src" }, 2826 .num_parents = 1, 2827 .flags = CLK_SET_RATE_PARENT, 2828 .ops = &clk_branch2_ops, 2829 }, 2830 }, 2831}; 2832 2833static struct clk_branch camss_ispif_ahb_clk = { 2834 .halt_reg = 0x3224, 2835 .clkr = { 2836 .enable_reg = 0x3224, 2837 .enable_mask = BIT(0), 2838 .hw.init = &(struct clk_init_data){ 2839 .name = "camss_ispif_ahb_clk", 2840 .parent_names = (const char *[]){ "ahb_clk_src" }, 2841 .num_parents = 1, 2842 .flags = CLK_SET_RATE_PARENT, 2843 .ops = &clk_branch2_ops, 2844 }, 2845 }, 2846}; 2847 2848static struct clk_branch fd_core_clk = { 2849 .halt_reg = 0x3b68, 2850 .clkr = { 2851 .enable_reg = 0x3b68, 2852 .enable_mask = BIT(0), 2853 .hw.init = &(struct clk_init_data){ 2854 .name = "fd_core_clk", 2855 .parent_names = (const char *[]){ "fd_core_clk_src" }, 2856 .num_parents = 1, 2857 .flags = CLK_SET_RATE_PARENT, 2858 .ops = &clk_branch2_ops, 2859 }, 2860 }, 2861}; 2862 2863static struct clk_branch fd_core_uar_clk = { 2864 .halt_reg = 0x3b6c, 2865 .clkr = { 2866 .enable_reg = 0x3b6c, 2867 .enable_mask = BIT(0), 2868 .hw.init = &(struct clk_init_data){ 2869 .name = "fd_core_uar_clk", 2870 .parent_names = (const char *[]){ "fd_core_clk_src" }, 2871 .num_parents = 1, 2872 .flags = CLK_SET_RATE_PARENT, 2873 .ops = &clk_branch2_ops, 2874 }, 2875 }, 2876}; 2877 2878static struct clk_branch fd_ahb_clk = { 2879 .halt_reg = 0x3ba74, 2880 .clkr = { 2881 .enable_reg = 0x3ba74, 2882 .enable_mask = BIT(0), 2883 .hw.init = &(struct clk_init_data){ 2884 .name = "fd_ahb_clk", 2885 .parent_names = (const char *[]){ "ahb_clk_src" }, 2886 .num_parents = 1, 2887 .flags = CLK_SET_RATE_PARENT, 2888 .ops = &clk_branch2_ops, 2889 }, 2890 }, 2891}; 2892 2893static struct clk_hw *mmcc_msm8996_hws[] = { 2894 &gpll0_div.hw, 2895}; 2896 2897static struct gdsc mmagic_bimc_gdsc = { 2898 .gdscr = 0x529c, 2899 .pd = { 2900 .name = "mmagic_bimc", 2901 }, 2902 .pwrsts = PWRSTS_OFF_ON, 2903 .flags = ALWAYS_ON, 2904}; 2905 2906static struct gdsc mmagic_video_gdsc = { 2907 .gdscr = 0x119c, 2908 .gds_hw_ctrl = 0x120c, 2909 .pd = { 2910 .name = "mmagic_video", 2911 }, 2912 .pwrsts = PWRSTS_OFF_ON, 2913 .flags = VOTABLE | ALWAYS_ON, 2914}; 2915 2916static struct gdsc mmagic_mdss_gdsc = { 2917 .gdscr = 0x247c, 2918 .gds_hw_ctrl = 0x2480, 2919 .pd = { 2920 .name = "mmagic_mdss", 2921 }, 2922 .pwrsts = PWRSTS_OFF_ON, 2923 .flags = VOTABLE | ALWAYS_ON, 2924}; 2925 2926static struct gdsc mmagic_camss_gdsc = { 2927 .gdscr = 0x3c4c, 2928 .gds_hw_ctrl = 0x3c50, 2929 .pd = { 2930 .name = "mmagic_camss", 2931 }, 2932 .pwrsts = PWRSTS_OFF_ON, 2933 .flags = VOTABLE | ALWAYS_ON, 2934}; 2935 2936static struct gdsc venus_gdsc = { 2937 .gdscr = 0x1024, 2938 .cxcs = (unsigned int []){ 0x1028, 0x1034, 0x1038 }, 2939 .cxc_count = 3, 2940 .pd = { 2941 .name = "venus", 2942 }, 2943 .parent = &mmagic_video_gdsc.pd, 2944 .pwrsts = PWRSTS_OFF_ON, 2945}; 2946 2947static struct gdsc venus_core0_gdsc = { 2948 .gdscr = 0x1040, 2949 .cxcs = (unsigned int []){ 0x1048 }, 2950 .cxc_count = 1, 2951 .pd = { 2952 .name = "venus_core0", 2953 }, 2954 .parent = &venus_gdsc.pd, 2955 .pwrsts = PWRSTS_OFF_ON, 2956 .flags = HW_CTRL, 2957}; 2958 2959static struct gdsc venus_core1_gdsc = { 2960 .gdscr = 0x1044, 2961 .cxcs = (unsigned int []){ 0x104c }, 2962 .cxc_count = 1, 2963 .pd = { 2964 .name = "venus_core1", 2965 }, 2966 .parent = &venus_gdsc.pd, 2967 .pwrsts = PWRSTS_OFF_ON, 2968 .flags = HW_CTRL, 2969}; 2970 2971static struct gdsc camss_gdsc = { 2972 .gdscr = 0x34a0, 2973 .cxcs = (unsigned int []){ 0x36bc, 0x36c4 }, 2974 .cxc_count = 2, 2975 .pd = { 2976 .name = "camss", 2977 }, 2978 .parent = &mmagic_camss_gdsc.pd, 2979 .pwrsts = PWRSTS_OFF_ON, 2980}; 2981 2982static struct gdsc vfe0_gdsc = { 2983 .gdscr = 0x3664, 2984 .cxcs = (unsigned int []){ 0x36a8 }, 2985 .cxc_count = 1, 2986 .pd = { 2987 .name = "vfe0", 2988 }, 2989 .parent = &camss_gdsc.pd, 2990 .pwrsts = PWRSTS_OFF_ON, 2991}; 2992 2993static struct gdsc vfe1_gdsc = { 2994 .gdscr = 0x3674, 2995 .cxcs = (unsigned int []){ 0x36ac }, 2996 .cxc_count = 1, 2997 .pd = { 2998 .name = "vfe1", 2999 }, 3000 .parent = &camss_gdsc.pd, 3001 .pwrsts = PWRSTS_OFF_ON, 3002}; 3003 3004static struct gdsc jpeg_gdsc = { 3005 .gdscr = 0x35a4, 3006 .cxcs = (unsigned int []){ 0x35a8, 0x35b0, 0x35c0, 0x35b8 }, 3007 .cxc_count = 4, 3008 .pd = { 3009 .name = "jpeg", 3010 }, 3011 .parent = &camss_gdsc.pd, 3012 .pwrsts = PWRSTS_OFF_ON, 3013}; 3014 3015static struct gdsc cpp_gdsc = { 3016 .gdscr = 0x36d4, 3017 .cxcs = (unsigned int []){ 0x36b0 }, 3018 .cxc_count = 1, 3019 .pd = { 3020 .name = "cpp", 3021 }, 3022 .parent = &camss_gdsc.pd, 3023 .pwrsts = PWRSTS_OFF_ON, 3024}; 3025 3026static struct gdsc fd_gdsc = { 3027 .gdscr = 0x3b64, 3028 .cxcs = (unsigned int []){ 0x3b68, 0x3b6c }, 3029 .cxc_count = 2, 3030 .pd = { 3031 .name = "fd", 3032 }, 3033 .parent = &camss_gdsc.pd, 3034 .pwrsts = PWRSTS_OFF_ON, 3035}; 3036 3037static struct gdsc mdss_gdsc = { 3038 .gdscr = 0x2304, 3039 .cxcs = (unsigned int []){ 0x2310, 0x231c }, 3040 .cxc_count = 2, 3041 .pd = { 3042 .name = "mdss", 3043 }, 3044 .parent = &mmagic_mdss_gdsc.pd, 3045 .pwrsts = PWRSTS_OFF_ON, 3046}; 3047 3048static struct gdsc gpu_gdsc = { 3049 .gdscr = 0x4034, 3050 .gds_hw_ctrl = 0x4038, 3051 .pd = { 3052 .name = "gpu", 3053 }, 3054 .pwrsts = PWRSTS_OFF_ON, 3055 .flags = VOTABLE, 3056}; 3057 3058static struct gdsc gpu_gx_gdsc = { 3059 .gdscr = 0x4024, 3060 .clamp_io_ctrl = 0x4300, 3061 .cxcs = (unsigned int []){ 0x4028 }, 3062 .cxc_count = 1, 3063 .pd = { 3064 .name = "gpu_gx", 3065 }, 3066 .pwrsts = PWRSTS_OFF_ON, 3067 .parent = &gpu_gdsc.pd, 3068 .flags = CLAMP_IO, 3069 .supply = "vdd-gfx", 3070}; 3071 3072static struct clk_regmap *mmcc_msm8996_clocks[] = { 3073 [MMPLL0_EARLY] = &mmpll0_early.clkr, 3074 [MMPLL0_PLL] = &mmpll0.clkr, 3075 [MMPLL1_EARLY] = &mmpll1_early.clkr, 3076 [MMPLL1_PLL] = &mmpll1.clkr, 3077 [MMPLL2_EARLY] = &mmpll2_early.clkr, 3078 [MMPLL2_PLL] = &mmpll2.clkr, 3079 [MMPLL3_EARLY] = &mmpll3_early.clkr, 3080 [MMPLL3_PLL] = &mmpll3.clkr, 3081 [MMPLL4_EARLY] = &mmpll4_early.clkr, 3082 [MMPLL4_PLL] = &mmpll4.clkr, 3083 [MMPLL5_EARLY] = &mmpll5_early.clkr, 3084 [MMPLL5_PLL] = &mmpll5.clkr, 3085 [MMPLL8_EARLY] = &mmpll8_early.clkr, 3086 [MMPLL8_PLL] = &mmpll8.clkr, 3087 [MMPLL9_EARLY] = &mmpll9_early.clkr, 3088 [MMPLL9_PLL] = &mmpll9.clkr, 3089 [AHB_CLK_SRC] = &ahb_clk_src.clkr, 3090 [AXI_CLK_SRC] = &axi_clk_src.clkr, 3091 [MAXI_CLK_SRC] = &maxi_clk_src.clkr, 3092 [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr, 3093 [RBBMTIMER_CLK_SRC] = &rbbmtimer_clk_src.clkr, 3094 [ISENSE_CLK_SRC] = &isense_clk_src.clkr, 3095 [RBCPR_CLK_SRC] = &rbcpr_clk_src.clkr, 3096 [VIDEO_CORE_CLK_SRC] = &video_core_clk_src.clkr, 3097 [VIDEO_SUBCORE0_CLK_SRC] = &video_subcore0_clk_src.clkr, 3098 [VIDEO_SUBCORE1_CLK_SRC] = &video_subcore1_clk_src.clkr, 3099 [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr, 3100 [PCLK1_CLK_SRC] = &pclk1_clk_src.clkr, 3101 [MDP_CLK_SRC] = &mdp_clk_src.clkr, 3102 [EXTPCLK_CLK_SRC] = &extpclk_clk_src.clkr, 3103 [VSYNC_CLK_SRC] = &vsync_clk_src.clkr, 3104 [HDMI_CLK_SRC] = &hdmi_clk_src.clkr, 3105 [BYTE0_CLK_SRC] = &byte0_clk_src.clkr, 3106 [BYTE1_CLK_SRC] = &byte1_clk_src.clkr, 3107 [ESC0_CLK_SRC] = &esc0_clk_src.clkr, 3108 [ESC1_CLK_SRC] = &esc1_clk_src.clkr, 3109 [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr, 3110 [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr, 3111 [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr, 3112 [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr, 3113 [MCLK2_CLK_SRC] = &mclk2_clk_src.clkr, 3114 [MCLK3_CLK_SRC] = &mclk3_clk_src.clkr, 3115 [CCI_CLK_SRC] = &cci_clk_src.clkr, 3116 [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr, 3117 [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr, 3118 [CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr, 3119 [CSIPHY0_3P_CLK_SRC] = &csiphy0_3p_clk_src.clkr, 3120 [CSIPHY1_3P_CLK_SRC] = &csiphy1_3p_clk_src.clkr, 3121 [CSIPHY2_3P_CLK_SRC] = &csiphy2_3p_clk_src.clkr, 3122 [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr, 3123 [JPEG2_CLK_SRC] = &jpeg2_clk_src.clkr, 3124 [JPEG_DMA_CLK_SRC] = &jpeg_dma_clk_src.clkr, 3125 [VFE0_CLK_SRC] = &vfe0_clk_src.clkr, 3126 [VFE1_CLK_SRC] = &vfe1_clk_src.clkr, 3127 [CPP_CLK_SRC] = &cpp_clk_src.clkr, 3128 [CSI0_CLK_SRC] = &csi0_clk_src.clkr, 3129 [CSI1_CLK_SRC] = &csi1_clk_src.clkr, 3130 [CSI2_CLK_SRC] = &csi2_clk_src.clkr, 3131 [CSI3_CLK_SRC] = &csi3_clk_src.clkr, 3132 [FD_CORE_CLK_SRC] = &fd_core_clk_src.clkr, 3133 [MMSS_MMAGIC_AHB_CLK] = &mmss_mmagic_ahb_clk.clkr, 3134 [MMSS_MMAGIC_CFG_AHB_CLK] = &mmss_mmagic_cfg_ahb_clk.clkr, 3135 [MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr, 3136 [MMSS_MISC_CXO_CLK] = &mmss_misc_cxo_clk.clkr, 3137 [MMSS_MMAGIC_MAXI_CLK] = &mmss_mmagic_maxi_clk.clkr, 3138 [MMAGIC_CAMSS_AXI_CLK] = &mmagic_camss_axi_clk.clkr, 3139 [MMAGIC_CAMSS_NOC_CFG_AHB_CLK] = &mmagic_camss_noc_cfg_ahb_clk.clkr, 3140 [SMMU_VFE_AHB_CLK] = &smmu_vfe_ahb_clk.clkr, 3141 [SMMU_VFE_AXI_CLK] = &smmu_vfe_axi_clk.clkr, 3142 [SMMU_CPP_AHB_CLK] = &smmu_cpp_ahb_clk.clkr, 3143 [SMMU_CPP_AXI_CLK] = &smmu_cpp_axi_clk.clkr, 3144 [SMMU_JPEG_AHB_CLK] = &smmu_jpeg_ahb_clk.clkr, 3145 [SMMU_JPEG_AXI_CLK] = &smmu_jpeg_axi_clk.clkr, 3146 [MMAGIC_MDSS_AXI_CLK] = &mmagic_mdss_axi_clk.clkr, 3147 [MMAGIC_MDSS_NOC_CFG_AHB_CLK] = &mmagic_mdss_noc_cfg_ahb_clk.clkr, 3148 [SMMU_ROT_AHB_CLK] = &smmu_rot_ahb_clk.clkr, 3149 [SMMU_ROT_AXI_CLK] = &smmu_rot_axi_clk.clkr, 3150 [SMMU_MDP_AHB_CLK] = &smmu_mdp_ahb_clk.clkr, 3151 [SMMU_MDP_AXI_CLK] = &smmu_mdp_axi_clk.clkr, 3152 [MMAGIC_VIDEO_AXI_CLK] = &mmagic_video_axi_clk.clkr, 3153 [MMAGIC_VIDEO_NOC_CFG_AHB_CLK] = &mmagic_video_noc_cfg_ahb_clk.clkr, 3154 [SMMU_VIDEO_AHB_CLK] = &smmu_video_ahb_clk.clkr, 3155 [SMMU_VIDEO_AXI_CLK] = &smmu_video_axi_clk.clkr, 3156 [MMAGIC_BIMC_NOC_CFG_AHB_CLK] = &mmagic_bimc_noc_cfg_ahb_clk.clkr, 3157 [GPU_GX_GFX3D_CLK] = &gpu_gx_gfx3d_clk.clkr, 3158 [GPU_GX_RBBMTIMER_CLK] = &gpu_gx_rbbmtimer_clk.clkr, 3159 [GPU_AHB_CLK] = &gpu_ahb_clk.clkr, 3160 [GPU_AON_ISENSE_CLK] = &gpu_aon_isense_clk.clkr, 3161 [VMEM_MAXI_CLK] = &vmem_maxi_clk.clkr, 3162 [VMEM_AHB_CLK] = &vmem_ahb_clk.clkr, 3163 [MMSS_RBCPR_CLK] = &mmss_rbcpr_clk.clkr, 3164 [MMSS_RBCPR_AHB_CLK] = &mmss_rbcpr_ahb_clk.clkr, 3165 [VIDEO_CORE_CLK] = &video_core_clk.clkr, 3166 [VIDEO_AXI_CLK] = &video_axi_clk.clkr, 3167 [VIDEO_MAXI_CLK] = &video_maxi_clk.clkr, 3168 [VIDEO_AHB_CLK] = &video_ahb_clk.clkr, 3169 [VIDEO_SUBCORE0_CLK] = &video_subcore0_clk.clkr, 3170 [VIDEO_SUBCORE1_CLK] = &video_subcore1_clk.clkr, 3171 [MDSS_AHB_CLK] = &mdss_ahb_clk.clkr, 3172 [MDSS_HDMI_AHB_CLK] = &mdss_hdmi_ahb_clk.clkr, 3173 [MDSS_AXI_CLK] = &mdss_axi_clk.clkr, 3174 [MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr, 3175 [MDSS_PCLK1_CLK] = &mdss_pclk1_clk.clkr, 3176 [MDSS_MDP_CLK] = &mdss_mdp_clk.clkr, 3177 [MDSS_EXTPCLK_CLK] = &mdss_extpclk_clk.clkr, 3178 [MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr, 3179 [MDSS_HDMI_CLK] = &mdss_hdmi_clk.clkr, 3180 [MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr, 3181 [MDSS_BYTE1_CLK] = &mdss_byte1_clk.clkr, 3182 [MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr, 3183 [MDSS_ESC1_CLK] = &mdss_esc1_clk.clkr, 3184 [CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr, 3185 [CAMSS_AHB_CLK] = &camss_ahb_clk.clkr, 3186 [CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr, 3187 [CAMSS_GP0_CLK] = &camss_gp0_clk.clkr, 3188 [CAMSS_GP1_CLK] = &camss_gp1_clk.clkr, 3189 [CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr, 3190 [CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr, 3191 [CAMSS_MCLK2_CLK] = &camss_mclk2_clk.clkr, 3192 [CAMSS_MCLK3_CLK] = &camss_mclk3_clk.clkr, 3193 [CAMSS_CCI_CLK] = &camss_cci_clk.clkr, 3194 [CAMSS_CCI_AHB_CLK] = &camss_cci_ahb_clk.clkr, 3195 [CAMSS_CSI0PHYTIMER_CLK] = &camss_csi0phytimer_clk.clkr, 3196 [CAMSS_CSI1PHYTIMER_CLK] = &camss_csi1phytimer_clk.clkr, 3197 [CAMSS_CSI2PHYTIMER_CLK] = &camss_csi2phytimer_clk.clkr, 3198 [CAMSS_CSIPHY0_3P_CLK] = &camss_csiphy0_3p_clk.clkr, 3199 [CAMSS_CSIPHY1_3P_CLK] = &camss_csiphy1_3p_clk.clkr, 3200 [CAMSS_CSIPHY2_3P_CLK] = &camss_csiphy2_3p_clk.clkr, 3201 [CAMSS_JPEG0_CLK] = &camss_jpeg0_clk.clkr, 3202 [CAMSS_JPEG2_CLK] = &camss_jpeg2_clk.clkr, 3203 [CAMSS_JPEG_DMA_CLK] = &camss_jpeg_dma_clk.clkr, 3204 [CAMSS_JPEG_AHB_CLK] = &camss_jpeg_ahb_clk.clkr, 3205 [CAMSS_JPEG_AXI_CLK] = &camss_jpeg_axi_clk.clkr, 3206 [CAMSS_VFE_AHB_CLK] = &camss_vfe_ahb_clk.clkr, 3207 [CAMSS_VFE_AXI_CLK] = &camss_vfe_axi_clk.clkr, 3208 [CAMSS_VFE0_CLK] = &camss_vfe0_clk.clkr, 3209 [CAMSS_VFE0_STREAM_CLK] = &camss_vfe0_stream_clk.clkr, 3210 [CAMSS_VFE0_AHB_CLK] = &camss_vfe0_ahb_clk.clkr, 3211 [CAMSS_VFE1_CLK] = &camss_vfe1_clk.clkr, 3212 [CAMSS_VFE1_STREAM_CLK] = &camss_vfe1_stream_clk.clkr, 3213 [CAMSS_VFE1_AHB_CLK] = &camss_vfe1_ahb_clk.clkr, 3214 [CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr, 3215 [CAMSS_CSI_VFE1_CLK] = &camss_csi_vfe1_clk.clkr, 3216 [CAMSS_CPP_VBIF_AHB_CLK] = &camss_cpp_vbif_ahb_clk.clkr, 3217 [CAMSS_CPP_AXI_CLK] = &camss_cpp_axi_clk.clkr, 3218 [CAMSS_CPP_CLK] = &camss_cpp_clk.clkr, 3219 [CAMSS_CPP_AHB_CLK] = &camss_cpp_ahb_clk.clkr, 3220 [CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr, 3221 [CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr, 3222 [CAMSS_CSI0PHY_CLK] = &camss_csi0phy_clk.clkr, 3223 [CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr, 3224 [CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr, 3225 [CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr, 3226 [CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr, 3227 [CAMSS_CSI1PHY_CLK] = &camss_csi1phy_clk.clkr, 3228 [CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr, 3229 [CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr, 3230 [CAMSS_CSI2_CLK] = &camss_csi2_clk.clkr, 3231 [CAMSS_CSI2_AHB_CLK] = &camss_csi2_ahb_clk.clkr, 3232 [CAMSS_CSI2PHY_CLK] = &camss_csi2phy_clk.clkr, 3233 [CAMSS_CSI2RDI_CLK] = &camss_csi2rdi_clk.clkr, 3234 [CAMSS_CSI2PIX_CLK] = &camss_csi2pix_clk.clkr, 3235 [CAMSS_CSI3_CLK] = &camss_csi3_clk.clkr, 3236 [CAMSS_CSI3_AHB_CLK] = &camss_csi3_ahb_clk.clkr, 3237 [CAMSS_CSI3PHY_CLK] = &camss_csi3phy_clk.clkr, 3238 [CAMSS_CSI3RDI_CLK] = &camss_csi3rdi_clk.clkr, 3239 [CAMSS_CSI3PIX_CLK] = &camss_csi3pix_clk.clkr, 3240 [CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr, 3241 [FD_CORE_CLK] = &fd_core_clk.clkr, 3242 [FD_CORE_UAR_CLK] = &fd_core_uar_clk.clkr, 3243 [FD_AHB_CLK] = &fd_ahb_clk.clkr, 3244}; 3245 3246static struct gdsc *mmcc_msm8996_gdscs[] = { 3247 [MMAGIC_BIMC_GDSC] = &mmagic_bimc_gdsc, 3248 [MMAGIC_VIDEO_GDSC] = &mmagic_video_gdsc, 3249 [MMAGIC_MDSS_GDSC] = &mmagic_mdss_gdsc, 3250 [MMAGIC_CAMSS_GDSC] = &mmagic_camss_gdsc, 3251 [VENUS_GDSC] = &venus_gdsc, 3252 [VENUS_CORE0_GDSC] = &venus_core0_gdsc, 3253 [VENUS_CORE1_GDSC] = &venus_core1_gdsc, 3254 [CAMSS_GDSC] = &camss_gdsc, 3255 [VFE0_GDSC] = &vfe0_gdsc, 3256 [VFE1_GDSC] = &vfe1_gdsc, 3257 [JPEG_GDSC] = &jpeg_gdsc, 3258 [CPP_GDSC] = &cpp_gdsc, 3259 [FD_GDSC] = &fd_gdsc, 3260 [MDSS_GDSC] = &mdss_gdsc, 3261 [GPU_GDSC] = &gpu_gdsc, 3262 [GPU_GX_GDSC] = &gpu_gx_gdsc, 3263}; 3264 3265static const struct qcom_reset_map mmcc_msm8996_resets[] = { 3266 [MMAGICAHB_BCR] = { 0x5020 }, 3267 [MMAGIC_CFG_BCR] = { 0x5050 }, 3268 [MISC_BCR] = { 0x5010 }, 3269 [BTO_BCR] = { 0x5030 }, 3270 [MMAGICAXI_BCR] = { 0x5060 }, 3271 [MMAGICMAXI_BCR] = { 0x5070 }, 3272 [DSA_BCR] = { 0x50a0 }, 3273 [MMAGIC_CAMSS_BCR] = { 0x3c40 }, 3274 [THROTTLE_CAMSS_BCR] = { 0x3c30 }, 3275 [SMMU_VFE_BCR] = { 0x3c00 }, 3276 [SMMU_CPP_BCR] = { 0x3c10 }, 3277 [SMMU_JPEG_BCR] = { 0x3c20 }, 3278 [MMAGIC_MDSS_BCR] = { 0x2470 }, 3279 [THROTTLE_MDSS_BCR] = { 0x2460 }, 3280 [SMMU_ROT_BCR] = { 0x2440 }, 3281 [SMMU_MDP_BCR] = { 0x2450 }, 3282 [MMAGIC_VIDEO_BCR] = { 0x1190 }, 3283 [THROTTLE_VIDEO_BCR] = { 0x1180 }, 3284 [SMMU_VIDEO_BCR] = { 0x1170 }, 3285 [MMAGIC_BIMC_BCR] = { 0x5290 }, 3286 [GPU_GX_BCR] = { 0x4020 }, 3287 [GPU_BCR] = { 0x4030 }, 3288 [GPU_AON_BCR] = { 0x4040 }, 3289 [VMEM_BCR] = { 0x1200 }, 3290 [MMSS_RBCPR_BCR] = { 0x4080 }, 3291 [VIDEO_BCR] = { 0x1020 }, 3292 [MDSS_BCR] = { 0x2300 }, 3293 [CAMSS_TOP_BCR] = { 0x3480 }, 3294 [CAMSS_AHB_BCR] = { 0x3488 }, 3295 [CAMSS_MICRO_BCR] = { 0x3490 }, 3296 [CAMSS_CCI_BCR] = { 0x3340 }, 3297 [CAMSS_PHY0_BCR] = { 0x3020 }, 3298 [CAMSS_PHY1_BCR] = { 0x3050 }, 3299 [CAMSS_PHY2_BCR] = { 0x3080 }, 3300 [CAMSS_CSIPHY0_3P_BCR] = { 0x3230 }, 3301 [CAMSS_CSIPHY1_3P_BCR] = { 0x3250 }, 3302 [CAMSS_CSIPHY2_3P_BCR] = { 0x3270 }, 3303 [CAMSS_JPEG_BCR] = { 0x35a0 }, 3304 [CAMSS_VFE_BCR] = { 0x36a0 }, 3305 [CAMSS_VFE0_BCR] = { 0x3660 }, 3306 [CAMSS_VFE1_BCR] = { 0x3670 }, 3307 [CAMSS_CSI_VFE0_BCR] = { 0x3700 }, 3308 [CAMSS_CSI_VFE1_BCR] = { 0x3710 }, 3309 [CAMSS_CPP_TOP_BCR] = { 0x36c0 }, 3310 [CAMSS_CPP_BCR] = { 0x36d0 }, 3311 [CAMSS_CSI0_BCR] = { 0x30b0 }, 3312 [CAMSS_CSI0RDI_BCR] = { 0x30d0 }, 3313 [CAMSS_CSI0PIX_BCR] = { 0x30e0 }, 3314 [CAMSS_CSI1_BCR] = { 0x3120 }, 3315 [CAMSS_CSI1RDI_BCR] = { 0x3140 }, 3316 [CAMSS_CSI1PIX_BCR] = { 0x3150 }, 3317 [CAMSS_CSI2_BCR] = { 0x3180 }, 3318 [CAMSS_CSI2RDI_BCR] = { 0x31a0 }, 3319 [CAMSS_CSI2PIX_BCR] = { 0x31b0 }, 3320 [CAMSS_CSI3_BCR] = { 0x31e0 }, 3321 [CAMSS_CSI3RDI_BCR] = { 0x3200 }, 3322 [CAMSS_CSI3PIX_BCR] = { 0x3210 }, 3323 [CAMSS_ISPIF_BCR] = { 0x3220 }, 3324 [FD_BCR] = { 0x3b60 }, 3325 [MMSS_SPDM_RM_BCR] = { 0x300 }, 3326}; 3327 3328static const struct regmap_config mmcc_msm8996_regmap_config = { 3329 .reg_bits = 32, 3330 .reg_stride = 4, 3331 .val_bits = 32, 3332 .max_register = 0xb008, 3333 .fast_io = true, 3334}; 3335 3336static const struct qcom_cc_desc mmcc_msm8996_desc = { 3337 .config = &mmcc_msm8996_regmap_config, 3338 .clks = mmcc_msm8996_clocks, 3339 .num_clks = ARRAY_SIZE(mmcc_msm8996_clocks), 3340 .resets = mmcc_msm8996_resets, 3341 .num_resets = ARRAY_SIZE(mmcc_msm8996_resets), 3342 .gdscs = mmcc_msm8996_gdscs, 3343 .num_gdscs = ARRAY_SIZE(mmcc_msm8996_gdscs), 3344 .clk_hws = mmcc_msm8996_hws, 3345 .num_clk_hws = ARRAY_SIZE(mmcc_msm8996_hws), 3346}; 3347 3348static const struct of_device_id mmcc_msm8996_match_table[] = { 3349 { .compatible = "qcom,mmcc-msm8996" }, 3350 { } 3351}; 3352MODULE_DEVICE_TABLE(of, mmcc_msm8996_match_table); 3353 3354static int mmcc_msm8996_probe(struct platform_device *pdev) 3355{ 3356 struct regmap *regmap; 3357 3358 regmap = qcom_cc_map(pdev, &mmcc_msm8996_desc); 3359 if (IS_ERR(regmap)) 3360 return PTR_ERR(regmap); 3361 3362 /* Disable the AHB DCD */ 3363 regmap_update_bits(regmap, 0x50d8, BIT(31), 0); 3364 /* Disable the NoC FSM for mmss_mmagic_cfg_ahb_clk */ 3365 regmap_update_bits(regmap, 0x5054, BIT(15), 0); 3366 3367 return qcom_cc_really_probe(pdev, &mmcc_msm8996_desc, regmap); 3368} 3369 3370static struct platform_driver mmcc_msm8996_driver = { 3371 .probe = mmcc_msm8996_probe, 3372 .driver = { 3373 .name = "mmcc-msm8996", 3374 .of_match_table = mmcc_msm8996_match_table, 3375 }, 3376}; 3377module_platform_driver(mmcc_msm8996_driver); 3378 3379MODULE_DESCRIPTION("QCOM MMCC MSM8996 Driver"); 3380MODULE_LICENSE("GPL v2"); 3381MODULE_ALIAS("platform:mmcc-msm8996"); 3382