1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2013, The Linux Foundation. All rights reserved. 4 */ 5 6#include <linux/kernel.h> 7#include <linux/bitops.h> 8#include <linux/err.h> 9#include <linux/platform_device.h> 10#include <linux/module.h> 11#include <linux/of.h> 12#include <linux/of_device.h> 13#include <linux/clk-provider.h> 14#include <linux/regmap.h> 15#include <linux/reset-controller.h> 16 17#include <dt-bindings/clock/qcom,mmcc-msm8974.h> 18#include <dt-bindings/reset/qcom,mmcc-msm8974.h> 19 20#include "common.h" 21#include "clk-regmap.h" 22#include "clk-pll.h" 23#include "clk-rcg.h" 24#include "clk-branch.h" 25#include "reset.h" 26#include "gdsc.h" 27 28enum { 29 P_XO, 30 P_MMPLL0, 31 P_EDPLINK, 32 P_MMPLL1, 33 P_HDMIPLL, 34 P_GPLL0, 35 P_EDPVCO, 36 P_GPLL1, 37 P_DSI0PLL, 38 P_DSI0PLL_BYTE, 39 P_MMPLL2, 40 P_MMPLL3, 41 P_DSI1PLL, 42 P_DSI1PLL_BYTE, 43}; 44 45static const struct parent_map mmcc_xo_mmpll0_mmpll1_gpll0_map[] = { 46 { P_XO, 0 }, 47 { P_MMPLL0, 1 }, 48 { P_MMPLL1, 2 }, 49 { P_GPLL0, 5 } 50}; 51 52static const char * const mmcc_xo_mmpll0_mmpll1_gpll0[] = { 53 "xo", 54 "mmpll0_vote", 55 "mmpll1_vote", 56 "mmss_gpll0_vote", 57}; 58 59static const struct parent_map mmcc_xo_mmpll0_dsi_hdmi_gpll0_map[] = { 60 { P_XO, 0 }, 61 { P_MMPLL0, 1 }, 62 { P_HDMIPLL, 4 }, 63 { P_GPLL0, 5 }, 64 { P_DSI0PLL, 2 }, 65 { P_DSI1PLL, 3 } 66}; 67 68static const char * const mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = { 69 "xo", 70 "mmpll0_vote", 71 "hdmipll", 72 "mmss_gpll0_vote", 73 "dsi0pll", 74 "dsi1pll", 75}; 76 77static const struct parent_map mmcc_xo_mmpll0_1_2_gpll0_map[] = { 78 { P_XO, 0 }, 79 { P_MMPLL0, 1 }, 80 { P_MMPLL1, 2 }, 81 { P_GPLL0, 5 }, 82 { P_MMPLL2, 3 } 83}; 84 85static const char * const mmcc_xo_mmpll0_1_2_gpll0[] = { 86 "xo", 87 "mmpll0_vote", 88 "mmpll1_vote", 89 "mmss_gpll0_vote", 90 "mmpll2", 91}; 92 93static const struct parent_map mmcc_xo_mmpll0_1_3_gpll0_map[] = { 94 { P_XO, 0 }, 95 { P_MMPLL0, 1 }, 96 { P_MMPLL1, 2 }, 97 { P_GPLL0, 5 }, 98 { P_MMPLL3, 3 } 99}; 100 101static const char * const mmcc_xo_mmpll0_1_3_gpll0[] = { 102 "xo", 103 "mmpll0_vote", 104 "mmpll1_vote", 105 "mmss_gpll0_vote", 106 "mmpll3", 107}; 108 109static const struct parent_map mmcc_xo_mmpll0_1_gpll1_0_map[] = { 110 { P_XO, 0 }, 111 { P_MMPLL0, 1 }, 112 { P_MMPLL1, 2 }, 113 { P_GPLL0, 5 }, 114 { P_GPLL1, 4 } 115}; 116 117static const char * const mmcc_xo_mmpll0_1_gpll1_0[] = { 118 "xo", 119 "mmpll0_vote", 120 "mmpll1_vote", 121 "mmss_gpll0_vote", 122 "gpll1_vote", 123}; 124 125static const struct parent_map mmcc_xo_dsi_hdmi_edp_map[] = { 126 { P_XO, 0 }, 127 { P_EDPLINK, 4 }, 128 { P_HDMIPLL, 3 }, 129 { P_EDPVCO, 5 }, 130 { P_DSI0PLL, 1 }, 131 { P_DSI1PLL, 2 } 132}; 133 134static const char * const mmcc_xo_dsi_hdmi_edp[] = { 135 "xo", 136 "edp_link_clk", 137 "hdmipll", 138 "edp_vco_div", 139 "dsi0pll", 140 "dsi1pll", 141}; 142 143static const struct parent_map mmcc_xo_dsi_hdmi_edp_gpll0_map[] = { 144 { P_XO, 0 }, 145 { P_EDPLINK, 4 }, 146 { P_HDMIPLL, 3 }, 147 { P_GPLL0, 5 }, 148 { P_DSI0PLL, 1 }, 149 { P_DSI1PLL, 2 } 150}; 151 152static const char * const mmcc_xo_dsi_hdmi_edp_gpll0[] = { 153 "xo", 154 "edp_link_clk", 155 "hdmipll", 156 "gpll0_vote", 157 "dsi0pll", 158 "dsi1pll", 159}; 160 161static const struct parent_map mmcc_xo_dsibyte_hdmi_edp_gpll0_map[] = { 162 { P_XO, 0 }, 163 { P_EDPLINK, 4 }, 164 { P_HDMIPLL, 3 }, 165 { P_GPLL0, 5 }, 166 { P_DSI0PLL_BYTE, 1 }, 167 { P_DSI1PLL_BYTE, 2 } 168}; 169 170static const char * const mmcc_xo_dsibyte_hdmi_edp_gpll0[] = { 171 "xo", 172 "edp_link_clk", 173 "hdmipll", 174 "gpll0_vote", 175 "dsi0pllbyte", 176 "dsi1pllbyte", 177}; 178 179static struct clk_pll mmpll0 = { 180 .l_reg = 0x0004, 181 .m_reg = 0x0008, 182 .n_reg = 0x000c, 183 .config_reg = 0x0014, 184 .mode_reg = 0x0000, 185 .status_reg = 0x001c, 186 .status_bit = 17, 187 .clkr.hw.init = &(struct clk_init_data){ 188 .name = "mmpll0", 189 .parent_names = (const char *[]){ "xo" }, 190 .num_parents = 1, 191 .ops = &clk_pll_ops, 192 }, 193}; 194 195static struct clk_regmap mmpll0_vote = { 196 .enable_reg = 0x0100, 197 .enable_mask = BIT(0), 198 .hw.init = &(struct clk_init_data){ 199 .name = "mmpll0_vote", 200 .parent_names = (const char *[]){ "mmpll0" }, 201 .num_parents = 1, 202 .ops = &clk_pll_vote_ops, 203 }, 204}; 205 206static struct clk_pll mmpll1 = { 207 .l_reg = 0x0044, 208 .m_reg = 0x0048, 209 .n_reg = 0x004c, 210 .config_reg = 0x0050, 211 .mode_reg = 0x0040, 212 .status_reg = 0x005c, 213 .status_bit = 17, 214 .clkr.hw.init = &(struct clk_init_data){ 215 .name = "mmpll1", 216 .parent_names = (const char *[]){ "xo" }, 217 .num_parents = 1, 218 .ops = &clk_pll_ops, 219 }, 220}; 221 222static struct clk_regmap mmpll1_vote = { 223 .enable_reg = 0x0100, 224 .enable_mask = BIT(1), 225 .hw.init = &(struct clk_init_data){ 226 .name = "mmpll1_vote", 227 .parent_names = (const char *[]){ "mmpll1" }, 228 .num_parents = 1, 229 .ops = &clk_pll_vote_ops, 230 }, 231}; 232 233static struct clk_pll mmpll2 = { 234 .l_reg = 0x4104, 235 .m_reg = 0x4108, 236 .n_reg = 0x410c, 237 .config_reg = 0x4110, 238 .mode_reg = 0x4100, 239 .status_reg = 0x411c, 240 .clkr.hw.init = &(struct clk_init_data){ 241 .name = "mmpll2", 242 .parent_names = (const char *[]){ "xo" }, 243 .num_parents = 1, 244 .ops = &clk_pll_ops, 245 }, 246}; 247 248static struct clk_pll mmpll3 = { 249 .l_reg = 0x0084, 250 .m_reg = 0x0088, 251 .n_reg = 0x008c, 252 .config_reg = 0x0090, 253 .mode_reg = 0x0080, 254 .status_reg = 0x009c, 255 .status_bit = 17, 256 .clkr.hw.init = &(struct clk_init_data){ 257 .name = "mmpll3", 258 .parent_names = (const char *[]){ "xo" }, 259 .num_parents = 1, 260 .ops = &clk_pll_ops, 261 }, 262}; 263 264static struct clk_rcg2 mmss_ahb_clk_src = { 265 .cmd_rcgr = 0x5000, 266 .hid_width = 5, 267 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, 268 .clkr.hw.init = &(struct clk_init_data){ 269 .name = "mmss_ahb_clk_src", 270 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, 271 .num_parents = 4, 272 .ops = &clk_rcg2_ops, 273 }, 274}; 275 276static struct freq_tbl ftbl_mmss_axi_clk[] = { 277 F( 19200000, P_XO, 1, 0, 0), 278 F( 37500000, P_GPLL0, 16, 0, 0), 279 F( 50000000, P_GPLL0, 12, 0, 0), 280 F( 75000000, P_GPLL0, 8, 0, 0), 281 F(100000000, P_GPLL0, 6, 0, 0), 282 F(150000000, P_GPLL0, 4, 0, 0), 283 F(291750000, P_MMPLL1, 4, 0, 0), 284 F(400000000, P_MMPLL0, 2, 0, 0), 285 F(466800000, P_MMPLL1, 2.5, 0, 0), 286}; 287 288static struct clk_rcg2 mmss_axi_clk_src = { 289 .cmd_rcgr = 0x5040, 290 .hid_width = 5, 291 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, 292 .freq_tbl = ftbl_mmss_axi_clk, 293 .clkr.hw.init = &(struct clk_init_data){ 294 .name = "mmss_axi_clk_src", 295 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, 296 .num_parents = 4, 297 .ops = &clk_rcg2_ops, 298 }, 299}; 300 301static struct freq_tbl ftbl_ocmemnoc_clk[] = { 302 F( 19200000, P_XO, 1, 0, 0), 303 F( 37500000, P_GPLL0, 16, 0, 0), 304 F( 50000000, P_GPLL0, 12, 0, 0), 305 F( 75000000, P_GPLL0, 8, 0, 0), 306 F(100000000, P_GPLL0, 6, 0, 0), 307 F(150000000, P_GPLL0, 4, 0, 0), 308 F(291750000, P_MMPLL1, 4, 0, 0), 309 F(400000000, P_MMPLL0, 2, 0, 0), 310}; 311 312static struct clk_rcg2 ocmemnoc_clk_src = { 313 .cmd_rcgr = 0x5090, 314 .hid_width = 5, 315 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, 316 .freq_tbl = ftbl_ocmemnoc_clk, 317 .clkr.hw.init = &(struct clk_init_data){ 318 .name = "ocmemnoc_clk_src", 319 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, 320 .num_parents = 4, 321 .ops = &clk_rcg2_ops, 322 }, 323}; 324 325static struct freq_tbl ftbl_camss_csi0_3_clk[] = { 326 F(100000000, P_GPLL0, 6, 0, 0), 327 F(200000000, P_MMPLL0, 4, 0, 0), 328 { } 329}; 330 331static struct clk_rcg2 csi0_clk_src = { 332 .cmd_rcgr = 0x3090, 333 .hid_width = 5, 334 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, 335 .freq_tbl = ftbl_camss_csi0_3_clk, 336 .clkr.hw.init = &(struct clk_init_data){ 337 .name = "csi0_clk_src", 338 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, 339 .num_parents = 4, 340 .ops = &clk_rcg2_ops, 341 }, 342}; 343 344static struct clk_rcg2 csi1_clk_src = { 345 .cmd_rcgr = 0x3100, 346 .hid_width = 5, 347 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, 348 .freq_tbl = ftbl_camss_csi0_3_clk, 349 .clkr.hw.init = &(struct clk_init_data){ 350 .name = "csi1_clk_src", 351 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, 352 .num_parents = 4, 353 .ops = &clk_rcg2_ops, 354 }, 355}; 356 357static struct clk_rcg2 csi2_clk_src = { 358 .cmd_rcgr = 0x3160, 359 .hid_width = 5, 360 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, 361 .freq_tbl = ftbl_camss_csi0_3_clk, 362 .clkr.hw.init = &(struct clk_init_data){ 363 .name = "csi2_clk_src", 364 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, 365 .num_parents = 4, 366 .ops = &clk_rcg2_ops, 367 }, 368}; 369 370static struct clk_rcg2 csi3_clk_src = { 371 .cmd_rcgr = 0x31c0, 372 .hid_width = 5, 373 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, 374 .freq_tbl = ftbl_camss_csi0_3_clk, 375 .clkr.hw.init = &(struct clk_init_data){ 376 .name = "csi3_clk_src", 377 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, 378 .num_parents = 4, 379 .ops = &clk_rcg2_ops, 380 }, 381}; 382 383static struct freq_tbl ftbl_camss_vfe_vfe0_1_clk[] = { 384 F(37500000, P_GPLL0, 16, 0, 0), 385 F(50000000, P_GPLL0, 12, 0, 0), 386 F(60000000, P_GPLL0, 10, 0, 0), 387 F(80000000, P_GPLL0, 7.5, 0, 0), 388 F(100000000, P_GPLL0, 6, 0, 0), 389 F(109090000, P_GPLL0, 5.5, 0, 0), 390 F(133330000, P_GPLL0, 4.5, 0, 0), 391 F(200000000, P_GPLL0, 3, 0, 0), 392 F(228570000, P_MMPLL0, 3.5, 0, 0), 393 F(266670000, P_MMPLL0, 3, 0, 0), 394 F(320000000, P_MMPLL0, 2.5, 0, 0), 395 F(400000000, P_MMPLL0, 2, 0, 0), 396 F(465000000, P_MMPLL3, 2, 0, 0), 397 { } 398}; 399 400static struct clk_rcg2 vfe0_clk_src = { 401 .cmd_rcgr = 0x3600, 402 .hid_width = 5, 403 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, 404 .freq_tbl = ftbl_camss_vfe_vfe0_1_clk, 405 .clkr.hw.init = &(struct clk_init_data){ 406 .name = "vfe0_clk_src", 407 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, 408 .num_parents = 4, 409 .ops = &clk_rcg2_ops, 410 }, 411}; 412 413static struct clk_rcg2 vfe1_clk_src = { 414 .cmd_rcgr = 0x3620, 415 .hid_width = 5, 416 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, 417 .freq_tbl = ftbl_camss_vfe_vfe0_1_clk, 418 .clkr.hw.init = &(struct clk_init_data){ 419 .name = "vfe1_clk_src", 420 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, 421 .num_parents = 4, 422 .ops = &clk_rcg2_ops, 423 }, 424}; 425 426static struct freq_tbl ftbl_mdss_mdp_clk[] = { 427 F(37500000, P_GPLL0, 16, 0, 0), 428 F(60000000, P_GPLL0, 10, 0, 0), 429 F(75000000, P_GPLL0, 8, 0, 0), 430 F(85710000, P_GPLL0, 7, 0, 0), 431 F(100000000, P_GPLL0, 6, 0, 0), 432 F(133330000, P_MMPLL0, 6, 0, 0), 433 F(160000000, P_MMPLL0, 5, 0, 0), 434 F(200000000, P_MMPLL0, 4, 0, 0), 435 F(228570000, P_MMPLL0, 3.5, 0, 0), 436 F(240000000, P_GPLL0, 2.5, 0, 0), 437 F(266670000, P_MMPLL0, 3, 0, 0), 438 F(320000000, P_MMPLL0, 2.5, 0, 0), 439 { } 440}; 441 442static struct clk_rcg2 mdp_clk_src = { 443 .cmd_rcgr = 0x2040, 444 .hid_width = 5, 445 .parent_map = mmcc_xo_mmpll0_dsi_hdmi_gpll0_map, 446 .freq_tbl = ftbl_mdss_mdp_clk, 447 .clkr.hw.init = &(struct clk_init_data){ 448 .name = "mdp_clk_src", 449 .parent_names = mmcc_xo_mmpll0_dsi_hdmi_gpll0, 450 .num_parents = 6, 451 .ops = &clk_rcg2_ops, 452 }, 453}; 454 455static struct freq_tbl ftbl_camss_jpeg_jpeg0_2_clk[] = { 456 F(75000000, P_GPLL0, 8, 0, 0), 457 F(133330000, P_GPLL0, 4.5, 0, 0), 458 F(200000000, P_GPLL0, 3, 0, 0), 459 F(228570000, P_MMPLL0, 3.5, 0, 0), 460 F(266670000, P_MMPLL0, 3, 0, 0), 461 F(320000000, P_MMPLL0, 2.5, 0, 0), 462 { } 463}; 464 465static struct clk_rcg2 jpeg0_clk_src = { 466 .cmd_rcgr = 0x3500, 467 .hid_width = 5, 468 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, 469 .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk, 470 .clkr.hw.init = &(struct clk_init_data){ 471 .name = "jpeg0_clk_src", 472 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, 473 .num_parents = 4, 474 .ops = &clk_rcg2_ops, 475 }, 476}; 477 478static struct clk_rcg2 jpeg1_clk_src = { 479 .cmd_rcgr = 0x3520, 480 .hid_width = 5, 481 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, 482 .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk, 483 .clkr.hw.init = &(struct clk_init_data){ 484 .name = "jpeg1_clk_src", 485 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, 486 .num_parents = 4, 487 .ops = &clk_rcg2_ops, 488 }, 489}; 490 491static struct clk_rcg2 jpeg2_clk_src = { 492 .cmd_rcgr = 0x3540, 493 .hid_width = 5, 494 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, 495 .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk, 496 .clkr.hw.init = &(struct clk_init_data){ 497 .name = "jpeg2_clk_src", 498 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, 499 .num_parents = 4, 500 .ops = &clk_rcg2_ops, 501 }, 502}; 503 504static struct clk_rcg2 pclk0_clk_src = { 505 .cmd_rcgr = 0x2000, 506 .mnd_width = 8, 507 .hid_width = 5, 508 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map, 509 .clkr.hw.init = &(struct clk_init_data){ 510 .name = "pclk0_clk_src", 511 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0, 512 .num_parents = 6, 513 .ops = &clk_pixel_ops, 514 .flags = CLK_SET_RATE_PARENT, 515 }, 516}; 517 518static struct clk_rcg2 pclk1_clk_src = { 519 .cmd_rcgr = 0x2020, 520 .mnd_width = 8, 521 .hid_width = 5, 522 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map, 523 .clkr.hw.init = &(struct clk_init_data){ 524 .name = "pclk1_clk_src", 525 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0, 526 .num_parents = 6, 527 .ops = &clk_pixel_ops, 528 .flags = CLK_SET_RATE_PARENT, 529 }, 530}; 531 532static struct freq_tbl ftbl_venus0_vcodec0_clk[] = { 533 F(50000000, P_GPLL0, 12, 0, 0), 534 F(100000000, P_GPLL0, 6, 0, 0), 535 F(133330000, P_MMPLL0, 6, 0, 0), 536 F(200000000, P_MMPLL0, 4, 0, 0), 537 F(266670000, P_MMPLL0, 3, 0, 0), 538 F(465000000, P_MMPLL3, 2, 0, 0), 539 { } 540}; 541 542static struct clk_rcg2 vcodec0_clk_src = { 543 .cmd_rcgr = 0x1000, 544 .mnd_width = 8, 545 .hid_width = 5, 546 .parent_map = mmcc_xo_mmpll0_1_3_gpll0_map, 547 .freq_tbl = ftbl_venus0_vcodec0_clk, 548 .clkr.hw.init = &(struct clk_init_data){ 549 .name = "vcodec0_clk_src", 550 .parent_names = mmcc_xo_mmpll0_1_3_gpll0, 551 .num_parents = 5, 552 .ops = &clk_rcg2_ops, 553 }, 554}; 555 556static struct freq_tbl ftbl_camss_cci_cci_clk[] = { 557 F(19200000, P_XO, 1, 0, 0), 558 { } 559}; 560 561static struct clk_rcg2 cci_clk_src = { 562 .cmd_rcgr = 0x3300, 563 .hid_width = 5, 564 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, 565 .freq_tbl = ftbl_camss_cci_cci_clk, 566 .clkr.hw.init = &(struct clk_init_data){ 567 .name = "cci_clk_src", 568 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, 569 .num_parents = 4, 570 .ops = &clk_rcg2_ops, 571 }, 572}; 573 574static struct freq_tbl ftbl_camss_gp0_1_clk[] = { 575 F(10000, P_XO, 16, 1, 120), 576 F(24000, P_XO, 16, 1, 50), 577 F(6000000, P_GPLL0, 10, 1, 10), 578 F(12000000, P_GPLL0, 10, 1, 5), 579 F(13000000, P_GPLL0, 4, 13, 150), 580 F(24000000, P_GPLL0, 5, 1, 5), 581 { } 582}; 583 584static struct clk_rcg2 camss_gp0_clk_src = { 585 .cmd_rcgr = 0x3420, 586 .mnd_width = 8, 587 .hid_width = 5, 588 .parent_map = mmcc_xo_mmpll0_1_gpll1_0_map, 589 .freq_tbl = ftbl_camss_gp0_1_clk, 590 .clkr.hw.init = &(struct clk_init_data){ 591 .name = "camss_gp0_clk_src", 592 .parent_names = mmcc_xo_mmpll0_1_gpll1_0, 593 .num_parents = 5, 594 .ops = &clk_rcg2_ops, 595 }, 596}; 597 598static struct clk_rcg2 camss_gp1_clk_src = { 599 .cmd_rcgr = 0x3450, 600 .mnd_width = 8, 601 .hid_width = 5, 602 .parent_map = mmcc_xo_mmpll0_1_gpll1_0_map, 603 .freq_tbl = ftbl_camss_gp0_1_clk, 604 .clkr.hw.init = &(struct clk_init_data){ 605 .name = "camss_gp1_clk_src", 606 .parent_names = mmcc_xo_mmpll0_1_gpll1_0, 607 .num_parents = 5, 608 .ops = &clk_rcg2_ops, 609 }, 610}; 611 612static struct freq_tbl ftbl_camss_mclk0_3_clk[] = { 613 F(4800000, P_XO, 4, 0, 0), 614 F(6000000, P_GPLL0, 10, 1, 10), 615 F(8000000, P_GPLL0, 15, 1, 5), 616 F(9600000, P_XO, 2, 0, 0), 617 F(16000000, P_GPLL0, 12.5, 1, 3), 618 F(19200000, P_XO, 1, 0, 0), 619 F(24000000, P_GPLL0, 5, 1, 5), 620 F(32000000, P_MMPLL0, 5, 1, 5), 621 F(48000000, P_GPLL0, 12.5, 0, 0), 622 F(64000000, P_MMPLL0, 12.5, 0, 0), 623 F(66670000, P_GPLL0, 9, 0, 0), 624 { } 625}; 626 627static struct clk_rcg2 mclk0_clk_src = { 628 .cmd_rcgr = 0x3360, 629 .hid_width = 5, 630 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, 631 .freq_tbl = ftbl_camss_mclk0_3_clk, 632 .clkr.hw.init = &(struct clk_init_data){ 633 .name = "mclk0_clk_src", 634 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, 635 .num_parents = 4, 636 .ops = &clk_rcg2_ops, 637 }, 638}; 639 640static struct clk_rcg2 mclk1_clk_src = { 641 .cmd_rcgr = 0x3390, 642 .hid_width = 5, 643 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, 644 .freq_tbl = ftbl_camss_mclk0_3_clk, 645 .clkr.hw.init = &(struct clk_init_data){ 646 .name = "mclk1_clk_src", 647 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, 648 .num_parents = 4, 649 .ops = &clk_rcg2_ops, 650 }, 651}; 652 653static struct clk_rcg2 mclk2_clk_src = { 654 .cmd_rcgr = 0x33c0, 655 .hid_width = 5, 656 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, 657 .freq_tbl = ftbl_camss_mclk0_3_clk, 658 .clkr.hw.init = &(struct clk_init_data){ 659 .name = "mclk2_clk_src", 660 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, 661 .num_parents = 4, 662 .ops = &clk_rcg2_ops, 663 }, 664}; 665 666static struct clk_rcg2 mclk3_clk_src = { 667 .cmd_rcgr = 0x33f0, 668 .hid_width = 5, 669 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, 670 .freq_tbl = ftbl_camss_mclk0_3_clk, 671 .clkr.hw.init = &(struct clk_init_data){ 672 .name = "mclk3_clk_src", 673 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, 674 .num_parents = 4, 675 .ops = &clk_rcg2_ops, 676 }, 677}; 678 679static struct freq_tbl ftbl_camss_phy0_2_csi0_2phytimer_clk[] = { 680 F(100000000, P_GPLL0, 6, 0, 0), 681 F(200000000, P_MMPLL0, 4, 0, 0), 682 { } 683}; 684 685static struct clk_rcg2 csi0phytimer_clk_src = { 686 .cmd_rcgr = 0x3000, 687 .hid_width = 5, 688 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, 689 .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk, 690 .clkr.hw.init = &(struct clk_init_data){ 691 .name = "csi0phytimer_clk_src", 692 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, 693 .num_parents = 4, 694 .ops = &clk_rcg2_ops, 695 }, 696}; 697 698static struct clk_rcg2 csi1phytimer_clk_src = { 699 .cmd_rcgr = 0x3030, 700 .hid_width = 5, 701 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, 702 .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk, 703 .clkr.hw.init = &(struct clk_init_data){ 704 .name = "csi1phytimer_clk_src", 705 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, 706 .num_parents = 4, 707 .ops = &clk_rcg2_ops, 708 }, 709}; 710 711static struct clk_rcg2 csi2phytimer_clk_src = { 712 .cmd_rcgr = 0x3060, 713 .hid_width = 5, 714 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, 715 .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk, 716 .clkr.hw.init = &(struct clk_init_data){ 717 .name = "csi2phytimer_clk_src", 718 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, 719 .num_parents = 4, 720 .ops = &clk_rcg2_ops, 721 }, 722}; 723 724static struct freq_tbl ftbl_camss_vfe_cpp_clk[] = { 725 F(133330000, P_GPLL0, 4.5, 0, 0), 726 F(266670000, P_MMPLL0, 3, 0, 0), 727 F(320000000, P_MMPLL0, 2.5, 0, 0), 728 F(400000000, P_MMPLL0, 2, 0, 0), 729 F(465000000, P_MMPLL3, 2, 0, 0), 730 { } 731}; 732 733static struct clk_rcg2 cpp_clk_src = { 734 .cmd_rcgr = 0x3640, 735 .hid_width = 5, 736 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, 737 .freq_tbl = ftbl_camss_vfe_cpp_clk, 738 .clkr.hw.init = &(struct clk_init_data){ 739 .name = "cpp_clk_src", 740 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, 741 .num_parents = 4, 742 .ops = &clk_rcg2_ops, 743 }, 744}; 745 746static struct freq_tbl byte_freq_tbl[] = { 747 { .src = P_DSI0PLL_BYTE }, 748 { } 749}; 750 751static struct clk_rcg2 byte0_clk_src = { 752 .cmd_rcgr = 0x2120, 753 .hid_width = 5, 754 .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map, 755 .freq_tbl = byte_freq_tbl, 756 .clkr.hw.init = &(struct clk_init_data){ 757 .name = "byte0_clk_src", 758 .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0, 759 .num_parents = 6, 760 .ops = &clk_byte2_ops, 761 .flags = CLK_SET_RATE_PARENT, 762 }, 763}; 764 765static struct clk_rcg2 byte1_clk_src = { 766 .cmd_rcgr = 0x2140, 767 .hid_width = 5, 768 .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map, 769 .freq_tbl = byte_freq_tbl, 770 .clkr.hw.init = &(struct clk_init_data){ 771 .name = "byte1_clk_src", 772 .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0, 773 .num_parents = 6, 774 .ops = &clk_byte2_ops, 775 .flags = CLK_SET_RATE_PARENT, 776 }, 777}; 778 779static struct freq_tbl ftbl_mdss_edpaux_clk[] = { 780 F(19200000, P_XO, 1, 0, 0), 781 { } 782}; 783 784static struct clk_rcg2 edpaux_clk_src = { 785 .cmd_rcgr = 0x20e0, 786 .hid_width = 5, 787 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, 788 .freq_tbl = ftbl_mdss_edpaux_clk, 789 .clkr.hw.init = &(struct clk_init_data){ 790 .name = "edpaux_clk_src", 791 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, 792 .num_parents = 4, 793 .ops = &clk_rcg2_ops, 794 }, 795}; 796 797static struct freq_tbl ftbl_mdss_edplink_clk[] = { 798 F(135000000, P_EDPLINK, 2, 0, 0), 799 F(270000000, P_EDPLINK, 11, 0, 0), 800 { } 801}; 802 803static struct clk_rcg2 edplink_clk_src = { 804 .cmd_rcgr = 0x20c0, 805 .hid_width = 5, 806 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map, 807 .freq_tbl = ftbl_mdss_edplink_clk, 808 .clkr.hw.init = &(struct clk_init_data){ 809 .name = "edplink_clk_src", 810 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0, 811 .num_parents = 6, 812 .ops = &clk_rcg2_ops, 813 .flags = CLK_SET_RATE_PARENT, 814 }, 815}; 816 817static struct freq_tbl edp_pixel_freq_tbl[] = { 818 { .src = P_EDPVCO }, 819 { } 820}; 821 822static struct clk_rcg2 edppixel_clk_src = { 823 .cmd_rcgr = 0x20a0, 824 .mnd_width = 8, 825 .hid_width = 5, 826 .parent_map = mmcc_xo_dsi_hdmi_edp_map, 827 .freq_tbl = edp_pixel_freq_tbl, 828 .clkr.hw.init = &(struct clk_init_data){ 829 .name = "edppixel_clk_src", 830 .parent_names = mmcc_xo_dsi_hdmi_edp, 831 .num_parents = 6, 832 .ops = &clk_edp_pixel_ops, 833 }, 834}; 835 836static struct freq_tbl ftbl_mdss_esc0_1_clk[] = { 837 F(19200000, P_XO, 1, 0, 0), 838 { } 839}; 840 841static struct clk_rcg2 esc0_clk_src = { 842 .cmd_rcgr = 0x2160, 843 .hid_width = 5, 844 .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map, 845 .freq_tbl = ftbl_mdss_esc0_1_clk, 846 .clkr.hw.init = &(struct clk_init_data){ 847 .name = "esc0_clk_src", 848 .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0, 849 .num_parents = 6, 850 .ops = &clk_rcg2_ops, 851 }, 852}; 853 854static struct clk_rcg2 esc1_clk_src = { 855 .cmd_rcgr = 0x2180, 856 .hid_width = 5, 857 .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map, 858 .freq_tbl = ftbl_mdss_esc0_1_clk, 859 .clkr.hw.init = &(struct clk_init_data){ 860 .name = "esc1_clk_src", 861 .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0, 862 .num_parents = 6, 863 .ops = &clk_rcg2_ops, 864 }, 865}; 866 867static struct freq_tbl extpclk_freq_tbl[] = { 868 { .src = P_HDMIPLL }, 869 { } 870}; 871 872static struct clk_rcg2 extpclk_clk_src = { 873 .cmd_rcgr = 0x2060, 874 .hid_width = 5, 875 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map, 876 .freq_tbl = extpclk_freq_tbl, 877 .clkr.hw.init = &(struct clk_init_data){ 878 .name = "extpclk_clk_src", 879 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0, 880 .num_parents = 6, 881 .ops = &clk_byte_ops, 882 .flags = CLK_SET_RATE_PARENT, 883 }, 884}; 885 886static struct freq_tbl ftbl_mdss_hdmi_clk[] = { 887 F(19200000, P_XO, 1, 0, 0), 888 { } 889}; 890 891static struct clk_rcg2 hdmi_clk_src = { 892 .cmd_rcgr = 0x2100, 893 .hid_width = 5, 894 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, 895 .freq_tbl = ftbl_mdss_hdmi_clk, 896 .clkr.hw.init = &(struct clk_init_data){ 897 .name = "hdmi_clk_src", 898 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, 899 .num_parents = 4, 900 .ops = &clk_rcg2_ops, 901 }, 902}; 903 904static struct freq_tbl ftbl_mdss_vsync_clk[] = { 905 F(19200000, P_XO, 1, 0, 0), 906 { } 907}; 908 909static struct clk_rcg2 vsync_clk_src = { 910 .cmd_rcgr = 0x2080, 911 .hid_width = 5, 912 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, 913 .freq_tbl = ftbl_mdss_vsync_clk, 914 .clkr.hw.init = &(struct clk_init_data){ 915 .name = "vsync_clk_src", 916 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, 917 .num_parents = 4, 918 .ops = &clk_rcg2_ops, 919 }, 920}; 921 922static struct clk_branch camss_cci_cci_ahb_clk = { 923 .halt_reg = 0x3348, 924 .clkr = { 925 .enable_reg = 0x3348, 926 .enable_mask = BIT(0), 927 .hw.init = &(struct clk_init_data){ 928 .name = "camss_cci_cci_ahb_clk", 929 .parent_names = (const char *[]){ 930 "mmss_ahb_clk_src", 931 }, 932 .num_parents = 1, 933 .ops = &clk_branch2_ops, 934 }, 935 }, 936}; 937 938static struct clk_branch camss_cci_cci_clk = { 939 .halt_reg = 0x3344, 940 .clkr = { 941 .enable_reg = 0x3344, 942 .enable_mask = BIT(0), 943 .hw.init = &(struct clk_init_data){ 944 .name = "camss_cci_cci_clk", 945 .parent_names = (const char *[]){ 946 "cci_clk_src", 947 }, 948 .num_parents = 1, 949 .flags = CLK_SET_RATE_PARENT, 950 .ops = &clk_branch2_ops, 951 }, 952 }, 953}; 954 955static struct clk_branch camss_csi0_ahb_clk = { 956 .halt_reg = 0x30bc, 957 .clkr = { 958 .enable_reg = 0x30bc, 959 .enable_mask = BIT(0), 960 .hw.init = &(struct clk_init_data){ 961 .name = "camss_csi0_ahb_clk", 962 .parent_names = (const char *[]){ 963 "mmss_ahb_clk_src", 964 }, 965 .num_parents = 1, 966 .ops = &clk_branch2_ops, 967 }, 968 }, 969}; 970 971static struct clk_branch camss_csi0_clk = { 972 .halt_reg = 0x30b4, 973 .clkr = { 974 .enable_reg = 0x30b4, 975 .enable_mask = BIT(0), 976 .hw.init = &(struct clk_init_data){ 977 .name = "camss_csi0_clk", 978 .parent_names = (const char *[]){ 979 "csi0_clk_src", 980 }, 981 .num_parents = 1, 982 .flags = CLK_SET_RATE_PARENT, 983 .ops = &clk_branch2_ops, 984 }, 985 }, 986}; 987 988static struct clk_branch camss_csi0phy_clk = { 989 .halt_reg = 0x30c4, 990 .clkr = { 991 .enable_reg = 0x30c4, 992 .enable_mask = BIT(0), 993 .hw.init = &(struct clk_init_data){ 994 .name = "camss_csi0phy_clk", 995 .parent_names = (const char *[]){ 996 "csi0_clk_src", 997 }, 998 .num_parents = 1, 999 .flags = CLK_SET_RATE_PARENT, 1000 .ops = &clk_branch2_ops, 1001 }, 1002 }, 1003}; 1004 1005static struct clk_branch camss_csi0pix_clk = { 1006 .halt_reg = 0x30e4, 1007 .clkr = { 1008 .enable_reg = 0x30e4, 1009 .enable_mask = BIT(0), 1010 .hw.init = &(struct clk_init_data){ 1011 .name = "camss_csi0pix_clk", 1012 .parent_names = (const char *[]){ 1013 "csi0_clk_src", 1014 }, 1015 .num_parents = 1, 1016 .flags = CLK_SET_RATE_PARENT, 1017 .ops = &clk_branch2_ops, 1018 }, 1019 }, 1020}; 1021 1022static struct clk_branch camss_csi0rdi_clk = { 1023 .halt_reg = 0x30d4, 1024 .clkr = { 1025 .enable_reg = 0x30d4, 1026 .enable_mask = BIT(0), 1027 .hw.init = &(struct clk_init_data){ 1028 .name = "camss_csi0rdi_clk", 1029 .parent_names = (const char *[]){ 1030 "csi0_clk_src", 1031 }, 1032 .num_parents = 1, 1033 .flags = CLK_SET_RATE_PARENT, 1034 .ops = &clk_branch2_ops, 1035 }, 1036 }, 1037}; 1038 1039static struct clk_branch camss_csi1_ahb_clk = { 1040 .halt_reg = 0x3128, 1041 .clkr = { 1042 .enable_reg = 0x3128, 1043 .enable_mask = BIT(0), 1044 .hw.init = &(struct clk_init_data){ 1045 .name = "camss_csi1_ahb_clk", 1046 .parent_names = (const char *[]){ 1047 "mmss_ahb_clk_src", 1048 }, 1049 .num_parents = 1, 1050 .ops = &clk_branch2_ops, 1051 }, 1052 }, 1053}; 1054 1055static struct clk_branch camss_csi1_clk = { 1056 .halt_reg = 0x3124, 1057 .clkr = { 1058 .enable_reg = 0x3124, 1059 .enable_mask = BIT(0), 1060 .hw.init = &(struct clk_init_data){ 1061 .name = "camss_csi1_clk", 1062 .parent_names = (const char *[]){ 1063 "csi1_clk_src", 1064 }, 1065 .num_parents = 1, 1066 .flags = CLK_SET_RATE_PARENT, 1067 .ops = &clk_branch2_ops, 1068 }, 1069 }, 1070}; 1071 1072static struct clk_branch camss_csi1phy_clk = { 1073 .halt_reg = 0x3134, 1074 .clkr = { 1075 .enable_reg = 0x3134, 1076 .enable_mask = BIT(0), 1077 .hw.init = &(struct clk_init_data){ 1078 .name = "camss_csi1phy_clk", 1079 .parent_names = (const char *[]){ 1080 "csi1_clk_src", 1081 }, 1082 .num_parents = 1, 1083 .flags = CLK_SET_RATE_PARENT, 1084 .ops = &clk_branch2_ops, 1085 }, 1086 }, 1087}; 1088 1089static struct clk_branch camss_csi1pix_clk = { 1090 .halt_reg = 0x3154, 1091 .clkr = { 1092 .enable_reg = 0x3154, 1093 .enable_mask = BIT(0), 1094 .hw.init = &(struct clk_init_data){ 1095 .name = "camss_csi1pix_clk", 1096 .parent_names = (const char *[]){ 1097 "csi1_clk_src", 1098 }, 1099 .num_parents = 1, 1100 .flags = CLK_SET_RATE_PARENT, 1101 .ops = &clk_branch2_ops, 1102 }, 1103 }, 1104}; 1105 1106static struct clk_branch camss_csi1rdi_clk = { 1107 .halt_reg = 0x3144, 1108 .clkr = { 1109 .enable_reg = 0x3144, 1110 .enable_mask = BIT(0), 1111 .hw.init = &(struct clk_init_data){ 1112 .name = "camss_csi1rdi_clk", 1113 .parent_names = (const char *[]){ 1114 "csi1_clk_src", 1115 }, 1116 .num_parents = 1, 1117 .flags = CLK_SET_RATE_PARENT, 1118 .ops = &clk_branch2_ops, 1119 }, 1120 }, 1121}; 1122 1123static struct clk_branch camss_csi2_ahb_clk = { 1124 .halt_reg = 0x3188, 1125 .clkr = { 1126 .enable_reg = 0x3188, 1127 .enable_mask = BIT(0), 1128 .hw.init = &(struct clk_init_data){ 1129 .name = "camss_csi2_ahb_clk", 1130 .parent_names = (const char *[]){ 1131 "mmss_ahb_clk_src", 1132 }, 1133 .num_parents = 1, 1134 .ops = &clk_branch2_ops, 1135 }, 1136 }, 1137}; 1138 1139static struct clk_branch camss_csi2_clk = { 1140 .halt_reg = 0x3184, 1141 .clkr = { 1142 .enable_reg = 0x3184, 1143 .enable_mask = BIT(0), 1144 .hw.init = &(struct clk_init_data){ 1145 .name = "camss_csi2_clk", 1146 .parent_names = (const char *[]){ 1147 "csi2_clk_src", 1148 }, 1149 .num_parents = 1, 1150 .flags = CLK_SET_RATE_PARENT, 1151 .ops = &clk_branch2_ops, 1152 }, 1153 }, 1154}; 1155 1156static struct clk_branch camss_csi2phy_clk = { 1157 .halt_reg = 0x3194, 1158 .clkr = { 1159 .enable_reg = 0x3194, 1160 .enable_mask = BIT(0), 1161 .hw.init = &(struct clk_init_data){ 1162 .name = "camss_csi2phy_clk", 1163 .parent_names = (const char *[]){ 1164 "csi2_clk_src", 1165 }, 1166 .num_parents = 1, 1167 .flags = CLK_SET_RATE_PARENT, 1168 .ops = &clk_branch2_ops, 1169 }, 1170 }, 1171}; 1172 1173static struct clk_branch camss_csi2pix_clk = { 1174 .halt_reg = 0x31b4, 1175 .clkr = { 1176 .enable_reg = 0x31b4, 1177 .enable_mask = BIT(0), 1178 .hw.init = &(struct clk_init_data){ 1179 .name = "camss_csi2pix_clk", 1180 .parent_names = (const char *[]){ 1181 "csi2_clk_src", 1182 }, 1183 .num_parents = 1, 1184 .flags = CLK_SET_RATE_PARENT, 1185 .ops = &clk_branch2_ops, 1186 }, 1187 }, 1188}; 1189 1190static struct clk_branch camss_csi2rdi_clk = { 1191 .halt_reg = 0x31a4, 1192 .clkr = { 1193 .enable_reg = 0x31a4, 1194 .enable_mask = BIT(0), 1195 .hw.init = &(struct clk_init_data){ 1196 .name = "camss_csi2rdi_clk", 1197 .parent_names = (const char *[]){ 1198 "csi2_clk_src", 1199 }, 1200 .num_parents = 1, 1201 .flags = CLK_SET_RATE_PARENT, 1202 .ops = &clk_branch2_ops, 1203 }, 1204 }, 1205}; 1206 1207static struct clk_branch camss_csi3_ahb_clk = { 1208 .halt_reg = 0x31e8, 1209 .clkr = { 1210 .enable_reg = 0x31e8, 1211 .enable_mask = BIT(0), 1212 .hw.init = &(struct clk_init_data){ 1213 .name = "camss_csi3_ahb_clk", 1214 .parent_names = (const char *[]){ 1215 "mmss_ahb_clk_src", 1216 }, 1217 .num_parents = 1, 1218 .ops = &clk_branch2_ops, 1219 }, 1220 }, 1221}; 1222 1223static struct clk_branch camss_csi3_clk = { 1224 .halt_reg = 0x31e4, 1225 .clkr = { 1226 .enable_reg = 0x31e4, 1227 .enable_mask = BIT(0), 1228 .hw.init = &(struct clk_init_data){ 1229 .name = "camss_csi3_clk", 1230 .parent_names = (const char *[]){ 1231 "csi3_clk_src", 1232 }, 1233 .num_parents = 1, 1234 .flags = CLK_SET_RATE_PARENT, 1235 .ops = &clk_branch2_ops, 1236 }, 1237 }, 1238}; 1239 1240static struct clk_branch camss_csi3phy_clk = { 1241 .halt_reg = 0x31f4, 1242 .clkr = { 1243 .enable_reg = 0x31f4, 1244 .enable_mask = BIT(0), 1245 .hw.init = &(struct clk_init_data){ 1246 .name = "camss_csi3phy_clk", 1247 .parent_names = (const char *[]){ 1248 "csi3_clk_src", 1249 }, 1250 .num_parents = 1, 1251 .flags = CLK_SET_RATE_PARENT, 1252 .ops = &clk_branch2_ops, 1253 }, 1254 }, 1255}; 1256 1257static struct clk_branch camss_csi3pix_clk = { 1258 .halt_reg = 0x3214, 1259 .clkr = { 1260 .enable_reg = 0x3214, 1261 .enable_mask = BIT(0), 1262 .hw.init = &(struct clk_init_data){ 1263 .name = "camss_csi3pix_clk", 1264 .parent_names = (const char *[]){ 1265 "csi3_clk_src", 1266 }, 1267 .num_parents = 1, 1268 .flags = CLK_SET_RATE_PARENT, 1269 .ops = &clk_branch2_ops, 1270 }, 1271 }, 1272}; 1273 1274static struct clk_branch camss_csi3rdi_clk = { 1275 .halt_reg = 0x3204, 1276 .clkr = { 1277 .enable_reg = 0x3204, 1278 .enable_mask = BIT(0), 1279 .hw.init = &(struct clk_init_data){ 1280 .name = "camss_csi3rdi_clk", 1281 .parent_names = (const char *[]){ 1282 "csi3_clk_src", 1283 }, 1284 .num_parents = 1, 1285 .flags = CLK_SET_RATE_PARENT, 1286 .ops = &clk_branch2_ops, 1287 }, 1288 }, 1289}; 1290 1291static struct clk_branch camss_csi_vfe0_clk = { 1292 .halt_reg = 0x3704, 1293 .clkr = { 1294 .enable_reg = 0x3704, 1295 .enable_mask = BIT(0), 1296 .hw.init = &(struct clk_init_data){ 1297 .name = "camss_csi_vfe0_clk", 1298 .parent_names = (const char *[]){ 1299 "vfe0_clk_src", 1300 }, 1301 .num_parents = 1, 1302 .flags = CLK_SET_RATE_PARENT, 1303 .ops = &clk_branch2_ops, 1304 }, 1305 }, 1306}; 1307 1308static struct clk_branch camss_csi_vfe1_clk = { 1309 .halt_reg = 0x3714, 1310 .clkr = { 1311 .enable_reg = 0x3714, 1312 .enable_mask = BIT(0), 1313 .hw.init = &(struct clk_init_data){ 1314 .name = "camss_csi_vfe1_clk", 1315 .parent_names = (const char *[]){ 1316 "vfe1_clk_src", 1317 }, 1318 .num_parents = 1, 1319 .flags = CLK_SET_RATE_PARENT, 1320 .ops = &clk_branch2_ops, 1321 }, 1322 }, 1323}; 1324 1325static struct clk_branch camss_gp0_clk = { 1326 .halt_reg = 0x3444, 1327 .clkr = { 1328 .enable_reg = 0x3444, 1329 .enable_mask = BIT(0), 1330 .hw.init = &(struct clk_init_data){ 1331 .name = "camss_gp0_clk", 1332 .parent_names = (const char *[]){ 1333 "camss_gp0_clk_src", 1334 }, 1335 .num_parents = 1, 1336 .flags = CLK_SET_RATE_PARENT, 1337 .ops = &clk_branch2_ops, 1338 }, 1339 }, 1340}; 1341 1342static struct clk_branch camss_gp1_clk = { 1343 .halt_reg = 0x3474, 1344 .clkr = { 1345 .enable_reg = 0x3474, 1346 .enable_mask = BIT(0), 1347 .hw.init = &(struct clk_init_data){ 1348 .name = "camss_gp1_clk", 1349 .parent_names = (const char *[]){ 1350 "camss_gp1_clk_src", 1351 }, 1352 .num_parents = 1, 1353 .flags = CLK_SET_RATE_PARENT, 1354 .ops = &clk_branch2_ops, 1355 }, 1356 }, 1357}; 1358 1359static struct clk_branch camss_ispif_ahb_clk = { 1360 .halt_reg = 0x3224, 1361 .clkr = { 1362 .enable_reg = 0x3224, 1363 .enable_mask = BIT(0), 1364 .hw.init = &(struct clk_init_data){ 1365 .name = "camss_ispif_ahb_clk", 1366 .parent_names = (const char *[]){ 1367 "mmss_ahb_clk_src", 1368 }, 1369 .num_parents = 1, 1370 .ops = &clk_branch2_ops, 1371 }, 1372 }, 1373}; 1374 1375static struct clk_branch camss_jpeg_jpeg0_clk = { 1376 .halt_reg = 0x35a8, 1377 .clkr = { 1378 .enable_reg = 0x35a8, 1379 .enable_mask = BIT(0), 1380 .hw.init = &(struct clk_init_data){ 1381 .name = "camss_jpeg_jpeg0_clk", 1382 .parent_names = (const char *[]){ 1383 "jpeg0_clk_src", 1384 }, 1385 .num_parents = 1, 1386 .flags = CLK_SET_RATE_PARENT, 1387 .ops = &clk_branch2_ops, 1388 }, 1389 }, 1390}; 1391 1392static struct clk_branch camss_jpeg_jpeg1_clk = { 1393 .halt_reg = 0x35ac, 1394 .clkr = { 1395 .enable_reg = 0x35ac, 1396 .enable_mask = BIT(0), 1397 .hw.init = &(struct clk_init_data){ 1398 .name = "camss_jpeg_jpeg1_clk", 1399 .parent_names = (const char *[]){ 1400 "jpeg1_clk_src", 1401 }, 1402 .num_parents = 1, 1403 .flags = CLK_SET_RATE_PARENT, 1404 .ops = &clk_branch2_ops, 1405 }, 1406 }, 1407}; 1408 1409static struct clk_branch camss_jpeg_jpeg2_clk = { 1410 .halt_reg = 0x35b0, 1411 .clkr = { 1412 .enable_reg = 0x35b0, 1413 .enable_mask = BIT(0), 1414 .hw.init = &(struct clk_init_data){ 1415 .name = "camss_jpeg_jpeg2_clk", 1416 .parent_names = (const char *[]){ 1417 "jpeg2_clk_src", 1418 }, 1419 .num_parents = 1, 1420 .flags = CLK_SET_RATE_PARENT, 1421 .ops = &clk_branch2_ops, 1422 }, 1423 }, 1424}; 1425 1426static struct clk_branch camss_jpeg_jpeg_ahb_clk = { 1427 .halt_reg = 0x35b4, 1428 .clkr = { 1429 .enable_reg = 0x35b4, 1430 .enable_mask = BIT(0), 1431 .hw.init = &(struct clk_init_data){ 1432 .name = "camss_jpeg_jpeg_ahb_clk", 1433 .parent_names = (const char *[]){ 1434 "mmss_ahb_clk_src", 1435 }, 1436 .num_parents = 1, 1437 .ops = &clk_branch2_ops, 1438 }, 1439 }, 1440}; 1441 1442static struct clk_branch camss_jpeg_jpeg_axi_clk = { 1443 .halt_reg = 0x35b8, 1444 .clkr = { 1445 .enable_reg = 0x35b8, 1446 .enable_mask = BIT(0), 1447 .hw.init = &(struct clk_init_data){ 1448 .name = "camss_jpeg_jpeg_axi_clk", 1449 .parent_names = (const char *[]){ 1450 "mmss_axi_clk_src", 1451 }, 1452 .num_parents = 1, 1453 .ops = &clk_branch2_ops, 1454 }, 1455 }, 1456}; 1457 1458static struct clk_branch camss_jpeg_jpeg_ocmemnoc_clk = { 1459 .halt_reg = 0x35bc, 1460 .clkr = { 1461 .enable_reg = 0x35bc, 1462 .enable_mask = BIT(0), 1463 .hw.init = &(struct clk_init_data){ 1464 .name = "camss_jpeg_jpeg_ocmemnoc_clk", 1465 .parent_names = (const char *[]){ 1466 "ocmemnoc_clk_src", 1467 }, 1468 .num_parents = 1, 1469 .flags = CLK_SET_RATE_PARENT, 1470 .ops = &clk_branch2_ops, 1471 }, 1472 }, 1473}; 1474 1475static struct clk_branch camss_mclk0_clk = { 1476 .halt_reg = 0x3384, 1477 .clkr = { 1478 .enable_reg = 0x3384, 1479 .enable_mask = BIT(0), 1480 .hw.init = &(struct clk_init_data){ 1481 .name = "camss_mclk0_clk", 1482 .parent_names = (const char *[]){ 1483 "mclk0_clk_src", 1484 }, 1485 .num_parents = 1, 1486 .flags = CLK_SET_RATE_PARENT, 1487 .ops = &clk_branch2_ops, 1488 }, 1489 }, 1490}; 1491 1492static struct clk_branch camss_mclk1_clk = { 1493 .halt_reg = 0x33b4, 1494 .clkr = { 1495 .enable_reg = 0x33b4, 1496 .enable_mask = BIT(0), 1497 .hw.init = &(struct clk_init_data){ 1498 .name = "camss_mclk1_clk", 1499 .parent_names = (const char *[]){ 1500 "mclk1_clk_src", 1501 }, 1502 .num_parents = 1, 1503 .flags = CLK_SET_RATE_PARENT, 1504 .ops = &clk_branch2_ops, 1505 }, 1506 }, 1507}; 1508 1509static struct clk_branch camss_mclk2_clk = { 1510 .halt_reg = 0x33e4, 1511 .clkr = { 1512 .enable_reg = 0x33e4, 1513 .enable_mask = BIT(0), 1514 .hw.init = &(struct clk_init_data){ 1515 .name = "camss_mclk2_clk", 1516 .parent_names = (const char *[]){ 1517 "mclk2_clk_src", 1518 }, 1519 .num_parents = 1, 1520 .flags = CLK_SET_RATE_PARENT, 1521 .ops = &clk_branch2_ops, 1522 }, 1523 }, 1524}; 1525 1526static struct clk_branch camss_mclk3_clk = { 1527 .halt_reg = 0x3414, 1528 .clkr = { 1529 .enable_reg = 0x3414, 1530 .enable_mask = BIT(0), 1531 .hw.init = &(struct clk_init_data){ 1532 .name = "camss_mclk3_clk", 1533 .parent_names = (const char *[]){ 1534 "mclk3_clk_src", 1535 }, 1536 .num_parents = 1, 1537 .flags = CLK_SET_RATE_PARENT, 1538 .ops = &clk_branch2_ops, 1539 }, 1540 }, 1541}; 1542 1543static struct clk_branch camss_micro_ahb_clk = { 1544 .halt_reg = 0x3494, 1545 .clkr = { 1546 .enable_reg = 0x3494, 1547 .enable_mask = BIT(0), 1548 .hw.init = &(struct clk_init_data){ 1549 .name = "camss_micro_ahb_clk", 1550 .parent_names = (const char *[]){ 1551 "mmss_ahb_clk_src", 1552 }, 1553 .num_parents = 1, 1554 .ops = &clk_branch2_ops, 1555 }, 1556 }, 1557}; 1558 1559static struct clk_branch camss_phy0_csi0phytimer_clk = { 1560 .halt_reg = 0x3024, 1561 .clkr = { 1562 .enable_reg = 0x3024, 1563 .enable_mask = BIT(0), 1564 .hw.init = &(struct clk_init_data){ 1565 .name = "camss_phy0_csi0phytimer_clk", 1566 .parent_names = (const char *[]){ 1567 "csi0phytimer_clk_src", 1568 }, 1569 .num_parents = 1, 1570 .flags = CLK_SET_RATE_PARENT, 1571 .ops = &clk_branch2_ops, 1572 }, 1573 }, 1574}; 1575 1576static struct clk_branch camss_phy1_csi1phytimer_clk = { 1577 .halt_reg = 0x3054, 1578 .clkr = { 1579 .enable_reg = 0x3054, 1580 .enable_mask = BIT(0), 1581 .hw.init = &(struct clk_init_data){ 1582 .name = "camss_phy1_csi1phytimer_clk", 1583 .parent_names = (const char *[]){ 1584 "csi1phytimer_clk_src", 1585 }, 1586 .num_parents = 1, 1587 .flags = CLK_SET_RATE_PARENT, 1588 .ops = &clk_branch2_ops, 1589 }, 1590 }, 1591}; 1592 1593static struct clk_branch camss_phy2_csi2phytimer_clk = { 1594 .halt_reg = 0x3084, 1595 .clkr = { 1596 .enable_reg = 0x3084, 1597 .enable_mask = BIT(0), 1598 .hw.init = &(struct clk_init_data){ 1599 .name = "camss_phy2_csi2phytimer_clk", 1600 .parent_names = (const char *[]){ 1601 "csi2phytimer_clk_src", 1602 }, 1603 .num_parents = 1, 1604 .flags = CLK_SET_RATE_PARENT, 1605 .ops = &clk_branch2_ops, 1606 }, 1607 }, 1608}; 1609 1610static struct clk_branch camss_top_ahb_clk = { 1611 .halt_reg = 0x3484, 1612 .clkr = { 1613 .enable_reg = 0x3484, 1614 .enable_mask = BIT(0), 1615 .hw.init = &(struct clk_init_data){ 1616 .name = "camss_top_ahb_clk", 1617 .parent_names = (const char *[]){ 1618 "mmss_ahb_clk_src", 1619 }, 1620 .num_parents = 1, 1621 .ops = &clk_branch2_ops, 1622 }, 1623 }, 1624}; 1625 1626static struct clk_branch camss_vfe_cpp_ahb_clk = { 1627 .halt_reg = 0x36b4, 1628 .clkr = { 1629 .enable_reg = 0x36b4, 1630 .enable_mask = BIT(0), 1631 .hw.init = &(struct clk_init_data){ 1632 .name = "camss_vfe_cpp_ahb_clk", 1633 .parent_names = (const char *[]){ 1634 "mmss_ahb_clk_src", 1635 }, 1636 .num_parents = 1, 1637 .ops = &clk_branch2_ops, 1638 }, 1639 }, 1640}; 1641 1642static struct clk_branch camss_vfe_cpp_clk = { 1643 .halt_reg = 0x36b0, 1644 .clkr = { 1645 .enable_reg = 0x36b0, 1646 .enable_mask = BIT(0), 1647 .hw.init = &(struct clk_init_data){ 1648 .name = "camss_vfe_cpp_clk", 1649 .parent_names = (const char *[]){ 1650 "cpp_clk_src", 1651 }, 1652 .num_parents = 1, 1653 .flags = CLK_SET_RATE_PARENT, 1654 .ops = &clk_branch2_ops, 1655 }, 1656 }, 1657}; 1658 1659static struct clk_branch camss_vfe_vfe0_clk = { 1660 .halt_reg = 0x36a8, 1661 .clkr = { 1662 .enable_reg = 0x36a8, 1663 .enable_mask = BIT(0), 1664 .hw.init = &(struct clk_init_data){ 1665 .name = "camss_vfe_vfe0_clk", 1666 .parent_names = (const char *[]){ 1667 "vfe0_clk_src", 1668 }, 1669 .num_parents = 1, 1670 .flags = CLK_SET_RATE_PARENT, 1671 .ops = &clk_branch2_ops, 1672 }, 1673 }, 1674}; 1675 1676static struct clk_branch camss_vfe_vfe1_clk = { 1677 .halt_reg = 0x36ac, 1678 .clkr = { 1679 .enable_reg = 0x36ac, 1680 .enable_mask = BIT(0), 1681 .hw.init = &(struct clk_init_data){ 1682 .name = "camss_vfe_vfe1_clk", 1683 .parent_names = (const char *[]){ 1684 "vfe1_clk_src", 1685 }, 1686 .num_parents = 1, 1687 .flags = CLK_SET_RATE_PARENT, 1688 .ops = &clk_branch2_ops, 1689 }, 1690 }, 1691}; 1692 1693static struct clk_branch camss_vfe_vfe_ahb_clk = { 1694 .halt_reg = 0x36b8, 1695 .clkr = { 1696 .enable_reg = 0x36b8, 1697 .enable_mask = BIT(0), 1698 .hw.init = &(struct clk_init_data){ 1699 .name = "camss_vfe_vfe_ahb_clk", 1700 .parent_names = (const char *[]){ 1701 "mmss_ahb_clk_src", 1702 }, 1703 .num_parents = 1, 1704 .ops = &clk_branch2_ops, 1705 }, 1706 }, 1707}; 1708 1709static struct clk_branch camss_vfe_vfe_axi_clk = { 1710 .halt_reg = 0x36bc, 1711 .clkr = { 1712 .enable_reg = 0x36bc, 1713 .enable_mask = BIT(0), 1714 .hw.init = &(struct clk_init_data){ 1715 .name = "camss_vfe_vfe_axi_clk", 1716 .parent_names = (const char *[]){ 1717 "mmss_axi_clk_src", 1718 }, 1719 .num_parents = 1, 1720 .ops = &clk_branch2_ops, 1721 }, 1722 }, 1723}; 1724 1725static struct clk_branch camss_vfe_vfe_ocmemnoc_clk = { 1726 .halt_reg = 0x36c0, 1727 .clkr = { 1728 .enable_reg = 0x36c0, 1729 .enable_mask = BIT(0), 1730 .hw.init = &(struct clk_init_data){ 1731 .name = "camss_vfe_vfe_ocmemnoc_clk", 1732 .parent_names = (const char *[]){ 1733 "ocmemnoc_clk_src", 1734 }, 1735 .num_parents = 1, 1736 .flags = CLK_SET_RATE_PARENT, 1737 .ops = &clk_branch2_ops, 1738 }, 1739 }, 1740}; 1741 1742static struct clk_branch mdss_ahb_clk = { 1743 .halt_reg = 0x2308, 1744 .clkr = { 1745 .enable_reg = 0x2308, 1746 .enable_mask = BIT(0), 1747 .hw.init = &(struct clk_init_data){ 1748 .name = "mdss_ahb_clk", 1749 .parent_names = (const char *[]){ 1750 "mmss_ahb_clk_src", 1751 }, 1752 .num_parents = 1, 1753 .ops = &clk_branch2_ops, 1754 }, 1755 }, 1756}; 1757 1758static struct clk_branch mdss_axi_clk = { 1759 .halt_reg = 0x2310, 1760 .clkr = { 1761 .enable_reg = 0x2310, 1762 .enable_mask = BIT(0), 1763 .hw.init = &(struct clk_init_data){ 1764 .name = "mdss_axi_clk", 1765 .parent_names = (const char *[]){ 1766 "mmss_axi_clk_src", 1767 }, 1768 .num_parents = 1, 1769 .flags = CLK_SET_RATE_PARENT, 1770 .ops = &clk_branch2_ops, 1771 }, 1772 }, 1773}; 1774 1775static struct clk_branch mdss_byte0_clk = { 1776 .halt_reg = 0x233c, 1777 .clkr = { 1778 .enable_reg = 0x233c, 1779 .enable_mask = BIT(0), 1780 .hw.init = &(struct clk_init_data){ 1781 .name = "mdss_byte0_clk", 1782 .parent_names = (const char *[]){ 1783 "byte0_clk_src", 1784 }, 1785 .num_parents = 1, 1786 .flags = CLK_SET_RATE_PARENT, 1787 .ops = &clk_branch2_ops, 1788 }, 1789 }, 1790}; 1791 1792static struct clk_branch mdss_byte1_clk = { 1793 .halt_reg = 0x2340, 1794 .clkr = { 1795 .enable_reg = 0x2340, 1796 .enable_mask = BIT(0), 1797 .hw.init = &(struct clk_init_data){ 1798 .name = "mdss_byte1_clk", 1799 .parent_names = (const char *[]){ 1800 "byte1_clk_src", 1801 }, 1802 .num_parents = 1, 1803 .flags = CLK_SET_RATE_PARENT, 1804 .ops = &clk_branch2_ops, 1805 }, 1806 }, 1807}; 1808 1809static struct clk_branch mdss_edpaux_clk = { 1810 .halt_reg = 0x2334, 1811 .clkr = { 1812 .enable_reg = 0x2334, 1813 .enable_mask = BIT(0), 1814 .hw.init = &(struct clk_init_data){ 1815 .name = "mdss_edpaux_clk", 1816 .parent_names = (const char *[]){ 1817 "edpaux_clk_src", 1818 }, 1819 .num_parents = 1, 1820 .flags = CLK_SET_RATE_PARENT, 1821 .ops = &clk_branch2_ops, 1822 }, 1823 }, 1824}; 1825 1826static struct clk_branch mdss_edplink_clk = { 1827 .halt_reg = 0x2330, 1828 .clkr = { 1829 .enable_reg = 0x2330, 1830 .enable_mask = BIT(0), 1831 .hw.init = &(struct clk_init_data){ 1832 .name = "mdss_edplink_clk", 1833 .parent_names = (const char *[]){ 1834 "edplink_clk_src", 1835 }, 1836 .num_parents = 1, 1837 .flags = CLK_SET_RATE_PARENT, 1838 .ops = &clk_branch2_ops, 1839 }, 1840 }, 1841}; 1842 1843static struct clk_branch mdss_edppixel_clk = { 1844 .halt_reg = 0x232c, 1845 .clkr = { 1846 .enable_reg = 0x232c, 1847 .enable_mask = BIT(0), 1848 .hw.init = &(struct clk_init_data){ 1849 .name = "mdss_edppixel_clk", 1850 .parent_names = (const char *[]){ 1851 "edppixel_clk_src", 1852 }, 1853 .num_parents = 1, 1854 .flags = CLK_SET_RATE_PARENT, 1855 .ops = &clk_branch2_ops, 1856 }, 1857 }, 1858}; 1859 1860static struct clk_branch mdss_esc0_clk = { 1861 .halt_reg = 0x2344, 1862 .clkr = { 1863 .enable_reg = 0x2344, 1864 .enable_mask = BIT(0), 1865 .hw.init = &(struct clk_init_data){ 1866 .name = "mdss_esc0_clk", 1867 .parent_names = (const char *[]){ 1868 "esc0_clk_src", 1869 }, 1870 .num_parents = 1, 1871 .flags = CLK_SET_RATE_PARENT, 1872 .ops = &clk_branch2_ops, 1873 }, 1874 }, 1875}; 1876 1877static struct clk_branch mdss_esc1_clk = { 1878 .halt_reg = 0x2348, 1879 .clkr = { 1880 .enable_reg = 0x2348, 1881 .enable_mask = BIT(0), 1882 .hw.init = &(struct clk_init_data){ 1883 .name = "mdss_esc1_clk", 1884 .parent_names = (const char *[]){ 1885 "esc1_clk_src", 1886 }, 1887 .num_parents = 1, 1888 .flags = CLK_SET_RATE_PARENT, 1889 .ops = &clk_branch2_ops, 1890 }, 1891 }, 1892}; 1893 1894static struct clk_branch mdss_extpclk_clk = { 1895 .halt_reg = 0x2324, 1896 .clkr = { 1897 .enable_reg = 0x2324, 1898 .enable_mask = BIT(0), 1899 .hw.init = &(struct clk_init_data){ 1900 .name = "mdss_extpclk_clk", 1901 .parent_names = (const char *[]){ 1902 "extpclk_clk_src", 1903 }, 1904 .num_parents = 1, 1905 .flags = CLK_SET_RATE_PARENT, 1906 .ops = &clk_branch2_ops, 1907 }, 1908 }, 1909}; 1910 1911static struct clk_branch mdss_hdmi_ahb_clk = { 1912 .halt_reg = 0x230c, 1913 .clkr = { 1914 .enable_reg = 0x230c, 1915 .enable_mask = BIT(0), 1916 .hw.init = &(struct clk_init_data){ 1917 .name = "mdss_hdmi_ahb_clk", 1918 .parent_names = (const char *[]){ 1919 "mmss_ahb_clk_src", 1920 }, 1921 .num_parents = 1, 1922 .ops = &clk_branch2_ops, 1923 }, 1924 }, 1925}; 1926 1927static struct clk_branch mdss_hdmi_clk = { 1928 .halt_reg = 0x2338, 1929 .clkr = { 1930 .enable_reg = 0x2338, 1931 .enable_mask = BIT(0), 1932 .hw.init = &(struct clk_init_data){ 1933 .name = "mdss_hdmi_clk", 1934 .parent_names = (const char *[]){ 1935 "hdmi_clk_src", 1936 }, 1937 .num_parents = 1, 1938 .flags = CLK_SET_RATE_PARENT, 1939 .ops = &clk_branch2_ops, 1940 }, 1941 }, 1942}; 1943 1944static struct clk_branch mdss_mdp_clk = { 1945 .halt_reg = 0x231c, 1946 .clkr = { 1947 .enable_reg = 0x231c, 1948 .enable_mask = BIT(0), 1949 .hw.init = &(struct clk_init_data){ 1950 .name = "mdss_mdp_clk", 1951 .parent_names = (const char *[]){ 1952 "mdp_clk_src", 1953 }, 1954 .num_parents = 1, 1955 .flags = CLK_SET_RATE_PARENT, 1956 .ops = &clk_branch2_ops, 1957 }, 1958 }, 1959}; 1960 1961static struct clk_branch mdss_mdp_lut_clk = { 1962 .halt_reg = 0x2320, 1963 .clkr = { 1964 .enable_reg = 0x2320, 1965 .enable_mask = BIT(0), 1966 .hw.init = &(struct clk_init_data){ 1967 .name = "mdss_mdp_lut_clk", 1968 .parent_names = (const char *[]){ 1969 "mdp_clk_src", 1970 }, 1971 .num_parents = 1, 1972 .flags = CLK_SET_RATE_PARENT, 1973 .ops = &clk_branch2_ops, 1974 }, 1975 }, 1976}; 1977 1978static struct clk_branch mdss_pclk0_clk = { 1979 .halt_reg = 0x2314, 1980 .clkr = { 1981 .enable_reg = 0x2314, 1982 .enable_mask = BIT(0), 1983 .hw.init = &(struct clk_init_data){ 1984 .name = "mdss_pclk0_clk", 1985 .parent_names = (const char *[]){ 1986 "pclk0_clk_src", 1987 }, 1988 .num_parents = 1, 1989 .flags = CLK_SET_RATE_PARENT, 1990 .ops = &clk_branch2_ops, 1991 }, 1992 }, 1993}; 1994 1995static struct clk_branch mdss_pclk1_clk = { 1996 .halt_reg = 0x2318, 1997 .clkr = { 1998 .enable_reg = 0x2318, 1999 .enable_mask = BIT(0), 2000 .hw.init = &(struct clk_init_data){ 2001 .name = "mdss_pclk1_clk", 2002 .parent_names = (const char *[]){ 2003 "pclk1_clk_src", 2004 }, 2005 .num_parents = 1, 2006 .flags = CLK_SET_RATE_PARENT, 2007 .ops = &clk_branch2_ops, 2008 }, 2009 }, 2010}; 2011 2012static struct clk_branch mdss_vsync_clk = { 2013 .halt_reg = 0x2328, 2014 .clkr = { 2015 .enable_reg = 0x2328, 2016 .enable_mask = BIT(0), 2017 .hw.init = &(struct clk_init_data){ 2018 .name = "mdss_vsync_clk", 2019 .parent_names = (const char *[]){ 2020 "vsync_clk_src", 2021 }, 2022 .num_parents = 1, 2023 .flags = CLK_SET_RATE_PARENT, 2024 .ops = &clk_branch2_ops, 2025 }, 2026 }, 2027}; 2028 2029static struct clk_branch mmss_misc_ahb_clk = { 2030 .halt_reg = 0x502c, 2031 .clkr = { 2032 .enable_reg = 0x502c, 2033 .enable_mask = BIT(0), 2034 .hw.init = &(struct clk_init_data){ 2035 .name = "mmss_misc_ahb_clk", 2036 .parent_names = (const char *[]){ 2037 "mmss_ahb_clk_src", 2038 }, 2039 .num_parents = 1, 2040 .ops = &clk_branch2_ops, 2041 }, 2042 }, 2043}; 2044 2045static struct clk_branch mmss_mmssnoc_ahb_clk = { 2046 .halt_reg = 0x5024, 2047 .clkr = { 2048 .enable_reg = 0x5024, 2049 .enable_mask = BIT(0), 2050 .hw.init = &(struct clk_init_data){ 2051 .name = "mmss_mmssnoc_ahb_clk", 2052 .parent_names = (const char *[]){ 2053 "mmss_ahb_clk_src", 2054 }, 2055 .num_parents = 1, 2056 .ops = &clk_branch2_ops, 2057 .flags = CLK_IGNORE_UNUSED, 2058 }, 2059 }, 2060}; 2061 2062static struct clk_branch mmss_mmssnoc_bto_ahb_clk = { 2063 .halt_reg = 0x5028, 2064 .clkr = { 2065 .enable_reg = 0x5028, 2066 .enable_mask = BIT(0), 2067 .hw.init = &(struct clk_init_data){ 2068 .name = "mmss_mmssnoc_bto_ahb_clk", 2069 .parent_names = (const char *[]){ 2070 "mmss_ahb_clk_src", 2071 }, 2072 .num_parents = 1, 2073 .ops = &clk_branch2_ops, 2074 .flags = CLK_IGNORE_UNUSED, 2075 }, 2076 }, 2077}; 2078 2079static struct clk_branch mmss_mmssnoc_axi_clk = { 2080 .halt_reg = 0x506c, 2081 .clkr = { 2082 .enable_reg = 0x506c, 2083 .enable_mask = BIT(0), 2084 .hw.init = &(struct clk_init_data){ 2085 .name = "mmss_mmssnoc_axi_clk", 2086 .parent_names = (const char *[]){ 2087 "mmss_axi_clk_src", 2088 }, 2089 .num_parents = 1, 2090 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2091 .ops = &clk_branch2_ops, 2092 }, 2093 }, 2094}; 2095 2096static struct clk_branch mmss_s0_axi_clk = { 2097 .halt_reg = 0x5064, 2098 .clkr = { 2099 .enable_reg = 0x5064, 2100 .enable_mask = BIT(0), 2101 .hw.init = &(struct clk_init_data){ 2102 .name = "mmss_s0_axi_clk", 2103 .parent_names = (const char *[]){ 2104 "mmss_axi_clk_src", 2105 }, 2106 .num_parents = 1, 2107 .ops = &clk_branch2_ops, 2108 .flags = CLK_IGNORE_UNUSED, 2109 }, 2110 }, 2111}; 2112 2113static struct clk_branch ocmemcx_ahb_clk = { 2114 .halt_reg = 0x405c, 2115 .clkr = { 2116 .enable_reg = 0x405c, 2117 .enable_mask = BIT(0), 2118 .hw.init = &(struct clk_init_data){ 2119 .name = "ocmemcx_ahb_clk", 2120 .parent_names = (const char *[]){ 2121 "mmss_ahb_clk_src", 2122 }, 2123 .num_parents = 1, 2124 .ops = &clk_branch2_ops, 2125 }, 2126 }, 2127}; 2128 2129static struct clk_branch ocmemcx_ocmemnoc_clk = { 2130 .halt_reg = 0x4058, 2131 .clkr = { 2132 .enable_reg = 0x4058, 2133 .enable_mask = BIT(0), 2134 .hw.init = &(struct clk_init_data){ 2135 .name = "ocmemcx_ocmemnoc_clk", 2136 .parent_names = (const char *[]){ 2137 "ocmemnoc_clk_src", 2138 }, 2139 .num_parents = 1, 2140 .flags = CLK_SET_RATE_PARENT, 2141 .ops = &clk_branch2_ops, 2142 }, 2143 }, 2144}; 2145 2146static struct clk_branch oxili_ocmemgx_clk = { 2147 .halt_reg = 0x402c, 2148 .clkr = { 2149 .enable_reg = 0x402c, 2150 .enable_mask = BIT(0), 2151 .hw.init = &(struct clk_init_data){ 2152 .name = "oxili_ocmemgx_clk", 2153 .parent_names = (const char *[]){ 2154 "gfx3d_clk_src", 2155 }, 2156 .num_parents = 1, 2157 .flags = CLK_SET_RATE_PARENT, 2158 .ops = &clk_branch2_ops, 2159 }, 2160 }, 2161}; 2162 2163static struct clk_branch ocmemnoc_clk = { 2164 .halt_reg = 0x50b4, 2165 .clkr = { 2166 .enable_reg = 0x50b4, 2167 .enable_mask = BIT(0), 2168 .hw.init = &(struct clk_init_data){ 2169 .name = "ocmemnoc_clk", 2170 .parent_names = (const char *[]){ 2171 "ocmemnoc_clk_src", 2172 }, 2173 .num_parents = 1, 2174 .flags = CLK_SET_RATE_PARENT, 2175 .ops = &clk_branch2_ops, 2176 }, 2177 }, 2178}; 2179 2180static struct clk_branch oxili_gfx3d_clk = { 2181 .halt_reg = 0x4028, 2182 .clkr = { 2183 .enable_reg = 0x4028, 2184 .enable_mask = BIT(0), 2185 .hw.init = &(struct clk_init_data){ 2186 .name = "oxili_gfx3d_clk", 2187 .parent_names = (const char *[]){ 2188 "gfx3d_clk_src", 2189 }, 2190 .num_parents = 1, 2191 .flags = CLK_SET_RATE_PARENT, 2192 .ops = &clk_branch2_ops, 2193 }, 2194 }, 2195}; 2196 2197static struct clk_branch oxilicx_ahb_clk = { 2198 .halt_reg = 0x403c, 2199 .clkr = { 2200 .enable_reg = 0x403c, 2201 .enable_mask = BIT(0), 2202 .hw.init = &(struct clk_init_data){ 2203 .name = "oxilicx_ahb_clk", 2204 .parent_names = (const char *[]){ 2205 "mmss_ahb_clk_src", 2206 }, 2207 .num_parents = 1, 2208 .ops = &clk_branch2_ops, 2209 }, 2210 }, 2211}; 2212 2213static struct clk_branch oxilicx_axi_clk = { 2214 .halt_reg = 0x4038, 2215 .clkr = { 2216 .enable_reg = 0x4038, 2217 .enable_mask = BIT(0), 2218 .hw.init = &(struct clk_init_data){ 2219 .name = "oxilicx_axi_clk", 2220 .parent_names = (const char *[]){ 2221 "mmss_axi_clk_src", 2222 }, 2223 .num_parents = 1, 2224 .ops = &clk_branch2_ops, 2225 }, 2226 }, 2227}; 2228 2229static struct clk_branch venus0_ahb_clk = { 2230 .halt_reg = 0x1030, 2231 .clkr = { 2232 .enable_reg = 0x1030, 2233 .enable_mask = BIT(0), 2234 .hw.init = &(struct clk_init_data){ 2235 .name = "venus0_ahb_clk", 2236 .parent_names = (const char *[]){ 2237 "mmss_ahb_clk_src", 2238 }, 2239 .num_parents = 1, 2240 .ops = &clk_branch2_ops, 2241 }, 2242 }, 2243}; 2244 2245static struct clk_branch venus0_axi_clk = { 2246 .halt_reg = 0x1034, 2247 .clkr = { 2248 .enable_reg = 0x1034, 2249 .enable_mask = BIT(0), 2250 .hw.init = &(struct clk_init_data){ 2251 .name = "venus0_axi_clk", 2252 .parent_names = (const char *[]){ 2253 "mmss_axi_clk_src", 2254 }, 2255 .num_parents = 1, 2256 .ops = &clk_branch2_ops, 2257 }, 2258 }, 2259}; 2260 2261static struct clk_branch venus0_ocmemnoc_clk = { 2262 .halt_reg = 0x1038, 2263 .clkr = { 2264 .enable_reg = 0x1038, 2265 .enable_mask = BIT(0), 2266 .hw.init = &(struct clk_init_data){ 2267 .name = "venus0_ocmemnoc_clk", 2268 .parent_names = (const char *[]){ 2269 "ocmemnoc_clk_src", 2270 }, 2271 .num_parents = 1, 2272 .flags = CLK_SET_RATE_PARENT, 2273 .ops = &clk_branch2_ops, 2274 }, 2275 }, 2276}; 2277 2278static struct clk_branch venus0_vcodec0_clk = { 2279 .halt_reg = 0x1028, 2280 .clkr = { 2281 .enable_reg = 0x1028, 2282 .enable_mask = BIT(0), 2283 .hw.init = &(struct clk_init_data){ 2284 .name = "venus0_vcodec0_clk", 2285 .parent_names = (const char *[]){ 2286 "vcodec0_clk_src", 2287 }, 2288 .num_parents = 1, 2289 .flags = CLK_SET_RATE_PARENT, 2290 .ops = &clk_branch2_ops, 2291 }, 2292 }, 2293}; 2294 2295static const struct pll_config mmpll1_config = { 2296 .l = 60, 2297 .m = 25, 2298 .n = 32, 2299 .vco_val = 0x0, 2300 .vco_mask = 0x3 << 20, 2301 .pre_div_val = 0x0, 2302 .pre_div_mask = 0x7 << 12, 2303 .post_div_val = 0x0, 2304 .post_div_mask = 0x3 << 8, 2305 .mn_ena_mask = BIT(24), 2306 .main_output_mask = BIT(0), 2307}; 2308 2309static struct pll_config mmpll3_config = { 2310 .l = 48, 2311 .m = 7, 2312 .n = 16, 2313 .vco_val = 0x0, 2314 .vco_mask = 0x3 << 20, 2315 .pre_div_val = 0x0, 2316 .pre_div_mask = 0x7 << 12, 2317 .post_div_val = 0x0, 2318 .post_div_mask = 0x3 << 8, 2319 .mn_ena_mask = BIT(24), 2320 .main_output_mask = BIT(0), 2321 .aux_output_mask = BIT(1), 2322}; 2323 2324static struct gdsc venus0_gdsc = { 2325 .gdscr = 0x1024, 2326 .cxcs = (unsigned int []){ 0x1028 }, 2327 .cxc_count = 1, 2328 .resets = (unsigned int []){ VENUS0_RESET }, 2329 .reset_count = 1, 2330 .pd = { 2331 .name = "venus0", 2332 }, 2333 .pwrsts = PWRSTS_ON, 2334}; 2335 2336static struct gdsc mdss_gdsc = { 2337 .gdscr = 0x2304, 2338 .cxcs = (unsigned int []){ 0x231c, 0x2320 }, 2339 .cxc_count = 2, 2340 .pd = { 2341 .name = "mdss", 2342 }, 2343 .pwrsts = PWRSTS_RET_ON, 2344}; 2345 2346static struct gdsc camss_jpeg_gdsc = { 2347 .gdscr = 0x35a4, 2348 .cxcs = (unsigned int []){ 0x35a8, 0x35ac, 0x35b0 }, 2349 .cxc_count = 3, 2350 .pd = { 2351 .name = "camss_jpeg", 2352 }, 2353 .pwrsts = PWRSTS_OFF_ON, 2354}; 2355 2356static struct gdsc camss_vfe_gdsc = { 2357 .gdscr = 0x36a4, 2358 .cxcs = (unsigned int []){ 0x36a8, 0x36ac, 0x3704, 0x3714, 0x36b0 }, 2359 .cxc_count = 5, 2360 .pd = { 2361 .name = "camss_vfe", 2362 }, 2363 .pwrsts = PWRSTS_OFF_ON, 2364}; 2365 2366static struct gdsc oxili_gdsc = { 2367 .gdscr = 0x4024, 2368 .cxcs = (unsigned int []){ 0x4028 }, 2369 .cxc_count = 1, 2370 .pd = { 2371 .name = "oxili", 2372 }, 2373 .pwrsts = PWRSTS_OFF_ON, 2374}; 2375 2376static struct gdsc oxilicx_gdsc = { 2377 .gdscr = 0x4034, 2378 .pd = { 2379 .name = "oxilicx", 2380 }, 2381 .parent = &oxili_gdsc.pd, 2382 .pwrsts = PWRSTS_OFF_ON, 2383}; 2384 2385static struct clk_regmap *mmcc_msm8974_clocks[] = { 2386 [MMSS_AHB_CLK_SRC] = &mmss_ahb_clk_src.clkr, 2387 [MMSS_AXI_CLK_SRC] = &mmss_axi_clk_src.clkr, 2388 [OCMEMNOC_CLK_SRC] = &ocmemnoc_clk_src.clkr, 2389 [MMPLL0] = &mmpll0.clkr, 2390 [MMPLL0_VOTE] = &mmpll0_vote, 2391 [MMPLL1] = &mmpll1.clkr, 2392 [MMPLL1_VOTE] = &mmpll1_vote, 2393 [MMPLL2] = &mmpll2.clkr, 2394 [MMPLL3] = &mmpll3.clkr, 2395 [CSI0_CLK_SRC] = &csi0_clk_src.clkr, 2396 [CSI1_CLK_SRC] = &csi1_clk_src.clkr, 2397 [CSI2_CLK_SRC] = &csi2_clk_src.clkr, 2398 [CSI3_CLK_SRC] = &csi3_clk_src.clkr, 2399 [VFE0_CLK_SRC] = &vfe0_clk_src.clkr, 2400 [VFE1_CLK_SRC] = &vfe1_clk_src.clkr, 2401 [MDP_CLK_SRC] = &mdp_clk_src.clkr, 2402 [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr, 2403 [JPEG1_CLK_SRC] = &jpeg1_clk_src.clkr, 2404 [JPEG2_CLK_SRC] = &jpeg2_clk_src.clkr, 2405 [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr, 2406 [PCLK1_CLK_SRC] = &pclk1_clk_src.clkr, 2407 [VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr, 2408 [CCI_CLK_SRC] = &cci_clk_src.clkr, 2409 [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr, 2410 [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr, 2411 [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr, 2412 [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr, 2413 [MCLK2_CLK_SRC] = &mclk2_clk_src.clkr, 2414 [MCLK3_CLK_SRC] = &mclk3_clk_src.clkr, 2415 [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr, 2416 [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr, 2417 [CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr, 2418 [CPP_CLK_SRC] = &cpp_clk_src.clkr, 2419 [BYTE0_CLK_SRC] = &byte0_clk_src.clkr, 2420 [BYTE1_CLK_SRC] = &byte1_clk_src.clkr, 2421 [EDPAUX_CLK_SRC] = &edpaux_clk_src.clkr, 2422 [EDPLINK_CLK_SRC] = &edplink_clk_src.clkr, 2423 [EDPPIXEL_CLK_SRC] = &edppixel_clk_src.clkr, 2424 [ESC0_CLK_SRC] = &esc0_clk_src.clkr, 2425 [ESC1_CLK_SRC] = &esc1_clk_src.clkr, 2426 [EXTPCLK_CLK_SRC] = &extpclk_clk_src.clkr, 2427 [HDMI_CLK_SRC] = &hdmi_clk_src.clkr, 2428 [VSYNC_CLK_SRC] = &vsync_clk_src.clkr, 2429 [CAMSS_CCI_CCI_AHB_CLK] = &camss_cci_cci_ahb_clk.clkr, 2430 [CAMSS_CCI_CCI_CLK] = &camss_cci_cci_clk.clkr, 2431 [CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr, 2432 [CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr, 2433 [CAMSS_CSI0PHY_CLK] = &camss_csi0phy_clk.clkr, 2434 [CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr, 2435 [CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr, 2436 [CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr, 2437 [CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr, 2438 [CAMSS_CSI1PHY_CLK] = &camss_csi1phy_clk.clkr, 2439 [CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr, 2440 [CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr, 2441 [CAMSS_CSI2_AHB_CLK] = &camss_csi2_ahb_clk.clkr, 2442 [CAMSS_CSI2_CLK] = &camss_csi2_clk.clkr, 2443 [CAMSS_CSI2PHY_CLK] = &camss_csi2phy_clk.clkr, 2444 [CAMSS_CSI2PIX_CLK] = &camss_csi2pix_clk.clkr, 2445 [CAMSS_CSI2RDI_CLK] = &camss_csi2rdi_clk.clkr, 2446 [CAMSS_CSI3_AHB_CLK] = &camss_csi3_ahb_clk.clkr, 2447 [CAMSS_CSI3_CLK] = &camss_csi3_clk.clkr, 2448 [CAMSS_CSI3PHY_CLK] = &camss_csi3phy_clk.clkr, 2449 [CAMSS_CSI3PIX_CLK] = &camss_csi3pix_clk.clkr, 2450 [CAMSS_CSI3RDI_CLK] = &camss_csi3rdi_clk.clkr, 2451 [CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr, 2452 [CAMSS_CSI_VFE1_CLK] = &camss_csi_vfe1_clk.clkr, 2453 [CAMSS_GP0_CLK] = &camss_gp0_clk.clkr, 2454 [CAMSS_GP1_CLK] = &camss_gp1_clk.clkr, 2455 [CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr, 2456 [CAMSS_JPEG_JPEG0_CLK] = &camss_jpeg_jpeg0_clk.clkr, 2457 [CAMSS_JPEG_JPEG1_CLK] = &camss_jpeg_jpeg1_clk.clkr, 2458 [CAMSS_JPEG_JPEG2_CLK] = &camss_jpeg_jpeg2_clk.clkr, 2459 [CAMSS_JPEG_JPEG_AHB_CLK] = &camss_jpeg_jpeg_ahb_clk.clkr, 2460 [CAMSS_JPEG_JPEG_AXI_CLK] = &camss_jpeg_jpeg_axi_clk.clkr, 2461 [CAMSS_JPEG_JPEG_OCMEMNOC_CLK] = &camss_jpeg_jpeg_ocmemnoc_clk.clkr, 2462 [CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr, 2463 [CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr, 2464 [CAMSS_MCLK2_CLK] = &camss_mclk2_clk.clkr, 2465 [CAMSS_MCLK3_CLK] = &camss_mclk3_clk.clkr, 2466 [CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr, 2467 [CAMSS_PHY0_CSI0PHYTIMER_CLK] = &camss_phy0_csi0phytimer_clk.clkr, 2468 [CAMSS_PHY1_CSI1PHYTIMER_CLK] = &camss_phy1_csi1phytimer_clk.clkr, 2469 [CAMSS_PHY2_CSI2PHYTIMER_CLK] = &camss_phy2_csi2phytimer_clk.clkr, 2470 [CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr, 2471 [CAMSS_VFE_CPP_AHB_CLK] = &camss_vfe_cpp_ahb_clk.clkr, 2472 [CAMSS_VFE_CPP_CLK] = &camss_vfe_cpp_clk.clkr, 2473 [CAMSS_VFE_VFE0_CLK] = &camss_vfe_vfe0_clk.clkr, 2474 [CAMSS_VFE_VFE1_CLK] = &camss_vfe_vfe1_clk.clkr, 2475 [CAMSS_VFE_VFE_AHB_CLK] = &camss_vfe_vfe_ahb_clk.clkr, 2476 [CAMSS_VFE_VFE_AXI_CLK] = &camss_vfe_vfe_axi_clk.clkr, 2477 [CAMSS_VFE_VFE_OCMEMNOC_CLK] = &camss_vfe_vfe_ocmemnoc_clk.clkr, 2478 [MDSS_AHB_CLK] = &mdss_ahb_clk.clkr, 2479 [MDSS_AXI_CLK] = &mdss_axi_clk.clkr, 2480 [MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr, 2481 [MDSS_BYTE1_CLK] = &mdss_byte1_clk.clkr, 2482 [MDSS_EDPAUX_CLK] = &mdss_edpaux_clk.clkr, 2483 [MDSS_EDPLINK_CLK] = &mdss_edplink_clk.clkr, 2484 [MDSS_EDPPIXEL_CLK] = &mdss_edppixel_clk.clkr, 2485 [MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr, 2486 [MDSS_ESC1_CLK] = &mdss_esc1_clk.clkr, 2487 [MDSS_EXTPCLK_CLK] = &mdss_extpclk_clk.clkr, 2488 [MDSS_HDMI_AHB_CLK] = &mdss_hdmi_ahb_clk.clkr, 2489 [MDSS_HDMI_CLK] = &mdss_hdmi_clk.clkr, 2490 [MDSS_MDP_CLK] = &mdss_mdp_clk.clkr, 2491 [MDSS_MDP_LUT_CLK] = &mdss_mdp_lut_clk.clkr, 2492 [MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr, 2493 [MDSS_PCLK1_CLK] = &mdss_pclk1_clk.clkr, 2494 [MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr, 2495 [MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr, 2496 [MMSS_MMSSNOC_AHB_CLK] = &mmss_mmssnoc_ahb_clk.clkr, 2497 [MMSS_MMSSNOC_BTO_AHB_CLK] = &mmss_mmssnoc_bto_ahb_clk.clkr, 2498 [MMSS_MMSSNOC_AXI_CLK] = &mmss_mmssnoc_axi_clk.clkr, 2499 [MMSS_S0_AXI_CLK] = &mmss_s0_axi_clk.clkr, 2500 [OCMEMCX_AHB_CLK] = &ocmemcx_ahb_clk.clkr, 2501 [OCMEMCX_OCMEMNOC_CLK] = &ocmemcx_ocmemnoc_clk.clkr, 2502 [OXILI_OCMEMGX_CLK] = &oxili_ocmemgx_clk.clkr, 2503 [OCMEMNOC_CLK] = &ocmemnoc_clk.clkr, 2504 [OXILI_GFX3D_CLK] = &oxili_gfx3d_clk.clkr, 2505 [OXILICX_AHB_CLK] = &oxilicx_ahb_clk.clkr, 2506 [OXILICX_AXI_CLK] = &oxilicx_axi_clk.clkr, 2507 [VENUS0_AHB_CLK] = &venus0_ahb_clk.clkr, 2508 [VENUS0_AXI_CLK] = &venus0_axi_clk.clkr, 2509 [VENUS0_OCMEMNOC_CLK] = &venus0_ocmemnoc_clk.clkr, 2510 [VENUS0_VCODEC0_CLK] = &venus0_vcodec0_clk.clkr, 2511}; 2512 2513static const struct qcom_reset_map mmcc_msm8974_resets[] = { 2514 [SPDM_RESET] = { 0x0200 }, 2515 [SPDM_RM_RESET] = { 0x0300 }, 2516 [VENUS0_RESET] = { 0x1020 }, 2517 [MDSS_RESET] = { 0x2300 }, 2518 [CAMSS_PHY0_RESET] = { 0x3020 }, 2519 [CAMSS_PHY1_RESET] = { 0x3050 }, 2520 [CAMSS_PHY2_RESET] = { 0x3080 }, 2521 [CAMSS_CSI0_RESET] = { 0x30b0 }, 2522 [CAMSS_CSI0PHY_RESET] = { 0x30c0 }, 2523 [CAMSS_CSI0RDI_RESET] = { 0x30d0 }, 2524 [CAMSS_CSI0PIX_RESET] = { 0x30e0 }, 2525 [CAMSS_CSI1_RESET] = { 0x3120 }, 2526 [CAMSS_CSI1PHY_RESET] = { 0x3130 }, 2527 [CAMSS_CSI1RDI_RESET] = { 0x3140 }, 2528 [CAMSS_CSI1PIX_RESET] = { 0x3150 }, 2529 [CAMSS_CSI2_RESET] = { 0x3180 }, 2530 [CAMSS_CSI2PHY_RESET] = { 0x3190 }, 2531 [CAMSS_CSI2RDI_RESET] = { 0x31a0 }, 2532 [CAMSS_CSI2PIX_RESET] = { 0x31b0 }, 2533 [CAMSS_CSI3_RESET] = { 0x31e0 }, 2534 [CAMSS_CSI3PHY_RESET] = { 0x31f0 }, 2535 [CAMSS_CSI3RDI_RESET] = { 0x3200 }, 2536 [CAMSS_CSI3PIX_RESET] = { 0x3210 }, 2537 [CAMSS_ISPIF_RESET] = { 0x3220 }, 2538 [CAMSS_CCI_RESET] = { 0x3340 }, 2539 [CAMSS_MCLK0_RESET] = { 0x3380 }, 2540 [CAMSS_MCLK1_RESET] = { 0x33b0 }, 2541 [CAMSS_MCLK2_RESET] = { 0x33e0 }, 2542 [CAMSS_MCLK3_RESET] = { 0x3410 }, 2543 [CAMSS_GP0_RESET] = { 0x3440 }, 2544 [CAMSS_GP1_RESET] = { 0x3470 }, 2545 [CAMSS_TOP_RESET] = { 0x3480 }, 2546 [CAMSS_MICRO_RESET] = { 0x3490 }, 2547 [CAMSS_JPEG_RESET] = { 0x35a0 }, 2548 [CAMSS_VFE_RESET] = { 0x36a0 }, 2549 [CAMSS_CSI_VFE0_RESET] = { 0x3700 }, 2550 [CAMSS_CSI_VFE1_RESET] = { 0x3710 }, 2551 [OXILI_RESET] = { 0x4020 }, 2552 [OXILICX_RESET] = { 0x4030 }, 2553 [OCMEMCX_RESET] = { 0x4050 }, 2554 [MMSS_RBCRP_RESET] = { 0x4080 }, 2555 [MMSSNOCAHB_RESET] = { 0x5020 }, 2556 [MMSSNOCAXI_RESET] = { 0x5060 }, 2557 [OCMEMNOC_RESET] = { 0x50b0 }, 2558}; 2559 2560static struct gdsc *mmcc_msm8974_gdscs[] = { 2561 [VENUS0_GDSC] = &venus0_gdsc, 2562 [MDSS_GDSC] = &mdss_gdsc, 2563 [CAMSS_JPEG_GDSC] = &camss_jpeg_gdsc, 2564 [CAMSS_VFE_GDSC] = &camss_vfe_gdsc, 2565 [OXILI_GDSC] = &oxili_gdsc, 2566 [OXILICX_GDSC] = &oxilicx_gdsc, 2567}; 2568 2569static const struct regmap_config mmcc_msm8974_regmap_config = { 2570 .reg_bits = 32, 2571 .reg_stride = 4, 2572 .val_bits = 32, 2573 .max_register = 0x5104, 2574 .fast_io = true, 2575}; 2576 2577static const struct qcom_cc_desc mmcc_msm8974_desc = { 2578 .config = &mmcc_msm8974_regmap_config, 2579 .clks = mmcc_msm8974_clocks, 2580 .num_clks = ARRAY_SIZE(mmcc_msm8974_clocks), 2581 .resets = mmcc_msm8974_resets, 2582 .num_resets = ARRAY_SIZE(mmcc_msm8974_resets), 2583 .gdscs = mmcc_msm8974_gdscs, 2584 .num_gdscs = ARRAY_SIZE(mmcc_msm8974_gdscs), 2585}; 2586 2587static const struct of_device_id mmcc_msm8974_match_table[] = { 2588 { .compatible = "qcom,mmcc-msm8974" }, 2589 { } 2590}; 2591MODULE_DEVICE_TABLE(of, mmcc_msm8974_match_table); 2592 2593static int mmcc_msm8974_probe(struct platform_device *pdev) 2594{ 2595 struct regmap *regmap; 2596 2597 regmap = qcom_cc_map(pdev, &mmcc_msm8974_desc); 2598 if (IS_ERR(regmap)) 2599 return PTR_ERR(regmap); 2600 2601 clk_pll_configure_sr_hpm_lp(&mmpll1, regmap, &mmpll1_config, true); 2602 clk_pll_configure_sr_hpm_lp(&mmpll3, regmap, &mmpll3_config, false); 2603 2604 return qcom_cc_really_probe(pdev, &mmcc_msm8974_desc, regmap); 2605} 2606 2607static struct platform_driver mmcc_msm8974_driver = { 2608 .probe = mmcc_msm8974_probe, 2609 .driver = { 2610 .name = "mmcc-msm8974", 2611 .of_match_table = mmcc_msm8974_match_table, 2612 }, 2613}; 2614module_platform_driver(mmcc_msm8974_driver); 2615 2616MODULE_DESCRIPTION("QCOM MMCC MSM8974 Driver"); 2617MODULE_LICENSE("GPL v2"); 2618MODULE_ALIAS("platform:mmcc-msm8974"); 2619