1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2013, The Linux Foundation. All rights reserved. 4 */ 5 6#include <linux/kernel.h> 7#include <linux/bitops.h> 8#include <linux/err.h> 9#include <linux/delay.h> 10#include <linux/platform_device.h> 11#include <linux/module.h> 12#include <linux/of.h> 13#include <linux/of_device.h> 14#include <linux/clk.h> 15#include <linux/clk-provider.h> 16#include <linux/regmap.h> 17#include <linux/reset-controller.h> 18 19#include <dt-bindings/clock/qcom,mmcc-msm8960.h> 20#include <dt-bindings/reset/qcom,mmcc-msm8960.h> 21 22#include "common.h" 23#include "clk-regmap.h" 24#include "clk-pll.h" 25#include "clk-rcg.h" 26#include "clk-branch.h" 27#include "reset.h" 28 29enum { 30 P_PXO, 31 P_PLL8, 32 P_PLL2, 33 P_PLL3, 34 P_PLL15, 35 P_HDMI_PLL, 36 P_DSI1_PLL_DSICLK, 37 P_DSI2_PLL_DSICLK, 38 P_DSI1_PLL_BYTECLK, 39 P_DSI2_PLL_BYTECLK, 40}; 41 42#define F_MN(f, s, _m, _n) { .freq = f, .src = s, .m = _m, .n = _n } 43 44static const struct parent_map mmcc_pxo_pll8_pll2_map[] = { 45 { P_PXO, 0 }, 46 { P_PLL8, 2 }, 47 { P_PLL2, 1 } 48}; 49 50static const char * const mmcc_pxo_pll8_pll2[] = { 51 "pxo", 52 "pll8_vote", 53 "pll2", 54}; 55 56static const struct parent_map mmcc_pxo_pll8_pll2_pll3_map[] = { 57 { P_PXO, 0 }, 58 { P_PLL8, 2 }, 59 { P_PLL2, 1 }, 60 { P_PLL3, 3 } 61}; 62 63static const char * const mmcc_pxo_pll8_pll2_pll15[] = { 64 "pxo", 65 "pll8_vote", 66 "pll2", 67 "pll15", 68}; 69 70static const struct parent_map mmcc_pxo_pll8_pll2_pll15_map[] = { 71 { P_PXO, 0 }, 72 { P_PLL8, 2 }, 73 { P_PLL2, 1 }, 74 { P_PLL15, 3 } 75}; 76 77static const char * const mmcc_pxo_pll8_pll2_pll3[] = { 78 "pxo", 79 "pll8_vote", 80 "pll2", 81 "pll3", 82}; 83 84static const struct parent_map mmcc_pxo_dsi2_dsi1_map[] = { 85 { P_PXO, 0 }, 86 { P_DSI2_PLL_DSICLK, 1 }, 87 { P_DSI1_PLL_DSICLK, 3 }, 88}; 89 90static const char * const mmcc_pxo_dsi2_dsi1[] = { 91 "pxo", 92 "dsi2pll", 93 "dsi1pll", 94}; 95 96static const struct parent_map mmcc_pxo_dsi1_dsi2_byte_map[] = { 97 { P_PXO, 0 }, 98 { P_DSI1_PLL_BYTECLK, 1 }, 99 { P_DSI2_PLL_BYTECLK, 2 }, 100}; 101 102static const char * const mmcc_pxo_dsi1_dsi2_byte[] = { 103 "pxo", 104 "dsi1pllbyte", 105 "dsi2pllbyte", 106}; 107 108static struct clk_pll pll2 = { 109 .l_reg = 0x320, 110 .m_reg = 0x324, 111 .n_reg = 0x328, 112 .config_reg = 0x32c, 113 .mode_reg = 0x31c, 114 .status_reg = 0x334, 115 .status_bit = 16, 116 .clkr.hw.init = &(struct clk_init_data){ 117 .name = "pll2", 118 .parent_names = (const char *[]){ "pxo" }, 119 .num_parents = 1, 120 .ops = &clk_pll_ops, 121 }, 122}; 123 124static struct clk_pll pll15 = { 125 .l_reg = 0x33c, 126 .m_reg = 0x340, 127 .n_reg = 0x344, 128 .config_reg = 0x348, 129 .mode_reg = 0x338, 130 .status_reg = 0x350, 131 .status_bit = 16, 132 .clkr.hw.init = &(struct clk_init_data){ 133 .name = "pll15", 134 .parent_names = (const char *[]){ "pxo" }, 135 .num_parents = 1, 136 .ops = &clk_pll_ops, 137 }, 138}; 139 140static const struct pll_config pll15_config = { 141 .l = 33, 142 .m = 1, 143 .n = 3, 144 .vco_val = 0x2 << 16, 145 .vco_mask = 0x3 << 16, 146 .pre_div_val = 0x0, 147 .pre_div_mask = BIT(19), 148 .post_div_val = 0x0, 149 .post_div_mask = 0x3 << 20, 150 .mn_ena_mask = BIT(22), 151 .main_output_mask = BIT(23), 152}; 153 154static struct freq_tbl clk_tbl_cam[] = { 155 { 6000000, P_PLL8, 4, 1, 16 }, 156 { 8000000, P_PLL8, 4, 1, 12 }, 157 { 12000000, P_PLL8, 4, 1, 8 }, 158 { 16000000, P_PLL8, 4, 1, 6 }, 159 { 19200000, P_PLL8, 4, 1, 5 }, 160 { 24000000, P_PLL8, 4, 1, 4 }, 161 { 32000000, P_PLL8, 4, 1, 3 }, 162 { 48000000, P_PLL8, 4, 1, 2 }, 163 { 64000000, P_PLL8, 3, 1, 2 }, 164 { 96000000, P_PLL8, 4, 0, 0 }, 165 { 128000000, P_PLL8, 3, 0, 0 }, 166 { } 167}; 168 169static struct clk_rcg camclk0_src = { 170 .ns_reg = 0x0148, 171 .md_reg = 0x0144, 172 .mn = { 173 .mnctr_en_bit = 5, 174 .mnctr_reset_bit = 8, 175 .reset_in_cc = true, 176 .mnctr_mode_shift = 6, 177 .n_val_shift = 24, 178 .m_val_shift = 8, 179 .width = 8, 180 }, 181 .p = { 182 .pre_div_shift = 14, 183 .pre_div_width = 2, 184 }, 185 .s = { 186 .src_sel_shift = 0, 187 .parent_map = mmcc_pxo_pll8_pll2_map, 188 }, 189 .freq_tbl = clk_tbl_cam, 190 .clkr = { 191 .enable_reg = 0x0140, 192 .enable_mask = BIT(2), 193 .hw.init = &(struct clk_init_data){ 194 .name = "camclk0_src", 195 .parent_names = mmcc_pxo_pll8_pll2, 196 .num_parents = 3, 197 .ops = &clk_rcg_ops, 198 }, 199 }, 200}; 201 202static struct clk_branch camclk0_clk = { 203 .halt_reg = 0x01e8, 204 .halt_bit = 15, 205 .clkr = { 206 .enable_reg = 0x0140, 207 .enable_mask = BIT(0), 208 .hw.init = &(struct clk_init_data){ 209 .name = "camclk0_clk", 210 .parent_names = (const char *[]){ "camclk0_src" }, 211 .num_parents = 1, 212 .ops = &clk_branch_ops, 213 }, 214 }, 215 216}; 217 218static struct clk_rcg camclk1_src = { 219 .ns_reg = 0x015c, 220 .md_reg = 0x0158, 221 .mn = { 222 .mnctr_en_bit = 5, 223 .mnctr_reset_bit = 8, 224 .reset_in_cc = true, 225 .mnctr_mode_shift = 6, 226 .n_val_shift = 24, 227 .m_val_shift = 8, 228 .width = 8, 229 }, 230 .p = { 231 .pre_div_shift = 14, 232 .pre_div_width = 2, 233 }, 234 .s = { 235 .src_sel_shift = 0, 236 .parent_map = mmcc_pxo_pll8_pll2_map, 237 }, 238 .freq_tbl = clk_tbl_cam, 239 .clkr = { 240 .enable_reg = 0x0154, 241 .enable_mask = BIT(2), 242 .hw.init = &(struct clk_init_data){ 243 .name = "camclk1_src", 244 .parent_names = mmcc_pxo_pll8_pll2, 245 .num_parents = 3, 246 .ops = &clk_rcg_ops, 247 }, 248 }, 249}; 250 251static struct clk_branch camclk1_clk = { 252 .halt_reg = 0x01e8, 253 .halt_bit = 16, 254 .clkr = { 255 .enable_reg = 0x0154, 256 .enable_mask = BIT(0), 257 .hw.init = &(struct clk_init_data){ 258 .name = "camclk1_clk", 259 .parent_names = (const char *[]){ "camclk1_src" }, 260 .num_parents = 1, 261 .ops = &clk_branch_ops, 262 }, 263 }, 264 265}; 266 267static struct clk_rcg camclk2_src = { 268 .ns_reg = 0x0228, 269 .md_reg = 0x0224, 270 .mn = { 271 .mnctr_en_bit = 5, 272 .mnctr_reset_bit = 8, 273 .reset_in_cc = true, 274 .mnctr_mode_shift = 6, 275 .n_val_shift = 24, 276 .m_val_shift = 8, 277 .width = 8, 278 }, 279 .p = { 280 .pre_div_shift = 14, 281 .pre_div_width = 2, 282 }, 283 .s = { 284 .src_sel_shift = 0, 285 .parent_map = mmcc_pxo_pll8_pll2_map, 286 }, 287 .freq_tbl = clk_tbl_cam, 288 .clkr = { 289 .enable_reg = 0x0220, 290 .enable_mask = BIT(2), 291 .hw.init = &(struct clk_init_data){ 292 .name = "camclk2_src", 293 .parent_names = mmcc_pxo_pll8_pll2, 294 .num_parents = 3, 295 .ops = &clk_rcg_ops, 296 }, 297 }, 298}; 299 300static struct clk_branch camclk2_clk = { 301 .halt_reg = 0x01e8, 302 .halt_bit = 16, 303 .clkr = { 304 .enable_reg = 0x0220, 305 .enable_mask = BIT(0), 306 .hw.init = &(struct clk_init_data){ 307 .name = "camclk2_clk", 308 .parent_names = (const char *[]){ "camclk2_src" }, 309 .num_parents = 1, 310 .ops = &clk_branch_ops, 311 }, 312 }, 313 314}; 315 316static struct freq_tbl clk_tbl_csi[] = { 317 { 27000000, P_PXO, 1, 0, 0 }, 318 { 85330000, P_PLL8, 1, 2, 9 }, 319 { 177780000, P_PLL2, 1, 2, 9 }, 320 { } 321}; 322 323static struct clk_rcg csi0_src = { 324 .ns_reg = 0x0048, 325 .md_reg = 0x0044, 326 .mn = { 327 .mnctr_en_bit = 5, 328 .mnctr_reset_bit = 7, 329 .mnctr_mode_shift = 6, 330 .n_val_shift = 24, 331 .m_val_shift = 8, 332 .width = 8, 333 }, 334 .p = { 335 .pre_div_shift = 14, 336 .pre_div_width = 2, 337 }, 338 .s = { 339 .src_sel_shift = 0, 340 .parent_map = mmcc_pxo_pll8_pll2_map, 341 }, 342 .freq_tbl = clk_tbl_csi, 343 .clkr = { 344 .enable_reg = 0x0040, 345 .enable_mask = BIT(2), 346 .hw.init = &(struct clk_init_data){ 347 .name = "csi0_src", 348 .parent_names = mmcc_pxo_pll8_pll2, 349 .num_parents = 3, 350 .ops = &clk_rcg_ops, 351 }, 352 }, 353}; 354 355static struct clk_branch csi0_clk = { 356 .halt_reg = 0x01cc, 357 .halt_bit = 13, 358 .clkr = { 359 .enable_reg = 0x0040, 360 .enable_mask = BIT(0), 361 .hw.init = &(struct clk_init_data){ 362 .parent_names = (const char *[]){ "csi0_src" }, 363 .num_parents = 1, 364 .name = "csi0_clk", 365 .ops = &clk_branch_ops, 366 .flags = CLK_SET_RATE_PARENT, 367 }, 368 }, 369}; 370 371static struct clk_branch csi0_phy_clk = { 372 .halt_reg = 0x01e8, 373 .halt_bit = 9, 374 .clkr = { 375 .enable_reg = 0x0040, 376 .enable_mask = BIT(8), 377 .hw.init = &(struct clk_init_data){ 378 .parent_names = (const char *[]){ "csi0_src" }, 379 .num_parents = 1, 380 .name = "csi0_phy_clk", 381 .ops = &clk_branch_ops, 382 .flags = CLK_SET_RATE_PARENT, 383 }, 384 }, 385}; 386 387static struct clk_rcg csi1_src = { 388 .ns_reg = 0x0010, 389 .md_reg = 0x0028, 390 .mn = { 391 .mnctr_en_bit = 5, 392 .mnctr_reset_bit = 7, 393 .mnctr_mode_shift = 6, 394 .n_val_shift = 24, 395 .m_val_shift = 8, 396 .width = 8, 397 }, 398 .p = { 399 .pre_div_shift = 14, 400 .pre_div_width = 2, 401 }, 402 .s = { 403 .src_sel_shift = 0, 404 .parent_map = mmcc_pxo_pll8_pll2_map, 405 }, 406 .freq_tbl = clk_tbl_csi, 407 .clkr = { 408 .enable_reg = 0x0024, 409 .enable_mask = BIT(2), 410 .hw.init = &(struct clk_init_data){ 411 .name = "csi1_src", 412 .parent_names = mmcc_pxo_pll8_pll2, 413 .num_parents = 3, 414 .ops = &clk_rcg_ops, 415 }, 416 }, 417}; 418 419static struct clk_branch csi1_clk = { 420 .halt_reg = 0x01cc, 421 .halt_bit = 14, 422 .clkr = { 423 .enable_reg = 0x0024, 424 .enable_mask = BIT(0), 425 .hw.init = &(struct clk_init_data){ 426 .parent_names = (const char *[]){ "csi1_src" }, 427 .num_parents = 1, 428 .name = "csi1_clk", 429 .ops = &clk_branch_ops, 430 .flags = CLK_SET_RATE_PARENT, 431 }, 432 }, 433}; 434 435static struct clk_branch csi1_phy_clk = { 436 .halt_reg = 0x01e8, 437 .halt_bit = 10, 438 .clkr = { 439 .enable_reg = 0x0024, 440 .enable_mask = BIT(8), 441 .hw.init = &(struct clk_init_data){ 442 .parent_names = (const char *[]){ "csi1_src" }, 443 .num_parents = 1, 444 .name = "csi1_phy_clk", 445 .ops = &clk_branch_ops, 446 .flags = CLK_SET_RATE_PARENT, 447 }, 448 }, 449}; 450 451static struct clk_rcg csi2_src = { 452 .ns_reg = 0x0234, 453 .md_reg = 0x022c, 454 .mn = { 455 .mnctr_en_bit = 5, 456 .mnctr_reset_bit = 7, 457 .mnctr_mode_shift = 6, 458 .n_val_shift = 24, 459 .m_val_shift = 8, 460 .width = 8, 461 }, 462 .p = { 463 .pre_div_shift = 14, 464 .pre_div_width = 2, 465 }, 466 .s = { 467 .src_sel_shift = 0, 468 .parent_map = mmcc_pxo_pll8_pll2_map, 469 }, 470 .freq_tbl = clk_tbl_csi, 471 .clkr = { 472 .enable_reg = 0x022c, 473 .enable_mask = BIT(2), 474 .hw.init = &(struct clk_init_data){ 475 .name = "csi2_src", 476 .parent_names = mmcc_pxo_pll8_pll2, 477 .num_parents = 3, 478 .ops = &clk_rcg_ops, 479 }, 480 }, 481}; 482 483static struct clk_branch csi2_clk = { 484 .halt_reg = 0x01cc, 485 .halt_bit = 29, 486 .clkr = { 487 .enable_reg = 0x022c, 488 .enable_mask = BIT(0), 489 .hw.init = &(struct clk_init_data){ 490 .parent_names = (const char *[]){ "csi2_src" }, 491 .num_parents = 1, 492 .name = "csi2_clk", 493 .ops = &clk_branch_ops, 494 .flags = CLK_SET_RATE_PARENT, 495 }, 496 }, 497}; 498 499static struct clk_branch csi2_phy_clk = { 500 .halt_reg = 0x01e8, 501 .halt_bit = 29, 502 .clkr = { 503 .enable_reg = 0x022c, 504 .enable_mask = BIT(8), 505 .hw.init = &(struct clk_init_data){ 506 .parent_names = (const char *[]){ "csi2_src" }, 507 .num_parents = 1, 508 .name = "csi2_phy_clk", 509 .ops = &clk_branch_ops, 510 .flags = CLK_SET_RATE_PARENT, 511 }, 512 }, 513}; 514 515struct clk_pix_rdi { 516 u32 s_reg; 517 u32 s_mask; 518 u32 s2_reg; 519 u32 s2_mask; 520 struct clk_regmap clkr; 521}; 522 523#define to_clk_pix_rdi(_hw) \ 524 container_of(to_clk_regmap(_hw), struct clk_pix_rdi, clkr) 525 526static int pix_rdi_set_parent(struct clk_hw *hw, u8 index) 527{ 528 int i; 529 int ret = 0; 530 u32 val; 531 struct clk_pix_rdi *rdi = to_clk_pix_rdi(hw); 532 int num_parents = clk_hw_get_num_parents(hw); 533 534 /* 535 * These clocks select three inputs via two muxes. One mux selects 536 * between csi0 and csi1 and the second mux selects between that mux's 537 * output and csi2. The source and destination selections for each 538 * mux must be clocking for the switch to succeed so just turn on 539 * all three sources because it's easier than figuring out what source 540 * needs to be on at what time. 541 */ 542 for (i = 0; i < num_parents; i++) { 543 struct clk_hw *p = clk_hw_get_parent_by_index(hw, i); 544 ret = clk_prepare_enable(p->clk); 545 if (ret) 546 goto err; 547 } 548 549 if (index == 2) 550 val = rdi->s2_mask; 551 else 552 val = 0; 553 regmap_update_bits(rdi->clkr.regmap, rdi->s2_reg, rdi->s2_mask, val); 554 /* 555 * Wait at least 6 cycles of slowest clock 556 * for the glitch-free MUX to fully switch sources. 557 */ 558 udelay(1); 559 560 if (index == 1) 561 val = rdi->s_mask; 562 else 563 val = 0; 564 regmap_update_bits(rdi->clkr.regmap, rdi->s_reg, rdi->s_mask, val); 565 /* 566 * Wait at least 6 cycles of slowest clock 567 * for the glitch-free MUX to fully switch sources. 568 */ 569 udelay(1); 570 571err: 572 for (i--; i >= 0; i--) { 573 struct clk_hw *p = clk_hw_get_parent_by_index(hw, i); 574 clk_disable_unprepare(p->clk); 575 } 576 577 return ret; 578} 579 580static u8 pix_rdi_get_parent(struct clk_hw *hw) 581{ 582 u32 val; 583 struct clk_pix_rdi *rdi = to_clk_pix_rdi(hw); 584 585 586 regmap_read(rdi->clkr.regmap, rdi->s2_reg, &val); 587 if (val & rdi->s2_mask) 588 return 2; 589 590 regmap_read(rdi->clkr.regmap, rdi->s_reg, &val); 591 if (val & rdi->s_mask) 592 return 1; 593 594 return 0; 595} 596 597static const struct clk_ops clk_ops_pix_rdi = { 598 .enable = clk_enable_regmap, 599 .disable = clk_disable_regmap, 600 .set_parent = pix_rdi_set_parent, 601 .get_parent = pix_rdi_get_parent, 602 .determine_rate = __clk_mux_determine_rate, 603}; 604 605static const char * const pix_rdi_parents[] = { 606 "csi0_clk", 607 "csi1_clk", 608 "csi2_clk", 609}; 610 611static struct clk_pix_rdi csi_pix_clk = { 612 .s_reg = 0x0058, 613 .s_mask = BIT(25), 614 .s2_reg = 0x0238, 615 .s2_mask = BIT(13), 616 .clkr = { 617 .enable_reg = 0x0058, 618 .enable_mask = BIT(26), 619 .hw.init = &(struct clk_init_data){ 620 .name = "csi_pix_clk", 621 .parent_names = pix_rdi_parents, 622 .num_parents = 3, 623 .ops = &clk_ops_pix_rdi, 624 }, 625 }, 626}; 627 628static struct clk_pix_rdi csi_pix1_clk = { 629 .s_reg = 0x0238, 630 .s_mask = BIT(8), 631 .s2_reg = 0x0238, 632 .s2_mask = BIT(9), 633 .clkr = { 634 .enable_reg = 0x0238, 635 .enable_mask = BIT(10), 636 .hw.init = &(struct clk_init_data){ 637 .name = "csi_pix1_clk", 638 .parent_names = pix_rdi_parents, 639 .num_parents = 3, 640 .ops = &clk_ops_pix_rdi, 641 }, 642 }, 643}; 644 645static struct clk_pix_rdi csi_rdi_clk = { 646 .s_reg = 0x0058, 647 .s_mask = BIT(12), 648 .s2_reg = 0x0238, 649 .s2_mask = BIT(12), 650 .clkr = { 651 .enable_reg = 0x0058, 652 .enable_mask = BIT(13), 653 .hw.init = &(struct clk_init_data){ 654 .name = "csi_rdi_clk", 655 .parent_names = pix_rdi_parents, 656 .num_parents = 3, 657 .ops = &clk_ops_pix_rdi, 658 }, 659 }, 660}; 661 662static struct clk_pix_rdi csi_rdi1_clk = { 663 .s_reg = 0x0238, 664 .s_mask = BIT(0), 665 .s2_reg = 0x0238, 666 .s2_mask = BIT(1), 667 .clkr = { 668 .enable_reg = 0x0238, 669 .enable_mask = BIT(2), 670 .hw.init = &(struct clk_init_data){ 671 .name = "csi_rdi1_clk", 672 .parent_names = pix_rdi_parents, 673 .num_parents = 3, 674 .ops = &clk_ops_pix_rdi, 675 }, 676 }, 677}; 678 679static struct clk_pix_rdi csi_rdi2_clk = { 680 .s_reg = 0x0238, 681 .s_mask = BIT(4), 682 .s2_reg = 0x0238, 683 .s2_mask = BIT(5), 684 .clkr = { 685 .enable_reg = 0x0238, 686 .enable_mask = BIT(6), 687 .hw.init = &(struct clk_init_data){ 688 .name = "csi_rdi2_clk", 689 .parent_names = pix_rdi_parents, 690 .num_parents = 3, 691 .ops = &clk_ops_pix_rdi, 692 }, 693 }, 694}; 695 696static struct freq_tbl clk_tbl_csiphytimer[] = { 697 { 85330000, P_PLL8, 1, 2, 9 }, 698 { 177780000, P_PLL2, 1, 2, 9 }, 699 { } 700}; 701 702static struct clk_rcg csiphytimer_src = { 703 .ns_reg = 0x0168, 704 .md_reg = 0x0164, 705 .mn = { 706 .mnctr_en_bit = 5, 707 .mnctr_reset_bit = 8, 708 .reset_in_cc = true, 709 .mnctr_mode_shift = 6, 710 .n_val_shift = 24, 711 .m_val_shift = 8, 712 .width = 8, 713 }, 714 .p = { 715 .pre_div_shift = 14, 716 .pre_div_width = 2, 717 }, 718 .s = { 719 .src_sel_shift = 0, 720 .parent_map = mmcc_pxo_pll8_pll2_map, 721 }, 722 .freq_tbl = clk_tbl_csiphytimer, 723 .clkr = { 724 .enable_reg = 0x0160, 725 .enable_mask = BIT(2), 726 .hw.init = &(struct clk_init_data){ 727 .name = "csiphytimer_src", 728 .parent_names = mmcc_pxo_pll8_pll2, 729 .num_parents = 3, 730 .ops = &clk_rcg_ops, 731 }, 732 }, 733}; 734 735static const char * const csixphy_timer_src[] = { "csiphytimer_src" }; 736 737static struct clk_branch csiphy0_timer_clk = { 738 .halt_reg = 0x01e8, 739 .halt_bit = 17, 740 .clkr = { 741 .enable_reg = 0x0160, 742 .enable_mask = BIT(0), 743 .hw.init = &(struct clk_init_data){ 744 .parent_names = csixphy_timer_src, 745 .num_parents = 1, 746 .name = "csiphy0_timer_clk", 747 .ops = &clk_branch_ops, 748 .flags = CLK_SET_RATE_PARENT, 749 }, 750 }, 751}; 752 753static struct clk_branch csiphy1_timer_clk = { 754 .halt_reg = 0x01e8, 755 .halt_bit = 18, 756 .clkr = { 757 .enable_reg = 0x0160, 758 .enable_mask = BIT(9), 759 .hw.init = &(struct clk_init_data){ 760 .parent_names = csixphy_timer_src, 761 .num_parents = 1, 762 .name = "csiphy1_timer_clk", 763 .ops = &clk_branch_ops, 764 .flags = CLK_SET_RATE_PARENT, 765 }, 766 }, 767}; 768 769static struct clk_branch csiphy2_timer_clk = { 770 .halt_reg = 0x01e8, 771 .halt_bit = 30, 772 .clkr = { 773 .enable_reg = 0x0160, 774 .enable_mask = BIT(11), 775 .hw.init = &(struct clk_init_data){ 776 .parent_names = csixphy_timer_src, 777 .num_parents = 1, 778 .name = "csiphy2_timer_clk", 779 .ops = &clk_branch_ops, 780 .flags = CLK_SET_RATE_PARENT, 781 }, 782 }, 783}; 784 785static struct freq_tbl clk_tbl_gfx2d[] = { 786 F_MN( 27000000, P_PXO, 1, 0), 787 F_MN( 48000000, P_PLL8, 1, 8), 788 F_MN( 54857000, P_PLL8, 1, 7), 789 F_MN( 64000000, P_PLL8, 1, 6), 790 F_MN( 76800000, P_PLL8, 1, 5), 791 F_MN( 96000000, P_PLL8, 1, 4), 792 F_MN(128000000, P_PLL8, 1, 3), 793 F_MN(145455000, P_PLL2, 2, 11), 794 F_MN(160000000, P_PLL2, 1, 5), 795 F_MN(177778000, P_PLL2, 2, 9), 796 F_MN(200000000, P_PLL2, 1, 4), 797 F_MN(228571000, P_PLL2, 2, 7), 798 { } 799}; 800 801static struct clk_dyn_rcg gfx2d0_src = { 802 .ns_reg[0] = 0x0070, 803 .ns_reg[1] = 0x0070, 804 .md_reg[0] = 0x0064, 805 .md_reg[1] = 0x0068, 806 .bank_reg = 0x0060, 807 .mn[0] = { 808 .mnctr_en_bit = 8, 809 .mnctr_reset_bit = 25, 810 .mnctr_mode_shift = 9, 811 .n_val_shift = 20, 812 .m_val_shift = 4, 813 .width = 4, 814 }, 815 .mn[1] = { 816 .mnctr_en_bit = 5, 817 .mnctr_reset_bit = 24, 818 .mnctr_mode_shift = 6, 819 .n_val_shift = 16, 820 .m_val_shift = 4, 821 .width = 4, 822 }, 823 .s[0] = { 824 .src_sel_shift = 3, 825 .parent_map = mmcc_pxo_pll8_pll2_map, 826 }, 827 .s[1] = { 828 .src_sel_shift = 0, 829 .parent_map = mmcc_pxo_pll8_pll2_map, 830 }, 831 .mux_sel_bit = 11, 832 .freq_tbl = clk_tbl_gfx2d, 833 .clkr = { 834 .enable_reg = 0x0060, 835 .enable_mask = BIT(2), 836 .hw.init = &(struct clk_init_data){ 837 .name = "gfx2d0_src", 838 .parent_names = mmcc_pxo_pll8_pll2, 839 .num_parents = 3, 840 .ops = &clk_dyn_rcg_ops, 841 }, 842 }, 843}; 844 845static struct clk_branch gfx2d0_clk = { 846 .halt_reg = 0x01c8, 847 .halt_bit = 9, 848 .clkr = { 849 .enable_reg = 0x0060, 850 .enable_mask = BIT(0), 851 .hw.init = &(struct clk_init_data){ 852 .name = "gfx2d0_clk", 853 .parent_names = (const char *[]){ "gfx2d0_src" }, 854 .num_parents = 1, 855 .ops = &clk_branch_ops, 856 .flags = CLK_SET_RATE_PARENT, 857 }, 858 }, 859}; 860 861static struct clk_dyn_rcg gfx2d1_src = { 862 .ns_reg[0] = 0x007c, 863 .ns_reg[1] = 0x007c, 864 .md_reg[0] = 0x0078, 865 .md_reg[1] = 0x006c, 866 .bank_reg = 0x0074, 867 .mn[0] = { 868 .mnctr_en_bit = 8, 869 .mnctr_reset_bit = 25, 870 .mnctr_mode_shift = 9, 871 .n_val_shift = 20, 872 .m_val_shift = 4, 873 .width = 4, 874 }, 875 .mn[1] = { 876 .mnctr_en_bit = 5, 877 .mnctr_reset_bit = 24, 878 .mnctr_mode_shift = 6, 879 .n_val_shift = 16, 880 .m_val_shift = 4, 881 .width = 4, 882 }, 883 .s[0] = { 884 .src_sel_shift = 3, 885 .parent_map = mmcc_pxo_pll8_pll2_map, 886 }, 887 .s[1] = { 888 .src_sel_shift = 0, 889 .parent_map = mmcc_pxo_pll8_pll2_map, 890 }, 891 .mux_sel_bit = 11, 892 .freq_tbl = clk_tbl_gfx2d, 893 .clkr = { 894 .enable_reg = 0x0074, 895 .enable_mask = BIT(2), 896 .hw.init = &(struct clk_init_data){ 897 .name = "gfx2d1_src", 898 .parent_names = mmcc_pxo_pll8_pll2, 899 .num_parents = 3, 900 .ops = &clk_dyn_rcg_ops, 901 }, 902 }, 903}; 904 905static struct clk_branch gfx2d1_clk = { 906 .halt_reg = 0x01c8, 907 .halt_bit = 14, 908 .clkr = { 909 .enable_reg = 0x0074, 910 .enable_mask = BIT(0), 911 .hw.init = &(struct clk_init_data){ 912 .name = "gfx2d1_clk", 913 .parent_names = (const char *[]){ "gfx2d1_src" }, 914 .num_parents = 1, 915 .ops = &clk_branch_ops, 916 .flags = CLK_SET_RATE_PARENT, 917 }, 918 }, 919}; 920 921static struct freq_tbl clk_tbl_gfx3d[] = { 922 F_MN( 27000000, P_PXO, 1, 0), 923 F_MN( 48000000, P_PLL8, 1, 8), 924 F_MN( 54857000, P_PLL8, 1, 7), 925 F_MN( 64000000, P_PLL8, 1, 6), 926 F_MN( 76800000, P_PLL8, 1, 5), 927 F_MN( 96000000, P_PLL8, 1, 4), 928 F_MN(128000000, P_PLL8, 1, 3), 929 F_MN(145455000, P_PLL2, 2, 11), 930 F_MN(160000000, P_PLL2, 1, 5), 931 F_MN(177778000, P_PLL2, 2, 9), 932 F_MN(200000000, P_PLL2, 1, 4), 933 F_MN(228571000, P_PLL2, 2, 7), 934 F_MN(266667000, P_PLL2, 1, 3), 935 F_MN(300000000, P_PLL3, 1, 4), 936 F_MN(320000000, P_PLL2, 2, 5), 937 F_MN(400000000, P_PLL2, 1, 2), 938 { } 939}; 940 941static struct freq_tbl clk_tbl_gfx3d_8064[] = { 942 F_MN( 27000000, P_PXO, 0, 0), 943 F_MN( 48000000, P_PLL8, 1, 8), 944 F_MN( 54857000, P_PLL8, 1, 7), 945 F_MN( 64000000, P_PLL8, 1, 6), 946 F_MN( 76800000, P_PLL8, 1, 5), 947 F_MN( 96000000, P_PLL8, 1, 4), 948 F_MN(128000000, P_PLL8, 1, 3), 949 F_MN(145455000, P_PLL2, 2, 11), 950 F_MN(160000000, P_PLL2, 1, 5), 951 F_MN(177778000, P_PLL2, 2, 9), 952 F_MN(192000000, P_PLL8, 1, 2), 953 F_MN(200000000, P_PLL2, 1, 4), 954 F_MN(228571000, P_PLL2, 2, 7), 955 F_MN(266667000, P_PLL2, 1, 3), 956 F_MN(320000000, P_PLL2, 2, 5), 957 F_MN(400000000, P_PLL2, 1, 2), 958 F_MN(450000000, P_PLL15, 1, 2), 959 { } 960}; 961 962static struct clk_dyn_rcg gfx3d_src = { 963 .ns_reg[0] = 0x008c, 964 .ns_reg[1] = 0x008c, 965 .md_reg[0] = 0x0084, 966 .md_reg[1] = 0x0088, 967 .bank_reg = 0x0080, 968 .mn[0] = { 969 .mnctr_en_bit = 8, 970 .mnctr_reset_bit = 25, 971 .mnctr_mode_shift = 9, 972 .n_val_shift = 18, 973 .m_val_shift = 4, 974 .width = 4, 975 }, 976 .mn[1] = { 977 .mnctr_en_bit = 5, 978 .mnctr_reset_bit = 24, 979 .mnctr_mode_shift = 6, 980 .n_val_shift = 14, 981 .m_val_shift = 4, 982 .width = 4, 983 }, 984 .s[0] = { 985 .src_sel_shift = 3, 986 .parent_map = mmcc_pxo_pll8_pll2_pll3_map, 987 }, 988 .s[1] = { 989 .src_sel_shift = 0, 990 .parent_map = mmcc_pxo_pll8_pll2_pll3_map, 991 }, 992 .mux_sel_bit = 11, 993 .freq_tbl = clk_tbl_gfx3d, 994 .clkr = { 995 .enable_reg = 0x0080, 996 .enable_mask = BIT(2), 997 .hw.init = &(struct clk_init_data){ 998 .name = "gfx3d_src", 999 .parent_names = mmcc_pxo_pll8_pll2_pll3, 1000 .num_parents = 4, 1001 .ops = &clk_dyn_rcg_ops, 1002 }, 1003 }, 1004}; 1005 1006static const struct clk_init_data gfx3d_8064_init = { 1007 .name = "gfx3d_src", 1008 .parent_names = mmcc_pxo_pll8_pll2_pll15, 1009 .num_parents = 4, 1010 .ops = &clk_dyn_rcg_ops, 1011}; 1012 1013static struct clk_branch gfx3d_clk = { 1014 .halt_reg = 0x01c8, 1015 .halt_bit = 4, 1016 .clkr = { 1017 .enable_reg = 0x0080, 1018 .enable_mask = BIT(0), 1019 .hw.init = &(struct clk_init_data){ 1020 .name = "gfx3d_clk", 1021 .parent_names = (const char *[]){ "gfx3d_src" }, 1022 .num_parents = 1, 1023 .ops = &clk_branch_ops, 1024 .flags = CLK_SET_RATE_PARENT, 1025 }, 1026 }, 1027}; 1028 1029static struct freq_tbl clk_tbl_vcap[] = { 1030 F_MN( 27000000, P_PXO, 0, 0), 1031 F_MN( 54860000, P_PLL8, 1, 7), 1032 F_MN( 64000000, P_PLL8, 1, 6), 1033 F_MN( 76800000, P_PLL8, 1, 5), 1034 F_MN(128000000, P_PLL8, 1, 3), 1035 F_MN(160000000, P_PLL2, 1, 5), 1036 F_MN(200000000, P_PLL2, 1, 4), 1037 { } 1038}; 1039 1040static struct clk_dyn_rcg vcap_src = { 1041 .ns_reg[0] = 0x021c, 1042 .ns_reg[1] = 0x021c, 1043 .md_reg[0] = 0x01ec, 1044 .md_reg[1] = 0x0218, 1045 .bank_reg = 0x0178, 1046 .mn[0] = { 1047 .mnctr_en_bit = 8, 1048 .mnctr_reset_bit = 23, 1049 .mnctr_mode_shift = 9, 1050 .n_val_shift = 18, 1051 .m_val_shift = 4, 1052 .width = 4, 1053 }, 1054 .mn[1] = { 1055 .mnctr_en_bit = 5, 1056 .mnctr_reset_bit = 22, 1057 .mnctr_mode_shift = 6, 1058 .n_val_shift = 14, 1059 .m_val_shift = 4, 1060 .width = 4, 1061 }, 1062 .s[0] = { 1063 .src_sel_shift = 3, 1064 .parent_map = mmcc_pxo_pll8_pll2_map, 1065 }, 1066 .s[1] = { 1067 .src_sel_shift = 0, 1068 .parent_map = mmcc_pxo_pll8_pll2_map, 1069 }, 1070 .mux_sel_bit = 11, 1071 .freq_tbl = clk_tbl_vcap, 1072 .clkr = { 1073 .enable_reg = 0x0178, 1074 .enable_mask = BIT(2), 1075 .hw.init = &(struct clk_init_data){ 1076 .name = "vcap_src", 1077 .parent_names = mmcc_pxo_pll8_pll2, 1078 .num_parents = 3, 1079 .ops = &clk_dyn_rcg_ops, 1080 }, 1081 }, 1082}; 1083 1084static struct clk_branch vcap_clk = { 1085 .halt_reg = 0x0240, 1086 .halt_bit = 15, 1087 .clkr = { 1088 .enable_reg = 0x0178, 1089 .enable_mask = BIT(0), 1090 .hw.init = &(struct clk_init_data){ 1091 .name = "vcap_clk", 1092 .parent_names = (const char *[]){ "vcap_src" }, 1093 .num_parents = 1, 1094 .ops = &clk_branch_ops, 1095 .flags = CLK_SET_RATE_PARENT, 1096 }, 1097 }, 1098}; 1099 1100static struct clk_branch vcap_npl_clk = { 1101 .halt_reg = 0x0240, 1102 .halt_bit = 25, 1103 .clkr = { 1104 .enable_reg = 0x0178, 1105 .enable_mask = BIT(13), 1106 .hw.init = &(struct clk_init_data){ 1107 .name = "vcap_npl_clk", 1108 .parent_names = (const char *[]){ "vcap_src" }, 1109 .num_parents = 1, 1110 .ops = &clk_branch_ops, 1111 .flags = CLK_SET_RATE_PARENT, 1112 }, 1113 }, 1114}; 1115 1116static struct freq_tbl clk_tbl_ijpeg[] = { 1117 { 27000000, P_PXO, 1, 0, 0 }, 1118 { 36570000, P_PLL8, 1, 2, 21 }, 1119 { 54860000, P_PLL8, 7, 0, 0 }, 1120 { 96000000, P_PLL8, 4, 0, 0 }, 1121 { 109710000, P_PLL8, 1, 2, 7 }, 1122 { 128000000, P_PLL8, 3, 0, 0 }, 1123 { 153600000, P_PLL8, 1, 2, 5 }, 1124 { 200000000, P_PLL2, 4, 0, 0 }, 1125 { 228571000, P_PLL2, 1, 2, 7 }, 1126 { 266667000, P_PLL2, 1, 1, 3 }, 1127 { 320000000, P_PLL2, 1, 2, 5 }, 1128 { } 1129}; 1130 1131static struct clk_rcg ijpeg_src = { 1132 .ns_reg = 0x00a0, 1133 .md_reg = 0x009c, 1134 .mn = { 1135 .mnctr_en_bit = 5, 1136 .mnctr_reset_bit = 7, 1137 .mnctr_mode_shift = 6, 1138 .n_val_shift = 16, 1139 .m_val_shift = 8, 1140 .width = 8, 1141 }, 1142 .p = { 1143 .pre_div_shift = 12, 1144 .pre_div_width = 2, 1145 }, 1146 .s = { 1147 .src_sel_shift = 0, 1148 .parent_map = mmcc_pxo_pll8_pll2_map, 1149 }, 1150 .freq_tbl = clk_tbl_ijpeg, 1151 .clkr = { 1152 .enable_reg = 0x0098, 1153 .enable_mask = BIT(2), 1154 .hw.init = &(struct clk_init_data){ 1155 .name = "ijpeg_src", 1156 .parent_names = mmcc_pxo_pll8_pll2, 1157 .num_parents = 3, 1158 .ops = &clk_rcg_ops, 1159 }, 1160 }, 1161}; 1162 1163static struct clk_branch ijpeg_clk = { 1164 .halt_reg = 0x01c8, 1165 .halt_bit = 24, 1166 .clkr = { 1167 .enable_reg = 0x0098, 1168 .enable_mask = BIT(0), 1169 .hw.init = &(struct clk_init_data){ 1170 .name = "ijpeg_clk", 1171 .parent_names = (const char *[]){ "ijpeg_src" }, 1172 .num_parents = 1, 1173 .ops = &clk_branch_ops, 1174 .flags = CLK_SET_RATE_PARENT, 1175 }, 1176 }, 1177}; 1178 1179static struct freq_tbl clk_tbl_jpegd[] = { 1180 { 64000000, P_PLL8, 6 }, 1181 { 76800000, P_PLL8, 5 }, 1182 { 96000000, P_PLL8, 4 }, 1183 { 160000000, P_PLL2, 5 }, 1184 { 200000000, P_PLL2, 4 }, 1185 { } 1186}; 1187 1188static struct clk_rcg jpegd_src = { 1189 .ns_reg = 0x00ac, 1190 .p = { 1191 .pre_div_shift = 12, 1192 .pre_div_width = 4, 1193 }, 1194 .s = { 1195 .src_sel_shift = 0, 1196 .parent_map = mmcc_pxo_pll8_pll2_map, 1197 }, 1198 .freq_tbl = clk_tbl_jpegd, 1199 .clkr = { 1200 .enable_reg = 0x00a4, 1201 .enable_mask = BIT(2), 1202 .hw.init = &(struct clk_init_data){ 1203 .name = "jpegd_src", 1204 .parent_names = mmcc_pxo_pll8_pll2, 1205 .num_parents = 3, 1206 .ops = &clk_rcg_ops, 1207 }, 1208 }, 1209}; 1210 1211static struct clk_branch jpegd_clk = { 1212 .halt_reg = 0x01c8, 1213 .halt_bit = 19, 1214 .clkr = { 1215 .enable_reg = 0x00a4, 1216 .enable_mask = BIT(0), 1217 .hw.init = &(struct clk_init_data){ 1218 .name = "jpegd_clk", 1219 .parent_names = (const char *[]){ "jpegd_src" }, 1220 .num_parents = 1, 1221 .ops = &clk_branch_ops, 1222 .flags = CLK_SET_RATE_PARENT, 1223 }, 1224 }, 1225}; 1226 1227static struct freq_tbl clk_tbl_mdp[] = { 1228 { 9600000, P_PLL8, 1, 1, 40 }, 1229 { 13710000, P_PLL8, 1, 1, 28 }, 1230 { 27000000, P_PXO, 1, 0, 0 }, 1231 { 29540000, P_PLL8, 1, 1, 13 }, 1232 { 34910000, P_PLL8, 1, 1, 11 }, 1233 { 38400000, P_PLL8, 1, 1, 10 }, 1234 { 59080000, P_PLL8, 1, 2, 13 }, 1235 { 76800000, P_PLL8, 1, 1, 5 }, 1236 { 85330000, P_PLL8, 1, 2, 9 }, 1237 { 96000000, P_PLL8, 1, 1, 4 }, 1238 { 128000000, P_PLL8, 1, 1, 3 }, 1239 { 160000000, P_PLL2, 1, 1, 5 }, 1240 { 177780000, P_PLL2, 1, 2, 9 }, 1241 { 200000000, P_PLL2, 1, 1, 4 }, 1242 { 228571000, P_PLL2, 1, 2, 7 }, 1243 { 266667000, P_PLL2, 1, 1, 3 }, 1244 { } 1245}; 1246 1247static struct clk_dyn_rcg mdp_src = { 1248 .ns_reg[0] = 0x00d0, 1249 .ns_reg[1] = 0x00d0, 1250 .md_reg[0] = 0x00c4, 1251 .md_reg[1] = 0x00c8, 1252 .bank_reg = 0x00c0, 1253 .mn[0] = { 1254 .mnctr_en_bit = 8, 1255 .mnctr_reset_bit = 31, 1256 .mnctr_mode_shift = 9, 1257 .n_val_shift = 22, 1258 .m_val_shift = 8, 1259 .width = 8, 1260 }, 1261 .mn[1] = { 1262 .mnctr_en_bit = 5, 1263 .mnctr_reset_bit = 30, 1264 .mnctr_mode_shift = 6, 1265 .n_val_shift = 14, 1266 .m_val_shift = 8, 1267 .width = 8, 1268 }, 1269 .s[0] = { 1270 .src_sel_shift = 3, 1271 .parent_map = mmcc_pxo_pll8_pll2_map, 1272 }, 1273 .s[1] = { 1274 .src_sel_shift = 0, 1275 .parent_map = mmcc_pxo_pll8_pll2_map, 1276 }, 1277 .mux_sel_bit = 11, 1278 .freq_tbl = clk_tbl_mdp, 1279 .clkr = { 1280 .enable_reg = 0x00c0, 1281 .enable_mask = BIT(2), 1282 .hw.init = &(struct clk_init_data){ 1283 .name = "mdp_src", 1284 .parent_names = mmcc_pxo_pll8_pll2, 1285 .num_parents = 3, 1286 .ops = &clk_dyn_rcg_ops, 1287 }, 1288 }, 1289}; 1290 1291static struct clk_branch mdp_clk = { 1292 .halt_reg = 0x01d0, 1293 .halt_bit = 10, 1294 .clkr = { 1295 .enable_reg = 0x00c0, 1296 .enable_mask = BIT(0), 1297 .hw.init = &(struct clk_init_data){ 1298 .name = "mdp_clk", 1299 .parent_names = (const char *[]){ "mdp_src" }, 1300 .num_parents = 1, 1301 .ops = &clk_branch_ops, 1302 .flags = CLK_SET_RATE_PARENT, 1303 }, 1304 }, 1305}; 1306 1307static struct clk_branch mdp_lut_clk = { 1308 .halt_reg = 0x01e8, 1309 .halt_bit = 13, 1310 .clkr = { 1311 .enable_reg = 0x016c, 1312 .enable_mask = BIT(0), 1313 .hw.init = &(struct clk_init_data){ 1314 .parent_names = (const char *[]){ "mdp_src" }, 1315 .num_parents = 1, 1316 .name = "mdp_lut_clk", 1317 .ops = &clk_branch_ops, 1318 .flags = CLK_SET_RATE_PARENT, 1319 }, 1320 }, 1321}; 1322 1323static struct clk_branch mdp_vsync_clk = { 1324 .halt_reg = 0x01cc, 1325 .halt_bit = 22, 1326 .clkr = { 1327 .enable_reg = 0x0058, 1328 .enable_mask = BIT(6), 1329 .hw.init = &(struct clk_init_data){ 1330 .name = "mdp_vsync_clk", 1331 .parent_names = (const char *[]){ "pxo" }, 1332 .num_parents = 1, 1333 .ops = &clk_branch_ops 1334 }, 1335 }, 1336}; 1337 1338static struct freq_tbl clk_tbl_rot[] = { 1339 { 27000000, P_PXO, 1 }, 1340 { 29540000, P_PLL8, 13 }, 1341 { 32000000, P_PLL8, 12 }, 1342 { 38400000, P_PLL8, 10 }, 1343 { 48000000, P_PLL8, 8 }, 1344 { 54860000, P_PLL8, 7 }, 1345 { 64000000, P_PLL8, 6 }, 1346 { 76800000, P_PLL8, 5 }, 1347 { 96000000, P_PLL8, 4 }, 1348 { 100000000, P_PLL2, 8 }, 1349 { 114290000, P_PLL2, 7 }, 1350 { 133330000, P_PLL2, 6 }, 1351 { 160000000, P_PLL2, 5 }, 1352 { 200000000, P_PLL2, 4 }, 1353 { } 1354}; 1355 1356static struct clk_dyn_rcg rot_src = { 1357 .ns_reg[0] = 0x00e8, 1358 .ns_reg[1] = 0x00e8, 1359 .bank_reg = 0x00e8, 1360 .p[0] = { 1361 .pre_div_shift = 22, 1362 .pre_div_width = 4, 1363 }, 1364 .p[1] = { 1365 .pre_div_shift = 26, 1366 .pre_div_width = 4, 1367 }, 1368 .s[0] = { 1369 .src_sel_shift = 16, 1370 .parent_map = mmcc_pxo_pll8_pll2_map, 1371 }, 1372 .s[1] = { 1373 .src_sel_shift = 19, 1374 .parent_map = mmcc_pxo_pll8_pll2_map, 1375 }, 1376 .mux_sel_bit = 30, 1377 .freq_tbl = clk_tbl_rot, 1378 .clkr = { 1379 .enable_reg = 0x00e0, 1380 .enable_mask = BIT(2), 1381 .hw.init = &(struct clk_init_data){ 1382 .name = "rot_src", 1383 .parent_names = mmcc_pxo_pll8_pll2, 1384 .num_parents = 3, 1385 .ops = &clk_dyn_rcg_ops, 1386 }, 1387 }, 1388}; 1389 1390static struct clk_branch rot_clk = { 1391 .halt_reg = 0x01d0, 1392 .halt_bit = 15, 1393 .clkr = { 1394 .enable_reg = 0x00e0, 1395 .enable_mask = BIT(0), 1396 .hw.init = &(struct clk_init_data){ 1397 .name = "rot_clk", 1398 .parent_names = (const char *[]){ "rot_src" }, 1399 .num_parents = 1, 1400 .ops = &clk_branch_ops, 1401 .flags = CLK_SET_RATE_PARENT, 1402 }, 1403 }, 1404}; 1405 1406static const struct parent_map mmcc_pxo_hdmi_map[] = { 1407 { P_PXO, 0 }, 1408 { P_HDMI_PLL, 3 } 1409}; 1410 1411static const char * const mmcc_pxo_hdmi[] = { 1412 "pxo", 1413 "hdmi_pll", 1414}; 1415 1416static struct freq_tbl clk_tbl_tv[] = { 1417 { .src = P_HDMI_PLL, .pre_div = 1 }, 1418 { } 1419}; 1420 1421static struct clk_rcg tv_src = { 1422 .ns_reg = 0x00f4, 1423 .md_reg = 0x00f0, 1424 .mn = { 1425 .mnctr_en_bit = 5, 1426 .mnctr_reset_bit = 7, 1427 .mnctr_mode_shift = 6, 1428 .n_val_shift = 16, 1429 .m_val_shift = 8, 1430 .width = 8, 1431 }, 1432 .p = { 1433 .pre_div_shift = 14, 1434 .pre_div_width = 2, 1435 }, 1436 .s = { 1437 .src_sel_shift = 0, 1438 .parent_map = mmcc_pxo_hdmi_map, 1439 }, 1440 .freq_tbl = clk_tbl_tv, 1441 .clkr = { 1442 .enable_reg = 0x00ec, 1443 .enable_mask = BIT(2), 1444 .hw.init = &(struct clk_init_data){ 1445 .name = "tv_src", 1446 .parent_names = mmcc_pxo_hdmi, 1447 .num_parents = 2, 1448 .ops = &clk_rcg_bypass_ops, 1449 .flags = CLK_SET_RATE_PARENT, 1450 }, 1451 }, 1452}; 1453 1454static const char * const tv_src_name[] = { "tv_src" }; 1455 1456static struct clk_branch tv_enc_clk = { 1457 .halt_reg = 0x01d4, 1458 .halt_bit = 9, 1459 .clkr = { 1460 .enable_reg = 0x00ec, 1461 .enable_mask = BIT(8), 1462 .hw.init = &(struct clk_init_data){ 1463 .parent_names = tv_src_name, 1464 .num_parents = 1, 1465 .name = "tv_enc_clk", 1466 .ops = &clk_branch_ops, 1467 .flags = CLK_SET_RATE_PARENT, 1468 }, 1469 }, 1470}; 1471 1472static struct clk_branch tv_dac_clk = { 1473 .halt_reg = 0x01d4, 1474 .halt_bit = 10, 1475 .clkr = { 1476 .enable_reg = 0x00ec, 1477 .enable_mask = BIT(10), 1478 .hw.init = &(struct clk_init_data){ 1479 .parent_names = tv_src_name, 1480 .num_parents = 1, 1481 .name = "tv_dac_clk", 1482 .ops = &clk_branch_ops, 1483 .flags = CLK_SET_RATE_PARENT, 1484 }, 1485 }, 1486}; 1487 1488static struct clk_branch mdp_tv_clk = { 1489 .halt_reg = 0x01d4, 1490 .halt_bit = 12, 1491 .clkr = { 1492 .enable_reg = 0x00ec, 1493 .enable_mask = BIT(0), 1494 .hw.init = &(struct clk_init_data){ 1495 .parent_names = tv_src_name, 1496 .num_parents = 1, 1497 .name = "mdp_tv_clk", 1498 .ops = &clk_branch_ops, 1499 .flags = CLK_SET_RATE_PARENT, 1500 }, 1501 }, 1502}; 1503 1504static struct clk_branch hdmi_tv_clk = { 1505 .halt_reg = 0x01d4, 1506 .halt_bit = 11, 1507 .clkr = { 1508 .enable_reg = 0x00ec, 1509 .enable_mask = BIT(12), 1510 .hw.init = &(struct clk_init_data){ 1511 .parent_names = tv_src_name, 1512 .num_parents = 1, 1513 .name = "hdmi_tv_clk", 1514 .ops = &clk_branch_ops, 1515 .flags = CLK_SET_RATE_PARENT, 1516 }, 1517 }, 1518}; 1519 1520static struct clk_branch rgb_tv_clk = { 1521 .halt_reg = 0x0240, 1522 .halt_bit = 27, 1523 .clkr = { 1524 .enable_reg = 0x0124, 1525 .enable_mask = BIT(14), 1526 .hw.init = &(struct clk_init_data){ 1527 .parent_names = tv_src_name, 1528 .num_parents = 1, 1529 .name = "rgb_tv_clk", 1530 .ops = &clk_branch_ops, 1531 .flags = CLK_SET_RATE_PARENT, 1532 }, 1533 }, 1534}; 1535 1536static struct clk_branch npl_tv_clk = { 1537 .halt_reg = 0x0240, 1538 .halt_bit = 26, 1539 .clkr = { 1540 .enable_reg = 0x0124, 1541 .enable_mask = BIT(16), 1542 .hw.init = &(struct clk_init_data){ 1543 .parent_names = tv_src_name, 1544 .num_parents = 1, 1545 .name = "npl_tv_clk", 1546 .ops = &clk_branch_ops, 1547 .flags = CLK_SET_RATE_PARENT, 1548 }, 1549 }, 1550}; 1551 1552static struct clk_branch hdmi_app_clk = { 1553 .halt_reg = 0x01cc, 1554 .halt_bit = 25, 1555 .clkr = { 1556 .enable_reg = 0x005c, 1557 .enable_mask = BIT(11), 1558 .hw.init = &(struct clk_init_data){ 1559 .parent_names = (const char *[]){ "pxo" }, 1560 .num_parents = 1, 1561 .name = "hdmi_app_clk", 1562 .ops = &clk_branch_ops, 1563 }, 1564 }, 1565}; 1566 1567static struct freq_tbl clk_tbl_vcodec[] = { 1568 F_MN( 27000000, P_PXO, 1, 0), 1569 F_MN( 32000000, P_PLL8, 1, 12), 1570 F_MN( 48000000, P_PLL8, 1, 8), 1571 F_MN( 54860000, P_PLL8, 1, 7), 1572 F_MN( 96000000, P_PLL8, 1, 4), 1573 F_MN(133330000, P_PLL2, 1, 6), 1574 F_MN(200000000, P_PLL2, 1, 4), 1575 F_MN(228570000, P_PLL2, 2, 7), 1576 F_MN(266670000, P_PLL2, 1, 3), 1577 { } 1578}; 1579 1580static struct clk_dyn_rcg vcodec_src = { 1581 .ns_reg[0] = 0x0100, 1582 .ns_reg[1] = 0x0100, 1583 .md_reg[0] = 0x00fc, 1584 .md_reg[1] = 0x0128, 1585 .bank_reg = 0x00f8, 1586 .mn[0] = { 1587 .mnctr_en_bit = 5, 1588 .mnctr_reset_bit = 31, 1589 .mnctr_mode_shift = 6, 1590 .n_val_shift = 11, 1591 .m_val_shift = 8, 1592 .width = 8, 1593 }, 1594 .mn[1] = { 1595 .mnctr_en_bit = 10, 1596 .mnctr_reset_bit = 30, 1597 .mnctr_mode_shift = 11, 1598 .n_val_shift = 19, 1599 .m_val_shift = 8, 1600 .width = 8, 1601 }, 1602 .s[0] = { 1603 .src_sel_shift = 27, 1604 .parent_map = mmcc_pxo_pll8_pll2_map, 1605 }, 1606 .s[1] = { 1607 .src_sel_shift = 0, 1608 .parent_map = mmcc_pxo_pll8_pll2_map, 1609 }, 1610 .mux_sel_bit = 13, 1611 .freq_tbl = clk_tbl_vcodec, 1612 .clkr = { 1613 .enable_reg = 0x00f8, 1614 .enable_mask = BIT(2), 1615 .hw.init = &(struct clk_init_data){ 1616 .name = "vcodec_src", 1617 .parent_names = mmcc_pxo_pll8_pll2, 1618 .num_parents = 3, 1619 .ops = &clk_dyn_rcg_ops, 1620 }, 1621 }, 1622}; 1623 1624static struct clk_branch vcodec_clk = { 1625 .halt_reg = 0x01d0, 1626 .halt_bit = 29, 1627 .clkr = { 1628 .enable_reg = 0x00f8, 1629 .enable_mask = BIT(0), 1630 .hw.init = &(struct clk_init_data){ 1631 .name = "vcodec_clk", 1632 .parent_names = (const char *[]){ "vcodec_src" }, 1633 .num_parents = 1, 1634 .ops = &clk_branch_ops, 1635 .flags = CLK_SET_RATE_PARENT, 1636 }, 1637 }, 1638}; 1639 1640static struct freq_tbl clk_tbl_vpe[] = { 1641 { 27000000, P_PXO, 1 }, 1642 { 34909000, P_PLL8, 11 }, 1643 { 38400000, P_PLL8, 10 }, 1644 { 64000000, P_PLL8, 6 }, 1645 { 76800000, P_PLL8, 5 }, 1646 { 96000000, P_PLL8, 4 }, 1647 { 100000000, P_PLL2, 8 }, 1648 { 160000000, P_PLL2, 5 }, 1649 { } 1650}; 1651 1652static struct clk_rcg vpe_src = { 1653 .ns_reg = 0x0118, 1654 .p = { 1655 .pre_div_shift = 12, 1656 .pre_div_width = 4, 1657 }, 1658 .s = { 1659 .src_sel_shift = 0, 1660 .parent_map = mmcc_pxo_pll8_pll2_map, 1661 }, 1662 .freq_tbl = clk_tbl_vpe, 1663 .clkr = { 1664 .enable_reg = 0x0110, 1665 .enable_mask = BIT(2), 1666 .hw.init = &(struct clk_init_data){ 1667 .name = "vpe_src", 1668 .parent_names = mmcc_pxo_pll8_pll2, 1669 .num_parents = 3, 1670 .ops = &clk_rcg_ops, 1671 }, 1672 }, 1673}; 1674 1675static struct clk_branch vpe_clk = { 1676 .halt_reg = 0x01c8, 1677 .halt_bit = 28, 1678 .clkr = { 1679 .enable_reg = 0x0110, 1680 .enable_mask = BIT(0), 1681 .hw.init = &(struct clk_init_data){ 1682 .name = "vpe_clk", 1683 .parent_names = (const char *[]){ "vpe_src" }, 1684 .num_parents = 1, 1685 .ops = &clk_branch_ops, 1686 .flags = CLK_SET_RATE_PARENT, 1687 }, 1688 }, 1689}; 1690 1691static struct freq_tbl clk_tbl_vfe[] = { 1692 { 13960000, P_PLL8, 1, 2, 55 }, 1693 { 27000000, P_PXO, 1, 0, 0 }, 1694 { 36570000, P_PLL8, 1, 2, 21 }, 1695 { 38400000, P_PLL8, 2, 1, 5 }, 1696 { 45180000, P_PLL8, 1, 2, 17 }, 1697 { 48000000, P_PLL8, 2, 1, 4 }, 1698 { 54860000, P_PLL8, 1, 1, 7 }, 1699 { 64000000, P_PLL8, 2, 1, 3 }, 1700 { 76800000, P_PLL8, 1, 1, 5 }, 1701 { 96000000, P_PLL8, 2, 1, 2 }, 1702 { 109710000, P_PLL8, 1, 2, 7 }, 1703 { 128000000, P_PLL8, 1, 1, 3 }, 1704 { 153600000, P_PLL8, 1, 2, 5 }, 1705 { 200000000, P_PLL2, 2, 1, 2 }, 1706 { 228570000, P_PLL2, 1, 2, 7 }, 1707 { 266667000, P_PLL2, 1, 1, 3 }, 1708 { 320000000, P_PLL2, 1, 2, 5 }, 1709 { } 1710}; 1711 1712static struct clk_rcg vfe_src = { 1713 .ns_reg = 0x0108, 1714 .mn = { 1715 .mnctr_en_bit = 5, 1716 .mnctr_reset_bit = 7, 1717 .mnctr_mode_shift = 6, 1718 .n_val_shift = 16, 1719 .m_val_shift = 8, 1720 .width = 8, 1721 }, 1722 .p = { 1723 .pre_div_shift = 10, 1724 .pre_div_width = 1, 1725 }, 1726 .s = { 1727 .src_sel_shift = 0, 1728 .parent_map = mmcc_pxo_pll8_pll2_map, 1729 }, 1730 .freq_tbl = clk_tbl_vfe, 1731 .clkr = { 1732 .enable_reg = 0x0104, 1733 .enable_mask = BIT(2), 1734 .hw.init = &(struct clk_init_data){ 1735 .name = "vfe_src", 1736 .parent_names = mmcc_pxo_pll8_pll2, 1737 .num_parents = 3, 1738 .ops = &clk_rcg_ops, 1739 }, 1740 }, 1741}; 1742 1743static struct clk_branch vfe_clk = { 1744 .halt_reg = 0x01cc, 1745 .halt_bit = 6, 1746 .clkr = { 1747 .enable_reg = 0x0104, 1748 .enable_mask = BIT(0), 1749 .hw.init = &(struct clk_init_data){ 1750 .name = "vfe_clk", 1751 .parent_names = (const char *[]){ "vfe_src" }, 1752 .num_parents = 1, 1753 .ops = &clk_branch_ops, 1754 .flags = CLK_SET_RATE_PARENT, 1755 }, 1756 }, 1757}; 1758 1759static struct clk_branch vfe_csi_clk = { 1760 .halt_reg = 0x01cc, 1761 .halt_bit = 8, 1762 .clkr = { 1763 .enable_reg = 0x0104, 1764 .enable_mask = BIT(12), 1765 .hw.init = &(struct clk_init_data){ 1766 .parent_names = (const char *[]){ "vfe_src" }, 1767 .num_parents = 1, 1768 .name = "vfe_csi_clk", 1769 .ops = &clk_branch_ops, 1770 .flags = CLK_SET_RATE_PARENT, 1771 }, 1772 }, 1773}; 1774 1775static struct clk_branch gmem_axi_clk = { 1776 .halt_reg = 0x01d8, 1777 .halt_bit = 6, 1778 .clkr = { 1779 .enable_reg = 0x0018, 1780 .enable_mask = BIT(24), 1781 .hw.init = &(struct clk_init_data){ 1782 .name = "gmem_axi_clk", 1783 .ops = &clk_branch_ops, 1784 }, 1785 }, 1786}; 1787 1788static struct clk_branch ijpeg_axi_clk = { 1789 .hwcg_reg = 0x0018, 1790 .hwcg_bit = 11, 1791 .halt_reg = 0x01d8, 1792 .halt_bit = 4, 1793 .clkr = { 1794 .enable_reg = 0x0018, 1795 .enable_mask = BIT(21), 1796 .hw.init = &(struct clk_init_data){ 1797 .name = "ijpeg_axi_clk", 1798 .ops = &clk_branch_ops, 1799 }, 1800 }, 1801}; 1802 1803static struct clk_branch mmss_imem_axi_clk = { 1804 .hwcg_reg = 0x0018, 1805 .hwcg_bit = 15, 1806 .halt_reg = 0x01d8, 1807 .halt_bit = 7, 1808 .clkr = { 1809 .enable_reg = 0x0018, 1810 .enable_mask = BIT(22), 1811 .hw.init = &(struct clk_init_data){ 1812 .name = "mmss_imem_axi_clk", 1813 .ops = &clk_branch_ops, 1814 }, 1815 }, 1816}; 1817 1818static struct clk_branch jpegd_axi_clk = { 1819 .halt_reg = 0x01d8, 1820 .halt_bit = 5, 1821 .clkr = { 1822 .enable_reg = 0x0018, 1823 .enable_mask = BIT(25), 1824 .hw.init = &(struct clk_init_data){ 1825 .name = "jpegd_axi_clk", 1826 .ops = &clk_branch_ops, 1827 }, 1828 }, 1829}; 1830 1831static struct clk_branch vcodec_axi_b_clk = { 1832 .hwcg_reg = 0x0114, 1833 .hwcg_bit = 22, 1834 .halt_reg = 0x01e8, 1835 .halt_bit = 25, 1836 .clkr = { 1837 .enable_reg = 0x0114, 1838 .enable_mask = BIT(23), 1839 .hw.init = &(struct clk_init_data){ 1840 .name = "vcodec_axi_b_clk", 1841 .ops = &clk_branch_ops, 1842 }, 1843 }, 1844}; 1845 1846static struct clk_branch vcodec_axi_a_clk = { 1847 .hwcg_reg = 0x0114, 1848 .hwcg_bit = 24, 1849 .halt_reg = 0x01e8, 1850 .halt_bit = 26, 1851 .clkr = { 1852 .enable_reg = 0x0114, 1853 .enable_mask = BIT(25), 1854 .hw.init = &(struct clk_init_data){ 1855 .name = "vcodec_axi_a_clk", 1856 .ops = &clk_branch_ops, 1857 }, 1858 }, 1859}; 1860 1861static struct clk_branch vcodec_axi_clk = { 1862 .hwcg_reg = 0x0018, 1863 .hwcg_bit = 13, 1864 .halt_reg = 0x01d8, 1865 .halt_bit = 3, 1866 .clkr = { 1867 .enable_reg = 0x0018, 1868 .enable_mask = BIT(19), 1869 .hw.init = &(struct clk_init_data){ 1870 .name = "vcodec_axi_clk", 1871 .ops = &clk_branch_ops, 1872 }, 1873 }, 1874}; 1875 1876static struct clk_branch vfe_axi_clk = { 1877 .halt_reg = 0x01d8, 1878 .halt_bit = 0, 1879 .clkr = { 1880 .enable_reg = 0x0018, 1881 .enable_mask = BIT(18), 1882 .hw.init = &(struct clk_init_data){ 1883 .name = "vfe_axi_clk", 1884 .ops = &clk_branch_ops, 1885 }, 1886 }, 1887}; 1888 1889static struct clk_branch mdp_axi_clk = { 1890 .hwcg_reg = 0x0018, 1891 .hwcg_bit = 16, 1892 .halt_reg = 0x01d8, 1893 .halt_bit = 8, 1894 .clkr = { 1895 .enable_reg = 0x0018, 1896 .enable_mask = BIT(23), 1897 .hw.init = &(struct clk_init_data){ 1898 .name = "mdp_axi_clk", 1899 .ops = &clk_branch_ops, 1900 }, 1901 }, 1902}; 1903 1904static struct clk_branch rot_axi_clk = { 1905 .hwcg_reg = 0x0020, 1906 .hwcg_bit = 25, 1907 .halt_reg = 0x01d8, 1908 .halt_bit = 2, 1909 .clkr = { 1910 .enable_reg = 0x0020, 1911 .enable_mask = BIT(24), 1912 .hw.init = &(struct clk_init_data){ 1913 .name = "rot_axi_clk", 1914 .ops = &clk_branch_ops, 1915 }, 1916 }, 1917}; 1918 1919static struct clk_branch vcap_axi_clk = { 1920 .halt_reg = 0x0240, 1921 .halt_bit = 20, 1922 .hwcg_reg = 0x0244, 1923 .hwcg_bit = 11, 1924 .clkr = { 1925 .enable_reg = 0x0244, 1926 .enable_mask = BIT(12), 1927 .hw.init = &(struct clk_init_data){ 1928 .name = "vcap_axi_clk", 1929 .ops = &clk_branch_ops, 1930 }, 1931 }, 1932}; 1933 1934static struct clk_branch vpe_axi_clk = { 1935 .hwcg_reg = 0x0020, 1936 .hwcg_bit = 27, 1937 .halt_reg = 0x01d8, 1938 .halt_bit = 1, 1939 .clkr = { 1940 .enable_reg = 0x0020, 1941 .enable_mask = BIT(26), 1942 .hw.init = &(struct clk_init_data){ 1943 .name = "vpe_axi_clk", 1944 .ops = &clk_branch_ops, 1945 }, 1946 }, 1947}; 1948 1949static struct clk_branch gfx3d_axi_clk = { 1950 .hwcg_reg = 0x0244, 1951 .hwcg_bit = 24, 1952 .halt_reg = 0x0240, 1953 .halt_bit = 30, 1954 .clkr = { 1955 .enable_reg = 0x0244, 1956 .enable_mask = BIT(25), 1957 .hw.init = &(struct clk_init_data){ 1958 .name = "gfx3d_axi_clk", 1959 .ops = &clk_branch_ops, 1960 }, 1961 }, 1962}; 1963 1964static struct clk_branch amp_ahb_clk = { 1965 .halt_reg = 0x01dc, 1966 .halt_bit = 18, 1967 .clkr = { 1968 .enable_reg = 0x0008, 1969 .enable_mask = BIT(24), 1970 .hw.init = &(struct clk_init_data){ 1971 .name = "amp_ahb_clk", 1972 .ops = &clk_branch_ops, 1973 }, 1974 }, 1975}; 1976 1977static struct clk_branch csi_ahb_clk = { 1978 .halt_reg = 0x01dc, 1979 .halt_bit = 16, 1980 .clkr = { 1981 .enable_reg = 0x0008, 1982 .enable_mask = BIT(7), 1983 .hw.init = &(struct clk_init_data){ 1984 .name = "csi_ahb_clk", 1985 .ops = &clk_branch_ops, 1986 }, 1987 }, 1988}; 1989 1990static struct clk_branch dsi_m_ahb_clk = { 1991 .halt_reg = 0x01dc, 1992 .halt_bit = 19, 1993 .clkr = { 1994 .enable_reg = 0x0008, 1995 .enable_mask = BIT(9), 1996 .hw.init = &(struct clk_init_data){ 1997 .name = "dsi_m_ahb_clk", 1998 .ops = &clk_branch_ops, 1999 }, 2000 }, 2001}; 2002 2003static struct clk_branch dsi_s_ahb_clk = { 2004 .hwcg_reg = 0x0038, 2005 .hwcg_bit = 20, 2006 .halt_reg = 0x01dc, 2007 .halt_bit = 21, 2008 .clkr = { 2009 .enable_reg = 0x0008, 2010 .enable_mask = BIT(18), 2011 .hw.init = &(struct clk_init_data){ 2012 .name = "dsi_s_ahb_clk", 2013 .ops = &clk_branch_ops, 2014 }, 2015 }, 2016}; 2017 2018static struct clk_branch dsi2_m_ahb_clk = { 2019 .halt_reg = 0x01d8, 2020 .halt_bit = 18, 2021 .clkr = { 2022 .enable_reg = 0x0008, 2023 .enable_mask = BIT(17), 2024 .hw.init = &(struct clk_init_data){ 2025 .name = "dsi2_m_ahb_clk", 2026 .ops = &clk_branch_ops, 2027 }, 2028 }, 2029}; 2030 2031static struct clk_branch dsi2_s_ahb_clk = { 2032 .hwcg_reg = 0x0038, 2033 .hwcg_bit = 15, 2034 .halt_reg = 0x01dc, 2035 .halt_bit = 20, 2036 .clkr = { 2037 .enable_reg = 0x0008, 2038 .enable_mask = BIT(22), 2039 .hw.init = &(struct clk_init_data){ 2040 .name = "dsi2_s_ahb_clk", 2041 .ops = &clk_branch_ops, 2042 }, 2043 }, 2044}; 2045 2046static struct clk_rcg dsi1_src = { 2047 .ns_reg = 0x0054, 2048 .md_reg = 0x0050, 2049 .mn = { 2050 .mnctr_en_bit = 5, 2051 .mnctr_reset_bit = 7, 2052 .mnctr_mode_shift = 6, 2053 .n_val_shift = 24, 2054 .m_val_shift = 8, 2055 .width = 8, 2056 }, 2057 .p = { 2058 .pre_div_shift = 14, 2059 .pre_div_width = 2, 2060 }, 2061 .s = { 2062 .src_sel_shift = 0, 2063 .parent_map = mmcc_pxo_dsi2_dsi1_map, 2064 }, 2065 .clkr = { 2066 .enable_reg = 0x004c, 2067 .enable_mask = BIT(2), 2068 .hw.init = &(struct clk_init_data){ 2069 .name = "dsi1_src", 2070 .parent_names = mmcc_pxo_dsi2_dsi1, 2071 .num_parents = 3, 2072 .ops = &clk_rcg_bypass2_ops, 2073 .flags = CLK_SET_RATE_PARENT, 2074 }, 2075 }, 2076}; 2077 2078static struct clk_branch dsi1_clk = { 2079 .halt_reg = 0x01d0, 2080 .halt_bit = 2, 2081 .clkr = { 2082 .enable_reg = 0x004c, 2083 .enable_mask = BIT(0), 2084 .hw.init = &(struct clk_init_data){ 2085 .name = "dsi1_clk", 2086 .parent_names = (const char *[]){ "dsi1_src" }, 2087 .num_parents = 1, 2088 .ops = &clk_branch_ops, 2089 .flags = CLK_SET_RATE_PARENT, 2090 }, 2091 }, 2092}; 2093 2094static struct clk_rcg dsi2_src = { 2095 .ns_reg = 0x012c, 2096 .md_reg = 0x00a8, 2097 .mn = { 2098 .mnctr_en_bit = 5, 2099 .mnctr_reset_bit = 7, 2100 .mnctr_mode_shift = 6, 2101 .n_val_shift = 24, 2102 .m_val_shift = 8, 2103 .width = 8, 2104 }, 2105 .p = { 2106 .pre_div_shift = 14, 2107 .pre_div_width = 2, 2108 }, 2109 .s = { 2110 .src_sel_shift = 0, 2111 .parent_map = mmcc_pxo_dsi2_dsi1_map, 2112 }, 2113 .clkr = { 2114 .enable_reg = 0x003c, 2115 .enable_mask = BIT(2), 2116 .hw.init = &(struct clk_init_data){ 2117 .name = "dsi2_src", 2118 .parent_names = mmcc_pxo_dsi2_dsi1, 2119 .num_parents = 3, 2120 .ops = &clk_rcg_bypass2_ops, 2121 .flags = CLK_SET_RATE_PARENT, 2122 }, 2123 }, 2124}; 2125 2126static struct clk_branch dsi2_clk = { 2127 .halt_reg = 0x01d0, 2128 .halt_bit = 20, 2129 .clkr = { 2130 .enable_reg = 0x003c, 2131 .enable_mask = BIT(0), 2132 .hw.init = &(struct clk_init_data){ 2133 .name = "dsi2_clk", 2134 .parent_names = (const char *[]){ "dsi2_src" }, 2135 .num_parents = 1, 2136 .ops = &clk_branch_ops, 2137 .flags = CLK_SET_RATE_PARENT, 2138 }, 2139 }, 2140}; 2141 2142static struct clk_rcg dsi1_byte_src = { 2143 .ns_reg = 0x00b0, 2144 .p = { 2145 .pre_div_shift = 12, 2146 .pre_div_width = 4, 2147 }, 2148 .s = { 2149 .src_sel_shift = 0, 2150 .parent_map = mmcc_pxo_dsi1_dsi2_byte_map, 2151 }, 2152 .clkr = { 2153 .enable_reg = 0x0090, 2154 .enable_mask = BIT(2), 2155 .hw.init = &(struct clk_init_data){ 2156 .name = "dsi1_byte_src", 2157 .parent_names = mmcc_pxo_dsi1_dsi2_byte, 2158 .num_parents = 3, 2159 .ops = &clk_rcg_bypass2_ops, 2160 .flags = CLK_SET_RATE_PARENT, 2161 }, 2162 }, 2163}; 2164 2165static struct clk_branch dsi1_byte_clk = { 2166 .halt_reg = 0x01cc, 2167 .halt_bit = 21, 2168 .clkr = { 2169 .enable_reg = 0x0090, 2170 .enable_mask = BIT(0), 2171 .hw.init = &(struct clk_init_data){ 2172 .name = "dsi1_byte_clk", 2173 .parent_names = (const char *[]){ "dsi1_byte_src" }, 2174 .num_parents = 1, 2175 .ops = &clk_branch_ops, 2176 .flags = CLK_SET_RATE_PARENT, 2177 }, 2178 }, 2179}; 2180 2181static struct clk_rcg dsi2_byte_src = { 2182 .ns_reg = 0x012c, 2183 .p = { 2184 .pre_div_shift = 12, 2185 .pre_div_width = 4, 2186 }, 2187 .s = { 2188 .src_sel_shift = 0, 2189 .parent_map = mmcc_pxo_dsi1_dsi2_byte_map, 2190 }, 2191 .clkr = { 2192 .enable_reg = 0x0130, 2193 .enable_mask = BIT(2), 2194 .hw.init = &(struct clk_init_data){ 2195 .name = "dsi2_byte_src", 2196 .parent_names = mmcc_pxo_dsi1_dsi2_byte, 2197 .num_parents = 3, 2198 .ops = &clk_rcg_bypass2_ops, 2199 .flags = CLK_SET_RATE_PARENT, 2200 }, 2201 }, 2202}; 2203 2204static struct clk_branch dsi2_byte_clk = { 2205 .halt_reg = 0x01cc, 2206 .halt_bit = 20, 2207 .clkr = { 2208 .enable_reg = 0x00b4, 2209 .enable_mask = BIT(0), 2210 .hw.init = &(struct clk_init_data){ 2211 .name = "dsi2_byte_clk", 2212 .parent_names = (const char *[]){ "dsi2_byte_src" }, 2213 .num_parents = 1, 2214 .ops = &clk_branch_ops, 2215 .flags = CLK_SET_RATE_PARENT, 2216 }, 2217 }, 2218}; 2219 2220static struct clk_rcg dsi1_esc_src = { 2221 .ns_reg = 0x0011c, 2222 .p = { 2223 .pre_div_shift = 12, 2224 .pre_div_width = 4, 2225 }, 2226 .s = { 2227 .src_sel_shift = 0, 2228 .parent_map = mmcc_pxo_dsi1_dsi2_byte_map, 2229 }, 2230 .clkr = { 2231 .enable_reg = 0x00cc, 2232 .enable_mask = BIT(2), 2233 .hw.init = &(struct clk_init_data){ 2234 .name = "dsi1_esc_src", 2235 .parent_names = mmcc_pxo_dsi1_dsi2_byte, 2236 .num_parents = 3, 2237 .ops = &clk_rcg_esc_ops, 2238 }, 2239 }, 2240}; 2241 2242static struct clk_branch dsi1_esc_clk = { 2243 .halt_reg = 0x01e8, 2244 .halt_bit = 1, 2245 .clkr = { 2246 .enable_reg = 0x00cc, 2247 .enable_mask = BIT(0), 2248 .hw.init = &(struct clk_init_data){ 2249 .name = "dsi1_esc_clk", 2250 .parent_names = (const char *[]){ "dsi1_esc_src" }, 2251 .num_parents = 1, 2252 .ops = &clk_branch_ops, 2253 .flags = CLK_SET_RATE_PARENT, 2254 }, 2255 }, 2256}; 2257 2258static struct clk_rcg dsi2_esc_src = { 2259 .ns_reg = 0x0150, 2260 .p = { 2261 .pre_div_shift = 12, 2262 .pre_div_width = 4, 2263 }, 2264 .s = { 2265 .src_sel_shift = 0, 2266 .parent_map = mmcc_pxo_dsi1_dsi2_byte_map, 2267 }, 2268 .clkr = { 2269 .enable_reg = 0x013c, 2270 .enable_mask = BIT(2), 2271 .hw.init = &(struct clk_init_data){ 2272 .name = "dsi2_esc_src", 2273 .parent_names = mmcc_pxo_dsi1_dsi2_byte, 2274 .num_parents = 3, 2275 .ops = &clk_rcg_esc_ops, 2276 }, 2277 }, 2278}; 2279 2280static struct clk_branch dsi2_esc_clk = { 2281 .halt_reg = 0x01e8, 2282 .halt_bit = 3, 2283 .clkr = { 2284 .enable_reg = 0x013c, 2285 .enable_mask = BIT(0), 2286 .hw.init = &(struct clk_init_data){ 2287 .name = "dsi2_esc_clk", 2288 .parent_names = (const char *[]){ "dsi2_esc_src" }, 2289 .num_parents = 1, 2290 .ops = &clk_branch_ops, 2291 .flags = CLK_SET_RATE_PARENT, 2292 }, 2293 }, 2294}; 2295 2296static struct clk_rcg dsi1_pixel_src = { 2297 .ns_reg = 0x0138, 2298 .md_reg = 0x0134, 2299 .mn = { 2300 .mnctr_en_bit = 5, 2301 .mnctr_reset_bit = 7, 2302 .mnctr_mode_shift = 6, 2303 .n_val_shift = 16, 2304 .m_val_shift = 8, 2305 .width = 8, 2306 }, 2307 .p = { 2308 .pre_div_shift = 12, 2309 .pre_div_width = 4, 2310 }, 2311 .s = { 2312 .src_sel_shift = 0, 2313 .parent_map = mmcc_pxo_dsi2_dsi1_map, 2314 }, 2315 .clkr = { 2316 .enable_reg = 0x0130, 2317 .enable_mask = BIT(2), 2318 .hw.init = &(struct clk_init_data){ 2319 .name = "dsi1_pixel_src", 2320 .parent_names = mmcc_pxo_dsi2_dsi1, 2321 .num_parents = 3, 2322 .ops = &clk_rcg_pixel_ops, 2323 }, 2324 }, 2325}; 2326 2327static struct clk_branch dsi1_pixel_clk = { 2328 .halt_reg = 0x01d0, 2329 .halt_bit = 6, 2330 .clkr = { 2331 .enable_reg = 0x0130, 2332 .enable_mask = BIT(0), 2333 .hw.init = &(struct clk_init_data){ 2334 .name = "mdp_pclk1_clk", 2335 .parent_names = (const char *[]){ "dsi1_pixel_src" }, 2336 .num_parents = 1, 2337 .ops = &clk_branch_ops, 2338 .flags = CLK_SET_RATE_PARENT, 2339 }, 2340 }, 2341}; 2342 2343static struct clk_rcg dsi2_pixel_src = { 2344 .ns_reg = 0x00e4, 2345 .md_reg = 0x00b8, 2346 .mn = { 2347 .mnctr_en_bit = 5, 2348 .mnctr_reset_bit = 7, 2349 .mnctr_mode_shift = 6, 2350 .n_val_shift = 16, 2351 .m_val_shift = 8, 2352 .width = 8, 2353 }, 2354 .p = { 2355 .pre_div_shift = 12, 2356 .pre_div_width = 4, 2357 }, 2358 .s = { 2359 .src_sel_shift = 0, 2360 .parent_map = mmcc_pxo_dsi2_dsi1_map, 2361 }, 2362 .clkr = { 2363 .enable_reg = 0x0094, 2364 .enable_mask = BIT(2), 2365 .hw.init = &(struct clk_init_data){ 2366 .name = "dsi2_pixel_src", 2367 .parent_names = mmcc_pxo_dsi2_dsi1, 2368 .num_parents = 3, 2369 .ops = &clk_rcg_pixel_ops, 2370 }, 2371 }, 2372}; 2373 2374static struct clk_branch dsi2_pixel_clk = { 2375 .halt_reg = 0x01d0, 2376 .halt_bit = 19, 2377 .clkr = { 2378 .enable_reg = 0x0094, 2379 .enable_mask = BIT(0), 2380 .hw.init = &(struct clk_init_data){ 2381 .name = "mdp_pclk2_clk", 2382 .parent_names = (const char *[]){ "dsi2_pixel_src" }, 2383 .num_parents = 1, 2384 .ops = &clk_branch_ops, 2385 .flags = CLK_SET_RATE_PARENT, 2386 }, 2387 }, 2388}; 2389 2390static struct clk_branch gfx2d0_ahb_clk = { 2391 .hwcg_reg = 0x0038, 2392 .hwcg_bit = 28, 2393 .halt_reg = 0x01dc, 2394 .halt_bit = 2, 2395 .clkr = { 2396 .enable_reg = 0x0008, 2397 .enable_mask = BIT(19), 2398 .hw.init = &(struct clk_init_data){ 2399 .name = "gfx2d0_ahb_clk", 2400 .ops = &clk_branch_ops, 2401 }, 2402 }, 2403}; 2404 2405static struct clk_branch gfx2d1_ahb_clk = { 2406 .hwcg_reg = 0x0038, 2407 .hwcg_bit = 29, 2408 .halt_reg = 0x01dc, 2409 .halt_bit = 3, 2410 .clkr = { 2411 .enable_reg = 0x0008, 2412 .enable_mask = BIT(2), 2413 .hw.init = &(struct clk_init_data){ 2414 .name = "gfx2d1_ahb_clk", 2415 .ops = &clk_branch_ops, 2416 }, 2417 }, 2418}; 2419 2420static struct clk_branch gfx3d_ahb_clk = { 2421 .hwcg_reg = 0x0038, 2422 .hwcg_bit = 27, 2423 .halt_reg = 0x01dc, 2424 .halt_bit = 4, 2425 .clkr = { 2426 .enable_reg = 0x0008, 2427 .enable_mask = BIT(3), 2428 .hw.init = &(struct clk_init_data){ 2429 .name = "gfx3d_ahb_clk", 2430 .ops = &clk_branch_ops, 2431 }, 2432 }, 2433}; 2434 2435static struct clk_branch hdmi_m_ahb_clk = { 2436 .hwcg_reg = 0x0038, 2437 .hwcg_bit = 21, 2438 .halt_reg = 0x01dc, 2439 .halt_bit = 5, 2440 .clkr = { 2441 .enable_reg = 0x0008, 2442 .enable_mask = BIT(14), 2443 .hw.init = &(struct clk_init_data){ 2444 .name = "hdmi_m_ahb_clk", 2445 .ops = &clk_branch_ops, 2446 }, 2447 }, 2448}; 2449 2450static struct clk_branch hdmi_s_ahb_clk = { 2451 .hwcg_reg = 0x0038, 2452 .hwcg_bit = 22, 2453 .halt_reg = 0x01dc, 2454 .halt_bit = 6, 2455 .clkr = { 2456 .enable_reg = 0x0008, 2457 .enable_mask = BIT(4), 2458 .hw.init = &(struct clk_init_data){ 2459 .name = "hdmi_s_ahb_clk", 2460 .ops = &clk_branch_ops, 2461 }, 2462 }, 2463}; 2464 2465static struct clk_branch ijpeg_ahb_clk = { 2466 .halt_reg = 0x01dc, 2467 .halt_bit = 9, 2468 .clkr = { 2469 .enable_reg = 0x0008, 2470 .enable_mask = BIT(5), 2471 .hw.init = &(struct clk_init_data){ 2472 .name = "ijpeg_ahb_clk", 2473 .ops = &clk_branch_ops, 2474 }, 2475 }, 2476}; 2477 2478static struct clk_branch mmss_imem_ahb_clk = { 2479 .hwcg_reg = 0x0038, 2480 .hwcg_bit = 12, 2481 .halt_reg = 0x01dc, 2482 .halt_bit = 10, 2483 .clkr = { 2484 .enable_reg = 0x0008, 2485 .enable_mask = BIT(6), 2486 .hw.init = &(struct clk_init_data){ 2487 .name = "mmss_imem_ahb_clk", 2488 .ops = &clk_branch_ops, 2489 }, 2490 }, 2491}; 2492 2493static struct clk_branch jpegd_ahb_clk = { 2494 .halt_reg = 0x01dc, 2495 .halt_bit = 7, 2496 .clkr = { 2497 .enable_reg = 0x0008, 2498 .enable_mask = BIT(21), 2499 .hw.init = &(struct clk_init_data){ 2500 .name = "jpegd_ahb_clk", 2501 .ops = &clk_branch_ops, 2502 }, 2503 }, 2504}; 2505 2506static struct clk_branch mdp_ahb_clk = { 2507 .halt_reg = 0x01dc, 2508 .halt_bit = 11, 2509 .clkr = { 2510 .enable_reg = 0x0008, 2511 .enable_mask = BIT(10), 2512 .hw.init = &(struct clk_init_data){ 2513 .name = "mdp_ahb_clk", 2514 .ops = &clk_branch_ops, 2515 }, 2516 }, 2517}; 2518 2519static struct clk_branch rot_ahb_clk = { 2520 .halt_reg = 0x01dc, 2521 .halt_bit = 13, 2522 .clkr = { 2523 .enable_reg = 0x0008, 2524 .enable_mask = BIT(12), 2525 .hw.init = &(struct clk_init_data){ 2526 .name = "rot_ahb_clk", 2527 .ops = &clk_branch_ops, 2528 }, 2529 }, 2530}; 2531 2532static struct clk_branch smmu_ahb_clk = { 2533 .hwcg_reg = 0x0008, 2534 .hwcg_bit = 26, 2535 .halt_reg = 0x01dc, 2536 .halt_bit = 22, 2537 .clkr = { 2538 .enable_reg = 0x0008, 2539 .enable_mask = BIT(15), 2540 .hw.init = &(struct clk_init_data){ 2541 .name = "smmu_ahb_clk", 2542 .ops = &clk_branch_ops, 2543 }, 2544 }, 2545}; 2546 2547static struct clk_branch tv_enc_ahb_clk = { 2548 .halt_reg = 0x01dc, 2549 .halt_bit = 23, 2550 .clkr = { 2551 .enable_reg = 0x0008, 2552 .enable_mask = BIT(25), 2553 .hw.init = &(struct clk_init_data){ 2554 .name = "tv_enc_ahb_clk", 2555 .ops = &clk_branch_ops, 2556 }, 2557 }, 2558}; 2559 2560static struct clk_branch vcap_ahb_clk = { 2561 .halt_reg = 0x0240, 2562 .halt_bit = 23, 2563 .clkr = { 2564 .enable_reg = 0x0248, 2565 .enable_mask = BIT(1), 2566 .hw.init = &(struct clk_init_data){ 2567 .name = "vcap_ahb_clk", 2568 .ops = &clk_branch_ops, 2569 }, 2570 }, 2571}; 2572 2573static struct clk_branch vcodec_ahb_clk = { 2574 .hwcg_reg = 0x0038, 2575 .hwcg_bit = 26, 2576 .halt_reg = 0x01dc, 2577 .halt_bit = 12, 2578 .clkr = { 2579 .enable_reg = 0x0008, 2580 .enable_mask = BIT(11), 2581 .hw.init = &(struct clk_init_data){ 2582 .name = "vcodec_ahb_clk", 2583 .ops = &clk_branch_ops, 2584 }, 2585 }, 2586}; 2587 2588static struct clk_branch vfe_ahb_clk = { 2589 .halt_reg = 0x01dc, 2590 .halt_bit = 14, 2591 .clkr = { 2592 .enable_reg = 0x0008, 2593 .enable_mask = BIT(13), 2594 .hw.init = &(struct clk_init_data){ 2595 .name = "vfe_ahb_clk", 2596 .ops = &clk_branch_ops, 2597 }, 2598 }, 2599}; 2600 2601static struct clk_branch vpe_ahb_clk = { 2602 .halt_reg = 0x01dc, 2603 .halt_bit = 15, 2604 .clkr = { 2605 .enable_reg = 0x0008, 2606 .enable_mask = BIT(16), 2607 .hw.init = &(struct clk_init_data){ 2608 .name = "vpe_ahb_clk", 2609 .ops = &clk_branch_ops, 2610 }, 2611 }, 2612}; 2613 2614static struct clk_regmap *mmcc_msm8960_clks[] = { 2615 [TV_ENC_AHB_CLK] = &tv_enc_ahb_clk.clkr, 2616 [AMP_AHB_CLK] = &_ahb_clk.clkr, 2617 [DSI2_S_AHB_CLK] = &dsi2_s_ahb_clk.clkr, 2618 [JPEGD_AHB_CLK] = &jpegd_ahb_clk.clkr, 2619 [GFX2D0_AHB_CLK] = &gfx2d0_ahb_clk.clkr, 2620 [DSI_S_AHB_CLK] = &dsi_s_ahb_clk.clkr, 2621 [DSI2_M_AHB_CLK] = &dsi2_m_ahb_clk.clkr, 2622 [VPE_AHB_CLK] = &vpe_ahb_clk.clkr, 2623 [SMMU_AHB_CLK] = &smmu_ahb_clk.clkr, 2624 [HDMI_M_AHB_CLK] = &hdmi_m_ahb_clk.clkr, 2625 [VFE_AHB_CLK] = &vfe_ahb_clk.clkr, 2626 [ROT_AHB_CLK] = &rot_ahb_clk.clkr, 2627 [VCODEC_AHB_CLK] = &vcodec_ahb_clk.clkr, 2628 [MDP_AHB_CLK] = &mdp_ahb_clk.clkr, 2629 [DSI_M_AHB_CLK] = &dsi_m_ahb_clk.clkr, 2630 [CSI_AHB_CLK] = &csi_ahb_clk.clkr, 2631 [MMSS_IMEM_AHB_CLK] = &mmss_imem_ahb_clk.clkr, 2632 [IJPEG_AHB_CLK] = &ijpeg_ahb_clk.clkr, 2633 [HDMI_S_AHB_CLK] = &hdmi_s_ahb_clk.clkr, 2634 [GFX3D_AHB_CLK] = &gfx3d_ahb_clk.clkr, 2635 [GFX2D1_AHB_CLK] = &gfx2d1_ahb_clk.clkr, 2636 [JPEGD_AXI_CLK] = &jpegd_axi_clk.clkr, 2637 [GMEM_AXI_CLK] = &gmem_axi_clk.clkr, 2638 [MDP_AXI_CLK] = &mdp_axi_clk.clkr, 2639 [MMSS_IMEM_AXI_CLK] = &mmss_imem_axi_clk.clkr, 2640 [IJPEG_AXI_CLK] = &ijpeg_axi_clk.clkr, 2641 [GFX3D_AXI_CLK] = &gfx3d_axi_clk.clkr, 2642 [VCODEC_AXI_CLK] = &vcodec_axi_clk.clkr, 2643 [VFE_AXI_CLK] = &vfe_axi_clk.clkr, 2644 [VPE_AXI_CLK] = &vpe_axi_clk.clkr, 2645 [ROT_AXI_CLK] = &rot_axi_clk.clkr, 2646 [VCODEC_AXI_A_CLK] = &vcodec_axi_a_clk.clkr, 2647 [VCODEC_AXI_B_CLK] = &vcodec_axi_b_clk.clkr, 2648 [CSI0_SRC] = &csi0_src.clkr, 2649 [CSI0_CLK] = &csi0_clk.clkr, 2650 [CSI0_PHY_CLK] = &csi0_phy_clk.clkr, 2651 [CSI1_SRC] = &csi1_src.clkr, 2652 [CSI1_CLK] = &csi1_clk.clkr, 2653 [CSI1_PHY_CLK] = &csi1_phy_clk.clkr, 2654 [CSI2_SRC] = &csi2_src.clkr, 2655 [CSI2_CLK] = &csi2_clk.clkr, 2656 [CSI2_PHY_CLK] = &csi2_phy_clk.clkr, 2657 [DSI_SRC] = &dsi1_src.clkr, 2658 [DSI_CLK] = &dsi1_clk.clkr, 2659 [CSI_PIX_CLK] = &csi_pix_clk.clkr, 2660 [CSI_RDI_CLK] = &csi_rdi_clk.clkr, 2661 [MDP_VSYNC_CLK] = &mdp_vsync_clk.clkr, 2662 [HDMI_APP_CLK] = &hdmi_app_clk.clkr, 2663 [CSI_PIX1_CLK] = &csi_pix1_clk.clkr, 2664 [CSI_RDI2_CLK] = &csi_rdi2_clk.clkr, 2665 [CSI_RDI1_CLK] = &csi_rdi1_clk.clkr, 2666 [GFX2D0_SRC] = &gfx2d0_src.clkr, 2667 [GFX2D0_CLK] = &gfx2d0_clk.clkr, 2668 [GFX2D1_SRC] = &gfx2d1_src.clkr, 2669 [GFX2D1_CLK] = &gfx2d1_clk.clkr, 2670 [GFX3D_SRC] = &gfx3d_src.clkr, 2671 [GFX3D_CLK] = &gfx3d_clk.clkr, 2672 [IJPEG_SRC] = &ijpeg_src.clkr, 2673 [IJPEG_CLK] = &ijpeg_clk.clkr, 2674 [JPEGD_SRC] = &jpegd_src.clkr, 2675 [JPEGD_CLK] = &jpegd_clk.clkr, 2676 [MDP_SRC] = &mdp_src.clkr, 2677 [MDP_CLK] = &mdp_clk.clkr, 2678 [MDP_LUT_CLK] = &mdp_lut_clk.clkr, 2679 [DSI2_PIXEL_SRC] = &dsi2_pixel_src.clkr, 2680 [DSI2_PIXEL_CLK] = &dsi2_pixel_clk.clkr, 2681 [DSI2_SRC] = &dsi2_src.clkr, 2682 [DSI2_CLK] = &dsi2_clk.clkr, 2683 [DSI1_BYTE_SRC] = &dsi1_byte_src.clkr, 2684 [DSI1_BYTE_CLK] = &dsi1_byte_clk.clkr, 2685 [DSI2_BYTE_SRC] = &dsi2_byte_src.clkr, 2686 [DSI2_BYTE_CLK] = &dsi2_byte_clk.clkr, 2687 [DSI1_ESC_SRC] = &dsi1_esc_src.clkr, 2688 [DSI1_ESC_CLK] = &dsi1_esc_clk.clkr, 2689 [DSI2_ESC_SRC] = &dsi2_esc_src.clkr, 2690 [DSI2_ESC_CLK] = &dsi2_esc_clk.clkr, 2691 [ROT_SRC] = &rot_src.clkr, 2692 [ROT_CLK] = &rot_clk.clkr, 2693 [TV_ENC_CLK] = &tv_enc_clk.clkr, 2694 [TV_DAC_CLK] = &tv_dac_clk.clkr, 2695 [HDMI_TV_CLK] = &hdmi_tv_clk.clkr, 2696 [MDP_TV_CLK] = &mdp_tv_clk.clkr, 2697 [TV_SRC] = &tv_src.clkr, 2698 [VCODEC_SRC] = &vcodec_src.clkr, 2699 [VCODEC_CLK] = &vcodec_clk.clkr, 2700 [VFE_SRC] = &vfe_src.clkr, 2701 [VFE_CLK] = &vfe_clk.clkr, 2702 [VFE_CSI_CLK] = &vfe_csi_clk.clkr, 2703 [VPE_SRC] = &vpe_src.clkr, 2704 [VPE_CLK] = &vpe_clk.clkr, 2705 [DSI_PIXEL_SRC] = &dsi1_pixel_src.clkr, 2706 [DSI_PIXEL_CLK] = &dsi1_pixel_clk.clkr, 2707 [CAMCLK0_SRC] = &camclk0_src.clkr, 2708 [CAMCLK0_CLK] = &camclk0_clk.clkr, 2709 [CAMCLK1_SRC] = &camclk1_src.clkr, 2710 [CAMCLK1_CLK] = &camclk1_clk.clkr, 2711 [CAMCLK2_SRC] = &camclk2_src.clkr, 2712 [CAMCLK2_CLK] = &camclk2_clk.clkr, 2713 [CSIPHYTIMER_SRC] = &csiphytimer_src.clkr, 2714 [CSIPHY2_TIMER_CLK] = &csiphy2_timer_clk.clkr, 2715 [CSIPHY1_TIMER_CLK] = &csiphy1_timer_clk.clkr, 2716 [CSIPHY0_TIMER_CLK] = &csiphy0_timer_clk.clkr, 2717 [PLL2] = &pll2.clkr, 2718}; 2719 2720static const struct qcom_reset_map mmcc_msm8960_resets[] = { 2721 [VPE_AXI_RESET] = { 0x0208, 15 }, 2722 [IJPEG_AXI_RESET] = { 0x0208, 14 }, 2723 [MPD_AXI_RESET] = { 0x0208, 13 }, 2724 [VFE_AXI_RESET] = { 0x0208, 9 }, 2725 [SP_AXI_RESET] = { 0x0208, 8 }, 2726 [VCODEC_AXI_RESET] = { 0x0208, 7 }, 2727 [ROT_AXI_RESET] = { 0x0208, 6 }, 2728 [VCODEC_AXI_A_RESET] = { 0x0208, 5 }, 2729 [VCODEC_AXI_B_RESET] = { 0x0208, 4 }, 2730 [FAB_S3_AXI_RESET] = { 0x0208, 3 }, 2731 [FAB_S2_AXI_RESET] = { 0x0208, 2 }, 2732 [FAB_S1_AXI_RESET] = { 0x0208, 1 }, 2733 [FAB_S0_AXI_RESET] = { 0x0208 }, 2734 [SMMU_GFX3D_ABH_RESET] = { 0x020c, 31 }, 2735 [SMMU_VPE_AHB_RESET] = { 0x020c, 30 }, 2736 [SMMU_VFE_AHB_RESET] = { 0x020c, 29 }, 2737 [SMMU_ROT_AHB_RESET] = { 0x020c, 28 }, 2738 [SMMU_VCODEC_B_AHB_RESET] = { 0x020c, 27 }, 2739 [SMMU_VCODEC_A_AHB_RESET] = { 0x020c, 26 }, 2740 [SMMU_MDP1_AHB_RESET] = { 0x020c, 25 }, 2741 [SMMU_MDP0_AHB_RESET] = { 0x020c, 24 }, 2742 [SMMU_JPEGD_AHB_RESET] = { 0x020c, 23 }, 2743 [SMMU_IJPEG_AHB_RESET] = { 0x020c, 22 }, 2744 [SMMU_GFX2D0_AHB_RESET] = { 0x020c, 21 }, 2745 [SMMU_GFX2D1_AHB_RESET] = { 0x020c, 20 }, 2746 [APU_AHB_RESET] = { 0x020c, 18 }, 2747 [CSI_AHB_RESET] = { 0x020c, 17 }, 2748 [TV_ENC_AHB_RESET] = { 0x020c, 15 }, 2749 [VPE_AHB_RESET] = { 0x020c, 14 }, 2750 [FABRIC_AHB_RESET] = { 0x020c, 13 }, 2751 [GFX2D0_AHB_RESET] = { 0x020c, 12 }, 2752 [GFX2D1_AHB_RESET] = { 0x020c, 11 }, 2753 [GFX3D_AHB_RESET] = { 0x020c, 10 }, 2754 [HDMI_AHB_RESET] = { 0x020c, 9 }, 2755 [MSSS_IMEM_AHB_RESET] = { 0x020c, 8 }, 2756 [IJPEG_AHB_RESET] = { 0x020c, 7 }, 2757 [DSI_M_AHB_RESET] = { 0x020c, 6 }, 2758 [DSI_S_AHB_RESET] = { 0x020c, 5 }, 2759 [JPEGD_AHB_RESET] = { 0x020c, 4 }, 2760 [MDP_AHB_RESET] = { 0x020c, 3 }, 2761 [ROT_AHB_RESET] = { 0x020c, 2 }, 2762 [VCODEC_AHB_RESET] = { 0x020c, 1 }, 2763 [VFE_AHB_RESET] = { 0x020c, 0 }, 2764 [DSI2_M_AHB_RESET] = { 0x0210, 31 }, 2765 [DSI2_S_AHB_RESET] = { 0x0210, 30 }, 2766 [CSIPHY2_RESET] = { 0x0210, 29 }, 2767 [CSI_PIX1_RESET] = { 0x0210, 28 }, 2768 [CSIPHY0_RESET] = { 0x0210, 27 }, 2769 [CSIPHY1_RESET] = { 0x0210, 26 }, 2770 [DSI2_RESET] = { 0x0210, 25 }, 2771 [VFE_CSI_RESET] = { 0x0210, 24 }, 2772 [MDP_RESET] = { 0x0210, 21 }, 2773 [AMP_RESET] = { 0x0210, 20 }, 2774 [JPEGD_RESET] = { 0x0210, 19 }, 2775 [CSI1_RESET] = { 0x0210, 18 }, 2776 [VPE_RESET] = { 0x0210, 17 }, 2777 [MMSS_FABRIC_RESET] = { 0x0210, 16 }, 2778 [VFE_RESET] = { 0x0210, 15 }, 2779 [GFX2D0_RESET] = { 0x0210, 14 }, 2780 [GFX2D1_RESET] = { 0x0210, 13 }, 2781 [GFX3D_RESET] = { 0x0210, 12 }, 2782 [HDMI_RESET] = { 0x0210, 11 }, 2783 [MMSS_IMEM_RESET] = { 0x0210, 10 }, 2784 [IJPEG_RESET] = { 0x0210, 9 }, 2785 [CSI0_RESET] = { 0x0210, 8 }, 2786 [DSI_RESET] = { 0x0210, 7 }, 2787 [VCODEC_RESET] = { 0x0210, 6 }, 2788 [MDP_TV_RESET] = { 0x0210, 4 }, 2789 [MDP_VSYNC_RESET] = { 0x0210, 3 }, 2790 [ROT_RESET] = { 0x0210, 2 }, 2791 [TV_HDMI_RESET] = { 0x0210, 1 }, 2792 [TV_ENC_RESET] = { 0x0210 }, 2793 [CSI2_RESET] = { 0x0214, 2 }, 2794 [CSI_RDI1_RESET] = { 0x0214, 1 }, 2795 [CSI_RDI2_RESET] = { 0x0214 }, 2796}; 2797 2798static struct clk_regmap *mmcc_apq8064_clks[] = { 2799 [AMP_AHB_CLK] = &_ahb_clk.clkr, 2800 [DSI2_S_AHB_CLK] = &dsi2_s_ahb_clk.clkr, 2801 [JPEGD_AHB_CLK] = &jpegd_ahb_clk.clkr, 2802 [DSI_S_AHB_CLK] = &dsi_s_ahb_clk.clkr, 2803 [DSI2_M_AHB_CLK] = &dsi2_m_ahb_clk.clkr, 2804 [VPE_AHB_CLK] = &vpe_ahb_clk.clkr, 2805 [SMMU_AHB_CLK] = &smmu_ahb_clk.clkr, 2806 [HDMI_M_AHB_CLK] = &hdmi_m_ahb_clk.clkr, 2807 [VFE_AHB_CLK] = &vfe_ahb_clk.clkr, 2808 [ROT_AHB_CLK] = &rot_ahb_clk.clkr, 2809 [VCODEC_AHB_CLK] = &vcodec_ahb_clk.clkr, 2810 [MDP_AHB_CLK] = &mdp_ahb_clk.clkr, 2811 [DSI_M_AHB_CLK] = &dsi_m_ahb_clk.clkr, 2812 [CSI_AHB_CLK] = &csi_ahb_clk.clkr, 2813 [MMSS_IMEM_AHB_CLK] = &mmss_imem_ahb_clk.clkr, 2814 [IJPEG_AHB_CLK] = &ijpeg_ahb_clk.clkr, 2815 [HDMI_S_AHB_CLK] = &hdmi_s_ahb_clk.clkr, 2816 [GFX3D_AHB_CLK] = &gfx3d_ahb_clk.clkr, 2817 [JPEGD_AXI_CLK] = &jpegd_axi_clk.clkr, 2818 [GMEM_AXI_CLK] = &gmem_axi_clk.clkr, 2819 [MDP_AXI_CLK] = &mdp_axi_clk.clkr, 2820 [MMSS_IMEM_AXI_CLK] = &mmss_imem_axi_clk.clkr, 2821 [IJPEG_AXI_CLK] = &ijpeg_axi_clk.clkr, 2822 [GFX3D_AXI_CLK] = &gfx3d_axi_clk.clkr, 2823 [VCODEC_AXI_CLK] = &vcodec_axi_clk.clkr, 2824 [VFE_AXI_CLK] = &vfe_axi_clk.clkr, 2825 [VPE_AXI_CLK] = &vpe_axi_clk.clkr, 2826 [ROT_AXI_CLK] = &rot_axi_clk.clkr, 2827 [VCODEC_AXI_A_CLK] = &vcodec_axi_a_clk.clkr, 2828 [VCODEC_AXI_B_CLK] = &vcodec_axi_b_clk.clkr, 2829 [CSI0_SRC] = &csi0_src.clkr, 2830 [CSI0_CLK] = &csi0_clk.clkr, 2831 [CSI0_PHY_CLK] = &csi0_phy_clk.clkr, 2832 [CSI1_SRC] = &csi1_src.clkr, 2833 [CSI1_CLK] = &csi1_clk.clkr, 2834 [CSI1_PHY_CLK] = &csi1_phy_clk.clkr, 2835 [CSI2_SRC] = &csi2_src.clkr, 2836 [CSI2_CLK] = &csi2_clk.clkr, 2837 [CSI2_PHY_CLK] = &csi2_phy_clk.clkr, 2838 [DSI_SRC] = &dsi1_src.clkr, 2839 [DSI_CLK] = &dsi1_clk.clkr, 2840 [CSI_PIX_CLK] = &csi_pix_clk.clkr, 2841 [CSI_RDI_CLK] = &csi_rdi_clk.clkr, 2842 [MDP_VSYNC_CLK] = &mdp_vsync_clk.clkr, 2843 [HDMI_APP_CLK] = &hdmi_app_clk.clkr, 2844 [CSI_PIX1_CLK] = &csi_pix1_clk.clkr, 2845 [CSI_RDI2_CLK] = &csi_rdi2_clk.clkr, 2846 [CSI_RDI1_CLK] = &csi_rdi1_clk.clkr, 2847 [GFX3D_SRC] = &gfx3d_src.clkr, 2848 [GFX3D_CLK] = &gfx3d_clk.clkr, 2849 [IJPEG_SRC] = &ijpeg_src.clkr, 2850 [IJPEG_CLK] = &ijpeg_clk.clkr, 2851 [JPEGD_SRC] = &jpegd_src.clkr, 2852 [JPEGD_CLK] = &jpegd_clk.clkr, 2853 [MDP_SRC] = &mdp_src.clkr, 2854 [MDP_CLK] = &mdp_clk.clkr, 2855 [MDP_LUT_CLK] = &mdp_lut_clk.clkr, 2856 [DSI2_PIXEL_SRC] = &dsi2_pixel_src.clkr, 2857 [DSI2_PIXEL_CLK] = &dsi2_pixel_clk.clkr, 2858 [DSI2_SRC] = &dsi2_src.clkr, 2859 [DSI2_CLK] = &dsi2_clk.clkr, 2860 [DSI1_BYTE_SRC] = &dsi1_byte_src.clkr, 2861 [DSI1_BYTE_CLK] = &dsi1_byte_clk.clkr, 2862 [DSI2_BYTE_SRC] = &dsi2_byte_src.clkr, 2863 [DSI2_BYTE_CLK] = &dsi2_byte_clk.clkr, 2864 [DSI1_ESC_SRC] = &dsi1_esc_src.clkr, 2865 [DSI1_ESC_CLK] = &dsi1_esc_clk.clkr, 2866 [DSI2_ESC_SRC] = &dsi2_esc_src.clkr, 2867 [DSI2_ESC_CLK] = &dsi2_esc_clk.clkr, 2868 [ROT_SRC] = &rot_src.clkr, 2869 [ROT_CLK] = &rot_clk.clkr, 2870 [TV_DAC_CLK] = &tv_dac_clk.clkr, 2871 [HDMI_TV_CLK] = &hdmi_tv_clk.clkr, 2872 [MDP_TV_CLK] = &mdp_tv_clk.clkr, 2873 [TV_SRC] = &tv_src.clkr, 2874 [VCODEC_SRC] = &vcodec_src.clkr, 2875 [VCODEC_CLK] = &vcodec_clk.clkr, 2876 [VFE_SRC] = &vfe_src.clkr, 2877 [VFE_CLK] = &vfe_clk.clkr, 2878 [VFE_CSI_CLK] = &vfe_csi_clk.clkr, 2879 [VPE_SRC] = &vpe_src.clkr, 2880 [VPE_CLK] = &vpe_clk.clkr, 2881 [DSI_PIXEL_SRC] = &dsi1_pixel_src.clkr, 2882 [DSI_PIXEL_CLK] = &dsi1_pixel_clk.clkr, 2883 [CAMCLK0_SRC] = &camclk0_src.clkr, 2884 [CAMCLK0_CLK] = &camclk0_clk.clkr, 2885 [CAMCLK1_SRC] = &camclk1_src.clkr, 2886 [CAMCLK1_CLK] = &camclk1_clk.clkr, 2887 [CAMCLK2_SRC] = &camclk2_src.clkr, 2888 [CAMCLK2_CLK] = &camclk2_clk.clkr, 2889 [CSIPHYTIMER_SRC] = &csiphytimer_src.clkr, 2890 [CSIPHY2_TIMER_CLK] = &csiphy2_timer_clk.clkr, 2891 [CSIPHY1_TIMER_CLK] = &csiphy1_timer_clk.clkr, 2892 [CSIPHY0_TIMER_CLK] = &csiphy0_timer_clk.clkr, 2893 [PLL2] = &pll2.clkr, 2894 [RGB_TV_CLK] = &rgb_tv_clk.clkr, 2895 [NPL_TV_CLK] = &npl_tv_clk.clkr, 2896 [VCAP_AHB_CLK] = &vcap_ahb_clk.clkr, 2897 [VCAP_AXI_CLK] = &vcap_axi_clk.clkr, 2898 [VCAP_SRC] = &vcap_src.clkr, 2899 [VCAP_CLK] = &vcap_clk.clkr, 2900 [VCAP_NPL_CLK] = &vcap_npl_clk.clkr, 2901 [PLL15] = &pll15.clkr, 2902}; 2903 2904static const struct qcom_reset_map mmcc_apq8064_resets[] = { 2905 [GFX3D_AXI_RESET] = { 0x0208, 17 }, 2906 [VCAP_AXI_RESET] = { 0x0208, 16 }, 2907 [VPE_AXI_RESET] = { 0x0208, 15 }, 2908 [IJPEG_AXI_RESET] = { 0x0208, 14 }, 2909 [MPD_AXI_RESET] = { 0x0208, 13 }, 2910 [VFE_AXI_RESET] = { 0x0208, 9 }, 2911 [SP_AXI_RESET] = { 0x0208, 8 }, 2912 [VCODEC_AXI_RESET] = { 0x0208, 7 }, 2913 [ROT_AXI_RESET] = { 0x0208, 6 }, 2914 [VCODEC_AXI_A_RESET] = { 0x0208, 5 }, 2915 [VCODEC_AXI_B_RESET] = { 0x0208, 4 }, 2916 [FAB_S3_AXI_RESET] = { 0x0208, 3 }, 2917 [FAB_S2_AXI_RESET] = { 0x0208, 2 }, 2918 [FAB_S1_AXI_RESET] = { 0x0208, 1 }, 2919 [FAB_S0_AXI_RESET] = { 0x0208 }, 2920 [SMMU_GFX3D_ABH_RESET] = { 0x020c, 31 }, 2921 [SMMU_VPE_AHB_RESET] = { 0x020c, 30 }, 2922 [SMMU_VFE_AHB_RESET] = { 0x020c, 29 }, 2923 [SMMU_ROT_AHB_RESET] = { 0x020c, 28 }, 2924 [SMMU_VCODEC_B_AHB_RESET] = { 0x020c, 27 }, 2925 [SMMU_VCODEC_A_AHB_RESET] = { 0x020c, 26 }, 2926 [SMMU_MDP1_AHB_RESET] = { 0x020c, 25 }, 2927 [SMMU_MDP0_AHB_RESET] = { 0x020c, 24 }, 2928 [SMMU_JPEGD_AHB_RESET] = { 0x020c, 23 }, 2929 [SMMU_IJPEG_AHB_RESET] = { 0x020c, 22 }, 2930 [APU_AHB_RESET] = { 0x020c, 18 }, 2931 [CSI_AHB_RESET] = { 0x020c, 17 }, 2932 [TV_ENC_AHB_RESET] = { 0x020c, 15 }, 2933 [VPE_AHB_RESET] = { 0x020c, 14 }, 2934 [FABRIC_AHB_RESET] = { 0x020c, 13 }, 2935 [GFX3D_AHB_RESET] = { 0x020c, 10 }, 2936 [HDMI_AHB_RESET] = { 0x020c, 9 }, 2937 [MSSS_IMEM_AHB_RESET] = { 0x020c, 8 }, 2938 [IJPEG_AHB_RESET] = { 0x020c, 7 }, 2939 [DSI_M_AHB_RESET] = { 0x020c, 6 }, 2940 [DSI_S_AHB_RESET] = { 0x020c, 5 }, 2941 [JPEGD_AHB_RESET] = { 0x020c, 4 }, 2942 [MDP_AHB_RESET] = { 0x020c, 3 }, 2943 [ROT_AHB_RESET] = { 0x020c, 2 }, 2944 [VCODEC_AHB_RESET] = { 0x020c, 1 }, 2945 [VFE_AHB_RESET] = { 0x020c, 0 }, 2946 [SMMU_VCAP_AHB_RESET] = { 0x0200, 3 }, 2947 [VCAP_AHB_RESET] = { 0x0200, 2 }, 2948 [DSI2_M_AHB_RESET] = { 0x0200, 1 }, 2949 [DSI2_S_AHB_RESET] = { 0x0200, 0 }, 2950 [CSIPHY2_RESET] = { 0x0210, 31 }, 2951 [CSI_PIX1_RESET] = { 0x0210, 30 }, 2952 [CSIPHY0_RESET] = { 0x0210, 29 }, 2953 [CSIPHY1_RESET] = { 0x0210, 28 }, 2954 [CSI_RDI_RESET] = { 0x0210, 27 }, 2955 [CSI_PIX_RESET] = { 0x0210, 26 }, 2956 [DSI2_RESET] = { 0x0210, 25 }, 2957 [VFE_CSI_RESET] = { 0x0210, 24 }, 2958 [MDP_RESET] = { 0x0210, 21 }, 2959 [AMP_RESET] = { 0x0210, 20 }, 2960 [JPEGD_RESET] = { 0x0210, 19 }, 2961 [CSI1_RESET] = { 0x0210, 18 }, 2962 [VPE_RESET] = { 0x0210, 17 }, 2963 [MMSS_FABRIC_RESET] = { 0x0210, 16 }, 2964 [VFE_RESET] = { 0x0210, 15 }, 2965 [GFX3D_RESET] = { 0x0210, 12 }, 2966 [HDMI_RESET] = { 0x0210, 11 }, 2967 [MMSS_IMEM_RESET] = { 0x0210, 10 }, 2968 [IJPEG_RESET] = { 0x0210, 9 }, 2969 [CSI0_RESET] = { 0x0210, 8 }, 2970 [DSI_RESET] = { 0x0210, 7 }, 2971 [VCODEC_RESET] = { 0x0210, 6 }, 2972 [MDP_TV_RESET] = { 0x0210, 4 }, 2973 [MDP_VSYNC_RESET] = { 0x0210, 3 }, 2974 [ROT_RESET] = { 0x0210, 2 }, 2975 [TV_HDMI_RESET] = { 0x0210, 1 }, 2976 [VCAP_NPL_RESET] = { 0x0214, 4 }, 2977 [VCAP_RESET] = { 0x0214, 3 }, 2978 [CSI2_RESET] = { 0x0214, 2 }, 2979 [CSI_RDI1_RESET] = { 0x0214, 1 }, 2980 [CSI_RDI2_RESET] = { 0x0214 }, 2981}; 2982 2983static const struct regmap_config mmcc_msm8960_regmap_config = { 2984 .reg_bits = 32, 2985 .reg_stride = 4, 2986 .val_bits = 32, 2987 .max_register = 0x334, 2988 .fast_io = true, 2989}; 2990 2991static const struct regmap_config mmcc_apq8064_regmap_config = { 2992 .reg_bits = 32, 2993 .reg_stride = 4, 2994 .val_bits = 32, 2995 .max_register = 0x350, 2996 .fast_io = true, 2997}; 2998 2999static const struct qcom_cc_desc mmcc_msm8960_desc = { 3000 .config = &mmcc_msm8960_regmap_config, 3001 .clks = mmcc_msm8960_clks, 3002 .num_clks = ARRAY_SIZE(mmcc_msm8960_clks), 3003 .resets = mmcc_msm8960_resets, 3004 .num_resets = ARRAY_SIZE(mmcc_msm8960_resets), 3005}; 3006 3007static const struct qcom_cc_desc mmcc_apq8064_desc = { 3008 .config = &mmcc_apq8064_regmap_config, 3009 .clks = mmcc_apq8064_clks, 3010 .num_clks = ARRAY_SIZE(mmcc_apq8064_clks), 3011 .resets = mmcc_apq8064_resets, 3012 .num_resets = ARRAY_SIZE(mmcc_apq8064_resets), 3013}; 3014 3015static const struct of_device_id mmcc_msm8960_match_table[] = { 3016 { .compatible = "qcom,mmcc-msm8960", .data = &mmcc_msm8960_desc }, 3017 { .compatible = "qcom,mmcc-apq8064", .data = &mmcc_apq8064_desc }, 3018 { } 3019}; 3020MODULE_DEVICE_TABLE(of, mmcc_msm8960_match_table); 3021 3022static int mmcc_msm8960_probe(struct platform_device *pdev) 3023{ 3024 const struct of_device_id *match; 3025 struct regmap *regmap; 3026 bool is_8064; 3027 struct device *dev = &pdev->dev; 3028 3029 match = of_match_device(mmcc_msm8960_match_table, dev); 3030 if (!match) 3031 return -EINVAL; 3032 3033 is_8064 = of_device_is_compatible(dev->of_node, "qcom,mmcc-apq8064"); 3034 if (is_8064) { 3035 gfx3d_src.freq_tbl = clk_tbl_gfx3d_8064; 3036 gfx3d_src.clkr.hw.init = &gfx3d_8064_init; 3037 gfx3d_src.s[0].parent_map = mmcc_pxo_pll8_pll2_pll15_map; 3038 gfx3d_src.s[1].parent_map = mmcc_pxo_pll8_pll2_pll15_map; 3039 } 3040 3041 regmap = qcom_cc_map(pdev, match->data); 3042 if (IS_ERR(regmap)) 3043 return PTR_ERR(regmap); 3044 3045 clk_pll_configure_sr(&pll15, regmap, &pll15_config, false); 3046 3047 return qcom_cc_really_probe(pdev, match->data, regmap); 3048} 3049 3050static struct platform_driver mmcc_msm8960_driver = { 3051 .probe = mmcc_msm8960_probe, 3052 .driver = { 3053 .name = "mmcc-msm8960", 3054 .of_match_table = mmcc_msm8960_match_table, 3055 }, 3056}; 3057 3058module_platform_driver(mmcc_msm8960_driver); 3059 3060MODULE_DESCRIPTION("QCOM MMCC MSM8960 Driver"); 3061MODULE_LICENSE("GPL v2"); 3062MODULE_ALIAS("platform:mmcc-msm8960"); 3063