1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. 4 */ 5 6#include <linux/kernel.h> 7#include <linux/platform_device.h> 8#include <linux/module.h> 9#include <linux/regmap.h> 10#include <linux/reset-controller.h> 11 12#include <dt-bindings/clock/qcom,mmcc-apq8084.h> 13#include <dt-bindings/reset/qcom,mmcc-apq8084.h> 14 15#include "common.h" 16#include "clk-regmap.h" 17#include "clk-pll.h" 18#include "clk-rcg.h" 19#include "clk-branch.h" 20#include "reset.h" 21#include "gdsc.h" 22 23enum { 24 P_XO, 25 P_MMPLL0, 26 P_EDPLINK, 27 P_MMPLL1, 28 P_HDMIPLL, 29 P_GPLL0, 30 P_EDPVCO, 31 P_MMPLL4, 32 P_DSI0PLL, 33 P_DSI0PLL_BYTE, 34 P_MMPLL2, 35 P_MMPLL3, 36 P_GPLL1, 37 P_DSI1PLL, 38 P_DSI1PLL_BYTE, 39 P_MMSLEEP, 40}; 41 42static const struct parent_map mmcc_xo_mmpll0_mmpll1_gpll0_map[] = { 43 { P_XO, 0 }, 44 { P_MMPLL0, 1 }, 45 { P_MMPLL1, 2 }, 46 { P_GPLL0, 5 } 47}; 48 49static const char * const mmcc_xo_mmpll0_mmpll1_gpll0[] = { 50 "xo", 51 "mmpll0_vote", 52 "mmpll1_vote", 53 "mmss_gpll0_vote", 54}; 55 56static const struct parent_map mmcc_xo_mmpll0_dsi_hdmi_gpll0_map[] = { 57 { P_XO, 0 }, 58 { P_MMPLL0, 1 }, 59 { P_HDMIPLL, 4 }, 60 { P_GPLL0, 5 }, 61 { P_DSI0PLL, 2 }, 62 { P_DSI1PLL, 3 } 63}; 64 65static const char * const mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = { 66 "xo", 67 "mmpll0_vote", 68 "hdmipll", 69 "mmss_gpll0_vote", 70 "dsi0pll", 71 "dsi1pll", 72}; 73 74static const struct parent_map mmcc_xo_mmpll0_1_2_gpll0_map[] = { 75 { P_XO, 0 }, 76 { P_MMPLL0, 1 }, 77 { P_MMPLL1, 2 }, 78 { P_GPLL0, 5 }, 79 { P_MMPLL2, 3 } 80}; 81 82static const char * const mmcc_xo_mmpll0_1_2_gpll0[] = { 83 "xo", 84 "mmpll0_vote", 85 "mmpll1_vote", 86 "mmss_gpll0_vote", 87 "mmpll2", 88}; 89 90static const struct parent_map mmcc_xo_mmpll0_1_3_gpll0_map[] = { 91 { P_XO, 0 }, 92 { P_MMPLL0, 1 }, 93 { P_MMPLL1, 2 }, 94 { P_GPLL0, 5 }, 95 { P_MMPLL3, 3 } 96}; 97 98static const char * const mmcc_xo_mmpll0_1_3_gpll0[] = { 99 "xo", 100 "mmpll0_vote", 101 "mmpll1_vote", 102 "mmss_gpll0_vote", 103 "mmpll3", 104}; 105 106static const struct parent_map mmcc_xo_dsi_hdmi_edp_map[] = { 107 { P_XO, 0 }, 108 { P_EDPLINK, 4 }, 109 { P_HDMIPLL, 3 }, 110 { P_EDPVCO, 5 }, 111 { P_DSI0PLL, 1 }, 112 { P_DSI1PLL, 2 } 113}; 114 115static const char * const mmcc_xo_dsi_hdmi_edp[] = { 116 "xo", 117 "edp_link_clk", 118 "hdmipll", 119 "edp_vco_div", 120 "dsi0pll", 121 "dsi1pll", 122}; 123 124static const struct parent_map mmcc_xo_dsi_hdmi_edp_gpll0_map[] = { 125 { P_XO, 0 }, 126 { P_EDPLINK, 4 }, 127 { P_HDMIPLL, 3 }, 128 { P_GPLL0, 5 }, 129 { P_DSI0PLL, 1 }, 130 { P_DSI1PLL, 2 } 131}; 132 133static const char * const mmcc_xo_dsi_hdmi_edp_gpll0[] = { 134 "xo", 135 "edp_link_clk", 136 "hdmipll", 137 "gpll0_vote", 138 "dsi0pll", 139 "dsi1pll", 140}; 141 142static const struct parent_map mmcc_xo_dsibyte_hdmi_edp_gpll0_map[] = { 143 { P_XO, 0 }, 144 { P_EDPLINK, 4 }, 145 { P_HDMIPLL, 3 }, 146 { P_GPLL0, 5 }, 147 { P_DSI0PLL_BYTE, 1 }, 148 { P_DSI1PLL_BYTE, 2 } 149}; 150 151static const char * const mmcc_xo_dsibyte_hdmi_edp_gpll0[] = { 152 "xo", 153 "edp_link_clk", 154 "hdmipll", 155 "gpll0_vote", 156 "dsi0pllbyte", 157 "dsi1pllbyte", 158}; 159 160static const struct parent_map mmcc_xo_mmpll0_1_4_gpll0_map[] = { 161 { P_XO, 0 }, 162 { P_MMPLL0, 1 }, 163 { P_MMPLL1, 2 }, 164 { P_GPLL0, 5 }, 165 { P_MMPLL4, 3 } 166}; 167 168static const char * const mmcc_xo_mmpll0_1_4_gpll0[] = { 169 "xo", 170 "mmpll0", 171 "mmpll1", 172 "mmpll4", 173 "gpll0", 174}; 175 176static const struct parent_map mmcc_xo_mmpll0_1_4_gpll1_0_map[] = { 177 { P_XO, 0 }, 178 { P_MMPLL0, 1 }, 179 { P_MMPLL1, 2 }, 180 { P_MMPLL4, 3 }, 181 { P_GPLL0, 5 }, 182 { P_GPLL1, 4 } 183}; 184 185static const char * const mmcc_xo_mmpll0_1_4_gpll1_0[] = { 186 "xo", 187 "mmpll0", 188 "mmpll1", 189 "mmpll4", 190 "gpll1", 191 "gpll0", 192}; 193 194static const struct parent_map mmcc_xo_mmpll0_1_4_gpll1_0_sleep_map[] = { 195 { P_XO, 0 }, 196 { P_MMPLL0, 1 }, 197 { P_MMPLL1, 2 }, 198 { P_MMPLL4, 3 }, 199 { P_GPLL0, 5 }, 200 { P_GPLL1, 4 }, 201 { P_MMSLEEP, 6 } 202}; 203 204static const char * const mmcc_xo_mmpll0_1_4_gpll1_0_sleep[] = { 205 "xo", 206 "mmpll0", 207 "mmpll1", 208 "mmpll4", 209 "gpll1", 210 "gpll0", 211 "sleep_clk_src", 212}; 213 214static struct clk_pll mmpll0 = { 215 .l_reg = 0x0004, 216 .m_reg = 0x0008, 217 .n_reg = 0x000c, 218 .config_reg = 0x0014, 219 .mode_reg = 0x0000, 220 .status_reg = 0x001c, 221 .status_bit = 17, 222 .clkr.hw.init = &(struct clk_init_data){ 223 .name = "mmpll0", 224 .parent_names = (const char *[]){ "xo" }, 225 .num_parents = 1, 226 .ops = &clk_pll_ops, 227 }, 228}; 229 230static struct clk_regmap mmpll0_vote = { 231 .enable_reg = 0x0100, 232 .enable_mask = BIT(0), 233 .hw.init = &(struct clk_init_data){ 234 .name = "mmpll0_vote", 235 .parent_names = (const char *[]){ "mmpll0" }, 236 .num_parents = 1, 237 .ops = &clk_pll_vote_ops, 238 }, 239}; 240 241static struct clk_pll mmpll1 = { 242 .l_reg = 0x0044, 243 .m_reg = 0x0048, 244 .n_reg = 0x004c, 245 .config_reg = 0x0050, 246 .mode_reg = 0x0040, 247 .status_reg = 0x005c, 248 .status_bit = 17, 249 .clkr.hw.init = &(struct clk_init_data){ 250 .name = "mmpll1", 251 .parent_names = (const char *[]){ "xo" }, 252 .num_parents = 1, 253 .ops = &clk_pll_ops, 254 }, 255}; 256 257static struct clk_regmap mmpll1_vote = { 258 .enable_reg = 0x0100, 259 .enable_mask = BIT(1), 260 .hw.init = &(struct clk_init_data){ 261 .name = "mmpll1_vote", 262 .parent_names = (const char *[]){ "mmpll1" }, 263 .num_parents = 1, 264 .ops = &clk_pll_vote_ops, 265 }, 266}; 267 268static struct clk_pll mmpll2 = { 269 .l_reg = 0x4104, 270 .m_reg = 0x4108, 271 .n_reg = 0x410c, 272 .config_reg = 0x4110, 273 .mode_reg = 0x4100, 274 .status_reg = 0x411c, 275 .clkr.hw.init = &(struct clk_init_data){ 276 .name = "mmpll2", 277 .parent_names = (const char *[]){ "xo" }, 278 .num_parents = 1, 279 .ops = &clk_pll_ops, 280 }, 281}; 282 283static struct clk_pll mmpll3 = { 284 .l_reg = 0x0084, 285 .m_reg = 0x0088, 286 .n_reg = 0x008c, 287 .config_reg = 0x0090, 288 .mode_reg = 0x0080, 289 .status_reg = 0x009c, 290 .status_bit = 17, 291 .clkr.hw.init = &(struct clk_init_data){ 292 .name = "mmpll3", 293 .parent_names = (const char *[]){ "xo" }, 294 .num_parents = 1, 295 .ops = &clk_pll_ops, 296 }, 297}; 298 299static struct clk_pll mmpll4 = { 300 .l_reg = 0x00a4, 301 .m_reg = 0x00a8, 302 .n_reg = 0x00ac, 303 .config_reg = 0x00b0, 304 .mode_reg = 0x0080, 305 .status_reg = 0x00bc, 306 .clkr.hw.init = &(struct clk_init_data){ 307 .name = "mmpll4", 308 .parent_names = (const char *[]){ "xo" }, 309 .num_parents = 1, 310 .ops = &clk_pll_ops, 311 }, 312}; 313 314static struct clk_rcg2 mmss_ahb_clk_src = { 315 .cmd_rcgr = 0x5000, 316 .hid_width = 5, 317 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, 318 .clkr.hw.init = &(struct clk_init_data){ 319 .name = "mmss_ahb_clk_src", 320 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, 321 .num_parents = 4, 322 .ops = &clk_rcg2_ops, 323 }, 324}; 325 326static struct freq_tbl ftbl_mmss_axi_clk[] = { 327 F(19200000, P_XO, 1, 0, 0), 328 F(37500000, P_GPLL0, 16, 0, 0), 329 F(50000000, P_GPLL0, 12, 0, 0), 330 F(75000000, P_GPLL0, 8, 0, 0), 331 F(100000000, P_GPLL0, 6, 0, 0), 332 F(150000000, P_GPLL0, 4, 0, 0), 333 F(333430000, P_MMPLL1, 3.5, 0, 0), 334 F(400000000, P_MMPLL0, 2, 0, 0), 335 F(466800000, P_MMPLL1, 2.5, 0, 0), 336 { } 337}; 338 339static struct clk_rcg2 mmss_axi_clk_src = { 340 .cmd_rcgr = 0x5040, 341 .hid_width = 5, 342 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, 343 .freq_tbl = ftbl_mmss_axi_clk, 344 .clkr.hw.init = &(struct clk_init_data){ 345 .name = "mmss_axi_clk_src", 346 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, 347 .num_parents = 4, 348 .ops = &clk_rcg2_ops, 349 }, 350}; 351 352static struct freq_tbl ftbl_ocmemnoc_clk[] = { 353 F(19200000, P_XO, 1, 0, 0), 354 F(37500000, P_GPLL0, 16, 0, 0), 355 F(50000000, P_GPLL0, 12, 0, 0), 356 F(75000000, P_GPLL0, 8, 0, 0), 357 F(109090000, P_GPLL0, 5.5, 0, 0), 358 F(150000000, P_GPLL0, 4, 0, 0), 359 F(228570000, P_MMPLL0, 3.5, 0, 0), 360 F(320000000, P_MMPLL0, 2.5, 0, 0), 361 { } 362}; 363 364static struct clk_rcg2 ocmemnoc_clk_src = { 365 .cmd_rcgr = 0x5090, 366 .hid_width = 5, 367 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, 368 .freq_tbl = ftbl_ocmemnoc_clk, 369 .clkr.hw.init = &(struct clk_init_data){ 370 .name = "ocmemnoc_clk_src", 371 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, 372 .num_parents = 4, 373 .ops = &clk_rcg2_ops, 374 }, 375}; 376 377static struct freq_tbl ftbl_camss_csi0_3_clk[] = { 378 F(100000000, P_GPLL0, 6, 0, 0), 379 F(200000000, P_MMPLL0, 4, 0, 0), 380 { } 381}; 382 383static struct clk_rcg2 csi0_clk_src = { 384 .cmd_rcgr = 0x3090, 385 .hid_width = 5, 386 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map, 387 .freq_tbl = ftbl_camss_csi0_3_clk, 388 .clkr.hw.init = &(struct clk_init_data){ 389 .name = "csi0_clk_src", 390 .parent_names = mmcc_xo_mmpll0_1_4_gpll0, 391 .num_parents = 5, 392 .ops = &clk_rcg2_ops, 393 }, 394}; 395 396static struct clk_rcg2 csi1_clk_src = { 397 .cmd_rcgr = 0x3100, 398 .hid_width = 5, 399 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map, 400 .freq_tbl = ftbl_camss_csi0_3_clk, 401 .clkr.hw.init = &(struct clk_init_data){ 402 .name = "csi1_clk_src", 403 .parent_names = mmcc_xo_mmpll0_1_4_gpll0, 404 .num_parents = 5, 405 .ops = &clk_rcg2_ops, 406 }, 407}; 408 409static struct clk_rcg2 csi2_clk_src = { 410 .cmd_rcgr = 0x3160, 411 .hid_width = 5, 412 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map, 413 .freq_tbl = ftbl_camss_csi0_3_clk, 414 .clkr.hw.init = &(struct clk_init_data){ 415 .name = "csi2_clk_src", 416 .parent_names = mmcc_xo_mmpll0_1_4_gpll0, 417 .num_parents = 5, 418 .ops = &clk_rcg2_ops, 419 }, 420}; 421 422static struct clk_rcg2 csi3_clk_src = { 423 .cmd_rcgr = 0x31c0, 424 .hid_width = 5, 425 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map, 426 .freq_tbl = ftbl_camss_csi0_3_clk, 427 .clkr.hw.init = &(struct clk_init_data){ 428 .name = "csi3_clk_src", 429 .parent_names = mmcc_xo_mmpll0_1_4_gpll0, 430 .num_parents = 5, 431 .ops = &clk_rcg2_ops, 432 }, 433}; 434 435static struct freq_tbl ftbl_camss_vfe_vfe0_1_clk[] = { 436 F(37500000, P_GPLL0, 16, 0, 0), 437 F(50000000, P_GPLL0, 12, 0, 0), 438 F(60000000, P_GPLL0, 10, 0, 0), 439 F(80000000, P_GPLL0, 7.5, 0, 0), 440 F(100000000, P_GPLL0, 6, 0, 0), 441 F(109090000, P_GPLL0, 5.5, 0, 0), 442 F(133330000, P_GPLL0, 4.5, 0, 0), 443 F(200000000, P_GPLL0, 3, 0, 0), 444 F(228570000, P_MMPLL0, 3.5, 0, 0), 445 F(266670000, P_MMPLL0, 3, 0, 0), 446 F(320000000, P_MMPLL0, 2.5, 0, 0), 447 F(465000000, P_MMPLL4, 2, 0, 0), 448 F(600000000, P_GPLL0, 1, 0, 0), 449 { } 450}; 451 452static struct clk_rcg2 vfe0_clk_src = { 453 .cmd_rcgr = 0x3600, 454 .hid_width = 5, 455 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map, 456 .freq_tbl = ftbl_camss_vfe_vfe0_1_clk, 457 .clkr.hw.init = &(struct clk_init_data){ 458 .name = "vfe0_clk_src", 459 .parent_names = mmcc_xo_mmpll0_1_4_gpll0, 460 .num_parents = 5, 461 .ops = &clk_rcg2_ops, 462 }, 463}; 464 465static struct clk_rcg2 vfe1_clk_src = { 466 .cmd_rcgr = 0x3620, 467 .hid_width = 5, 468 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map, 469 .freq_tbl = ftbl_camss_vfe_vfe0_1_clk, 470 .clkr.hw.init = &(struct clk_init_data){ 471 .name = "vfe1_clk_src", 472 .parent_names = mmcc_xo_mmpll0_1_4_gpll0, 473 .num_parents = 5, 474 .ops = &clk_rcg2_ops, 475 }, 476}; 477 478static struct freq_tbl ftbl_mdss_mdp_clk[] = { 479 F(37500000, P_GPLL0, 16, 0, 0), 480 F(60000000, P_GPLL0, 10, 0, 0), 481 F(75000000, P_GPLL0, 8, 0, 0), 482 F(85710000, P_GPLL0, 7, 0, 0), 483 F(100000000, P_GPLL0, 6, 0, 0), 484 F(150000000, P_GPLL0, 4, 0, 0), 485 F(160000000, P_MMPLL0, 5, 0, 0), 486 F(200000000, P_MMPLL0, 4, 0, 0), 487 F(228570000, P_MMPLL0, 3.5, 0, 0), 488 F(300000000, P_GPLL0, 2, 0, 0), 489 F(320000000, P_MMPLL0, 2.5, 0, 0), 490 { } 491}; 492 493static struct clk_rcg2 mdp_clk_src = { 494 .cmd_rcgr = 0x2040, 495 .hid_width = 5, 496 .parent_map = mmcc_xo_mmpll0_dsi_hdmi_gpll0_map, 497 .freq_tbl = ftbl_mdss_mdp_clk, 498 .clkr.hw.init = &(struct clk_init_data){ 499 .name = "mdp_clk_src", 500 .parent_names = mmcc_xo_mmpll0_dsi_hdmi_gpll0, 501 .num_parents = 6, 502 .ops = &clk_rcg2_ops, 503 }, 504}; 505 506static struct clk_rcg2 gfx3d_clk_src = { 507 .cmd_rcgr = 0x4000, 508 .hid_width = 5, 509 .parent_map = mmcc_xo_mmpll0_1_2_gpll0_map, 510 .clkr.hw.init = &(struct clk_init_data){ 511 .name = "gfx3d_clk_src", 512 .parent_names = mmcc_xo_mmpll0_1_2_gpll0, 513 .num_parents = 5, 514 .ops = &clk_rcg2_ops, 515 }, 516}; 517 518static struct freq_tbl ftbl_camss_jpeg_jpeg0_2_clk[] = { 519 F(75000000, P_GPLL0, 8, 0, 0), 520 F(133330000, P_GPLL0, 4.5, 0, 0), 521 F(200000000, P_GPLL0, 3, 0, 0), 522 F(228570000, P_MMPLL0, 3.5, 0, 0), 523 F(266670000, P_MMPLL0, 3, 0, 0), 524 F(320000000, P_MMPLL0, 2.5, 0, 0), 525 { } 526}; 527 528static struct clk_rcg2 jpeg0_clk_src = { 529 .cmd_rcgr = 0x3500, 530 .hid_width = 5, 531 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map, 532 .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk, 533 .clkr.hw.init = &(struct clk_init_data){ 534 .name = "jpeg0_clk_src", 535 .parent_names = mmcc_xo_mmpll0_1_4_gpll0, 536 .num_parents = 5, 537 .ops = &clk_rcg2_ops, 538 }, 539}; 540 541static struct clk_rcg2 jpeg1_clk_src = { 542 .cmd_rcgr = 0x3520, 543 .hid_width = 5, 544 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map, 545 .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk, 546 .clkr.hw.init = &(struct clk_init_data){ 547 .name = "jpeg1_clk_src", 548 .parent_names = mmcc_xo_mmpll0_1_4_gpll0, 549 .num_parents = 5, 550 .ops = &clk_rcg2_ops, 551 }, 552}; 553 554static struct clk_rcg2 jpeg2_clk_src = { 555 .cmd_rcgr = 0x3540, 556 .hid_width = 5, 557 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map, 558 .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk, 559 .clkr.hw.init = &(struct clk_init_data){ 560 .name = "jpeg2_clk_src", 561 .parent_names = mmcc_xo_mmpll0_1_4_gpll0, 562 .num_parents = 5, 563 .ops = &clk_rcg2_ops, 564 }, 565}; 566 567static struct clk_rcg2 pclk0_clk_src = { 568 .cmd_rcgr = 0x2000, 569 .mnd_width = 8, 570 .hid_width = 5, 571 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map, 572 .clkr.hw.init = &(struct clk_init_data){ 573 .name = "pclk0_clk_src", 574 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0, 575 .num_parents = 6, 576 .ops = &clk_pixel_ops, 577 .flags = CLK_SET_RATE_PARENT, 578 }, 579}; 580 581static struct clk_rcg2 pclk1_clk_src = { 582 .cmd_rcgr = 0x2020, 583 .mnd_width = 8, 584 .hid_width = 5, 585 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map, 586 .clkr.hw.init = &(struct clk_init_data){ 587 .name = "pclk1_clk_src", 588 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0, 589 .num_parents = 6, 590 .ops = &clk_pixel_ops, 591 .flags = CLK_SET_RATE_PARENT, 592 }, 593}; 594 595static struct freq_tbl ftbl_venus0_vcodec0_clk[] = { 596 F(50000000, P_GPLL0, 12, 0, 0), 597 F(100000000, P_GPLL0, 6, 0, 0), 598 F(133330000, P_GPLL0, 4.5, 0, 0), 599 F(200000000, P_MMPLL0, 4, 0, 0), 600 F(266670000, P_MMPLL0, 3, 0, 0), 601 F(465000000, P_MMPLL3, 2, 0, 0), 602 { } 603}; 604 605static struct clk_rcg2 vcodec0_clk_src = { 606 .cmd_rcgr = 0x1000, 607 .mnd_width = 8, 608 .hid_width = 5, 609 .parent_map = mmcc_xo_mmpll0_1_3_gpll0_map, 610 .freq_tbl = ftbl_venus0_vcodec0_clk, 611 .clkr.hw.init = &(struct clk_init_data){ 612 .name = "vcodec0_clk_src", 613 .parent_names = mmcc_xo_mmpll0_1_3_gpll0, 614 .num_parents = 5, 615 .ops = &clk_rcg2_ops, 616 }, 617}; 618 619static struct freq_tbl ftbl_avsync_vp_clk[] = { 620 F(150000000, P_GPLL0, 4, 0, 0), 621 F(320000000, P_MMPLL0, 2.5, 0, 0), 622 { } 623}; 624 625static struct clk_rcg2 vp_clk_src = { 626 .cmd_rcgr = 0x2430, 627 .hid_width = 5, 628 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, 629 .freq_tbl = ftbl_avsync_vp_clk, 630 .clkr.hw.init = &(struct clk_init_data){ 631 .name = "vp_clk_src", 632 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, 633 .num_parents = 4, 634 .ops = &clk_rcg2_ops, 635 }, 636}; 637 638static struct freq_tbl ftbl_camss_cci_cci_clk[] = { 639 F(19200000, P_XO, 1, 0, 0), 640 { } 641}; 642 643static struct clk_rcg2 cci_clk_src = { 644 .cmd_rcgr = 0x3300, 645 .mnd_width = 8, 646 .hid_width = 5, 647 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map, 648 .freq_tbl = ftbl_camss_cci_cci_clk, 649 .clkr.hw.init = &(struct clk_init_data){ 650 .name = "cci_clk_src", 651 .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0, 652 .num_parents = 6, 653 .ops = &clk_rcg2_ops, 654 }, 655}; 656 657static struct freq_tbl ftbl_camss_gp0_1_clk[] = { 658 F(10000, P_XO, 16, 1, 120), 659 F(24000, P_XO, 16, 1, 50), 660 F(6000000, P_GPLL0, 10, 1, 10), 661 F(12000000, P_GPLL0, 10, 1, 5), 662 F(13000000, P_GPLL0, 4, 13, 150), 663 F(24000000, P_GPLL0, 5, 1, 5), 664 { } 665}; 666 667static struct clk_rcg2 camss_gp0_clk_src = { 668 .cmd_rcgr = 0x3420, 669 .mnd_width = 8, 670 .hid_width = 5, 671 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_sleep_map, 672 .freq_tbl = ftbl_camss_gp0_1_clk, 673 .clkr.hw.init = &(struct clk_init_data){ 674 .name = "camss_gp0_clk_src", 675 .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0_sleep, 676 .num_parents = 7, 677 .ops = &clk_rcg2_ops, 678 }, 679}; 680 681static struct clk_rcg2 camss_gp1_clk_src = { 682 .cmd_rcgr = 0x3450, 683 .mnd_width = 8, 684 .hid_width = 5, 685 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_sleep_map, 686 .freq_tbl = ftbl_camss_gp0_1_clk, 687 .clkr.hw.init = &(struct clk_init_data){ 688 .name = "camss_gp1_clk_src", 689 .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0_sleep, 690 .num_parents = 7, 691 .ops = &clk_rcg2_ops, 692 }, 693}; 694 695static struct freq_tbl ftbl_camss_mclk0_3_clk[] = { 696 F(4800000, P_XO, 4, 0, 0), 697 F(6000000, P_GPLL0, 10, 1, 10), 698 F(8000000, P_GPLL0, 15, 1, 5), 699 F(9600000, P_XO, 2, 0, 0), 700 F(16000000, P_MMPLL0, 10, 1, 5), 701 F(19200000, P_XO, 1, 0, 0), 702 F(24000000, P_GPLL0, 5, 1, 5), 703 F(32000000, P_MMPLL0, 5, 1, 5), 704 F(48000000, P_GPLL0, 12.5, 0, 0), 705 F(64000000, P_MMPLL0, 12.5, 0, 0), 706 { } 707}; 708 709static struct clk_rcg2 mclk0_clk_src = { 710 .cmd_rcgr = 0x3360, 711 .mnd_width = 8, 712 .hid_width = 5, 713 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map, 714 .freq_tbl = ftbl_camss_mclk0_3_clk, 715 .clkr.hw.init = &(struct clk_init_data){ 716 .name = "mclk0_clk_src", 717 .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0, 718 .num_parents = 6, 719 .ops = &clk_rcg2_ops, 720 }, 721}; 722 723static struct clk_rcg2 mclk1_clk_src = { 724 .cmd_rcgr = 0x3390, 725 .mnd_width = 8, 726 .hid_width = 5, 727 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map, 728 .freq_tbl = ftbl_camss_mclk0_3_clk, 729 .clkr.hw.init = &(struct clk_init_data){ 730 .name = "mclk1_clk_src", 731 .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0, 732 .num_parents = 6, 733 .ops = &clk_rcg2_ops, 734 }, 735}; 736 737static struct clk_rcg2 mclk2_clk_src = { 738 .cmd_rcgr = 0x33c0, 739 .mnd_width = 8, 740 .hid_width = 5, 741 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map, 742 .freq_tbl = ftbl_camss_mclk0_3_clk, 743 .clkr.hw.init = &(struct clk_init_data){ 744 .name = "mclk2_clk_src", 745 .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0, 746 .num_parents = 6, 747 .ops = &clk_rcg2_ops, 748 }, 749}; 750 751static struct clk_rcg2 mclk3_clk_src = { 752 .cmd_rcgr = 0x33f0, 753 .mnd_width = 8, 754 .hid_width = 5, 755 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map, 756 .freq_tbl = ftbl_camss_mclk0_3_clk, 757 .clkr.hw.init = &(struct clk_init_data){ 758 .name = "mclk3_clk_src", 759 .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0, 760 .num_parents = 6, 761 .ops = &clk_rcg2_ops, 762 }, 763}; 764 765static struct freq_tbl ftbl_camss_phy0_2_csi0_2phytimer_clk[] = { 766 F(100000000, P_GPLL0, 6, 0, 0), 767 F(200000000, P_MMPLL0, 4, 0, 0), 768 { } 769}; 770 771static struct clk_rcg2 csi0phytimer_clk_src = { 772 .cmd_rcgr = 0x3000, 773 .hid_width = 5, 774 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map, 775 .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk, 776 .clkr.hw.init = &(struct clk_init_data){ 777 .name = "csi0phytimer_clk_src", 778 .parent_names = mmcc_xo_mmpll0_1_4_gpll0, 779 .num_parents = 5, 780 .ops = &clk_rcg2_ops, 781 }, 782}; 783 784static struct clk_rcg2 csi1phytimer_clk_src = { 785 .cmd_rcgr = 0x3030, 786 .hid_width = 5, 787 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map, 788 .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk, 789 .clkr.hw.init = &(struct clk_init_data){ 790 .name = "csi1phytimer_clk_src", 791 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, 792 .num_parents = 5, 793 .ops = &clk_rcg2_ops, 794 }, 795}; 796 797static struct clk_rcg2 csi2phytimer_clk_src = { 798 .cmd_rcgr = 0x3060, 799 .hid_width = 5, 800 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map, 801 .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk, 802 .clkr.hw.init = &(struct clk_init_data){ 803 .name = "csi2phytimer_clk_src", 804 .parent_names = mmcc_xo_mmpll0_1_4_gpll0, 805 .num_parents = 5, 806 .ops = &clk_rcg2_ops, 807 }, 808}; 809 810static struct freq_tbl ftbl_camss_vfe_cpp_clk[] = { 811 F(133330000, P_GPLL0, 4.5, 0, 0), 812 F(266670000, P_MMPLL0, 3, 0, 0), 813 F(320000000, P_MMPLL0, 2.5, 0, 0), 814 F(372000000, P_MMPLL4, 2.5, 0, 0), 815 F(465000000, P_MMPLL4, 2, 0, 0), 816 F(600000000, P_GPLL0, 1, 0, 0), 817 { } 818}; 819 820static struct clk_rcg2 cpp_clk_src = { 821 .cmd_rcgr = 0x3640, 822 .hid_width = 5, 823 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map, 824 .freq_tbl = ftbl_camss_vfe_cpp_clk, 825 .clkr.hw.init = &(struct clk_init_data){ 826 .name = "cpp_clk_src", 827 .parent_names = mmcc_xo_mmpll0_1_4_gpll0, 828 .num_parents = 5, 829 .ops = &clk_rcg2_ops, 830 }, 831}; 832 833static struct clk_rcg2 byte0_clk_src = { 834 .cmd_rcgr = 0x2120, 835 .hid_width = 5, 836 .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map, 837 .clkr.hw.init = &(struct clk_init_data){ 838 .name = "byte0_clk_src", 839 .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0, 840 .num_parents = 6, 841 .ops = &clk_byte2_ops, 842 .flags = CLK_SET_RATE_PARENT, 843 }, 844}; 845 846static struct clk_rcg2 byte1_clk_src = { 847 .cmd_rcgr = 0x2140, 848 .hid_width = 5, 849 .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map, 850 .clkr.hw.init = &(struct clk_init_data){ 851 .name = "byte1_clk_src", 852 .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0, 853 .num_parents = 6, 854 .ops = &clk_byte2_ops, 855 .flags = CLK_SET_RATE_PARENT, 856 }, 857}; 858 859static struct freq_tbl ftbl_mdss_edpaux_clk[] = { 860 F(19200000, P_XO, 1, 0, 0), 861 { } 862}; 863 864static struct clk_rcg2 edpaux_clk_src = { 865 .cmd_rcgr = 0x20e0, 866 .hid_width = 5, 867 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, 868 .freq_tbl = ftbl_mdss_edpaux_clk, 869 .clkr.hw.init = &(struct clk_init_data){ 870 .name = "edpaux_clk_src", 871 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, 872 .num_parents = 4, 873 .ops = &clk_rcg2_ops, 874 }, 875}; 876 877static struct freq_tbl ftbl_mdss_edplink_clk[] = { 878 F(135000000, P_EDPLINK, 2, 0, 0), 879 F(270000000, P_EDPLINK, 11, 0, 0), 880 { } 881}; 882 883static struct clk_rcg2 edplink_clk_src = { 884 .cmd_rcgr = 0x20c0, 885 .hid_width = 5, 886 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map, 887 .freq_tbl = ftbl_mdss_edplink_clk, 888 .clkr.hw.init = &(struct clk_init_data){ 889 .name = "edplink_clk_src", 890 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0, 891 .num_parents = 6, 892 .ops = &clk_rcg2_ops, 893 .flags = CLK_SET_RATE_PARENT, 894 }, 895}; 896 897static struct freq_tbl edp_pixel_freq_tbl[] = { 898 { .src = P_EDPVCO }, 899 { } 900}; 901 902static struct clk_rcg2 edppixel_clk_src = { 903 .cmd_rcgr = 0x20a0, 904 .mnd_width = 8, 905 .hid_width = 5, 906 .parent_map = mmcc_xo_dsi_hdmi_edp_map, 907 .freq_tbl = edp_pixel_freq_tbl, 908 .clkr.hw.init = &(struct clk_init_data){ 909 .name = "edppixel_clk_src", 910 .parent_names = mmcc_xo_dsi_hdmi_edp, 911 .num_parents = 6, 912 .ops = &clk_edp_pixel_ops, 913 }, 914}; 915 916static struct freq_tbl ftbl_mdss_esc0_1_clk[] = { 917 F(19200000, P_XO, 1, 0, 0), 918 { } 919}; 920 921static struct clk_rcg2 esc0_clk_src = { 922 .cmd_rcgr = 0x2160, 923 .hid_width = 5, 924 .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map, 925 .freq_tbl = ftbl_mdss_esc0_1_clk, 926 .clkr.hw.init = &(struct clk_init_data){ 927 .name = "esc0_clk_src", 928 .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0, 929 .num_parents = 6, 930 .ops = &clk_rcg2_ops, 931 }, 932}; 933 934static struct clk_rcg2 esc1_clk_src = { 935 .cmd_rcgr = 0x2180, 936 .hid_width = 5, 937 .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map, 938 .freq_tbl = ftbl_mdss_esc0_1_clk, 939 .clkr.hw.init = &(struct clk_init_data){ 940 .name = "esc1_clk_src", 941 .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0, 942 .num_parents = 6, 943 .ops = &clk_rcg2_ops, 944 }, 945}; 946 947static struct freq_tbl extpclk_freq_tbl[] = { 948 { .src = P_HDMIPLL }, 949 { } 950}; 951 952static struct clk_rcg2 extpclk_clk_src = { 953 .cmd_rcgr = 0x2060, 954 .hid_width = 5, 955 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map, 956 .freq_tbl = extpclk_freq_tbl, 957 .clkr.hw.init = &(struct clk_init_data){ 958 .name = "extpclk_clk_src", 959 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0, 960 .num_parents = 6, 961 .ops = &clk_byte_ops, 962 .flags = CLK_SET_RATE_PARENT, 963 }, 964}; 965 966static struct freq_tbl ftbl_mdss_hdmi_clk[] = { 967 F(19200000, P_XO, 1, 0, 0), 968 { } 969}; 970 971static struct clk_rcg2 hdmi_clk_src = { 972 .cmd_rcgr = 0x2100, 973 .hid_width = 5, 974 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, 975 .freq_tbl = ftbl_mdss_hdmi_clk, 976 .clkr.hw.init = &(struct clk_init_data){ 977 .name = "hdmi_clk_src", 978 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, 979 .num_parents = 4, 980 .ops = &clk_rcg2_ops, 981 }, 982}; 983 984static struct freq_tbl ftbl_mdss_vsync_clk[] = { 985 F(19200000, P_XO, 1, 0, 0), 986 { } 987}; 988 989static struct clk_rcg2 vsync_clk_src = { 990 .cmd_rcgr = 0x2080, 991 .hid_width = 5, 992 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, 993 .freq_tbl = ftbl_mdss_vsync_clk, 994 .clkr.hw.init = &(struct clk_init_data){ 995 .name = "vsync_clk_src", 996 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, 997 .num_parents = 4, 998 .ops = &clk_rcg2_ops, 999 }, 1000}; 1001 1002static struct freq_tbl ftbl_mmss_rbcpr_clk[] = { 1003 F(50000000, P_GPLL0, 12, 0, 0), 1004 { } 1005}; 1006 1007static struct clk_rcg2 rbcpr_clk_src = { 1008 .cmd_rcgr = 0x4060, 1009 .hid_width = 5, 1010 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, 1011 .freq_tbl = ftbl_mmss_rbcpr_clk, 1012 .clkr.hw.init = &(struct clk_init_data){ 1013 .name = "rbcpr_clk_src", 1014 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, 1015 .num_parents = 4, 1016 .ops = &clk_rcg2_ops, 1017 }, 1018}; 1019 1020static struct freq_tbl ftbl_oxili_rbbmtimer_clk[] = { 1021 F(19200000, P_XO, 1, 0, 0), 1022 { } 1023}; 1024 1025static struct clk_rcg2 rbbmtimer_clk_src = { 1026 .cmd_rcgr = 0x4090, 1027 .hid_width = 5, 1028 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, 1029 .freq_tbl = ftbl_oxili_rbbmtimer_clk, 1030 .clkr.hw.init = &(struct clk_init_data){ 1031 .name = "rbbmtimer_clk_src", 1032 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, 1033 .num_parents = 4, 1034 .ops = &clk_rcg2_ops, 1035 }, 1036}; 1037 1038static struct freq_tbl ftbl_vpu_maple_clk[] = { 1039 F(50000000, P_GPLL0, 12, 0, 0), 1040 F(100000000, P_GPLL0, 6, 0, 0), 1041 F(133330000, P_GPLL0, 4.5, 0, 0), 1042 F(200000000, P_MMPLL0, 4, 0, 0), 1043 F(266670000, P_MMPLL0, 3, 0, 0), 1044 F(465000000, P_MMPLL3, 2, 0, 0), 1045 { } 1046}; 1047 1048static struct clk_rcg2 maple_clk_src = { 1049 .cmd_rcgr = 0x1320, 1050 .hid_width = 5, 1051 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, 1052 .freq_tbl = ftbl_vpu_maple_clk, 1053 .clkr.hw.init = &(struct clk_init_data){ 1054 .name = "maple_clk_src", 1055 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, 1056 .num_parents = 4, 1057 .ops = &clk_rcg2_ops, 1058 }, 1059}; 1060 1061static struct freq_tbl ftbl_vpu_vdp_clk[] = { 1062 F(50000000, P_GPLL0, 12, 0, 0), 1063 F(100000000, P_GPLL0, 6, 0, 0), 1064 F(200000000, P_MMPLL0, 4, 0, 0), 1065 F(320000000, P_MMPLL0, 2.5, 0, 0), 1066 F(400000000, P_MMPLL0, 2, 0, 0), 1067 { } 1068}; 1069 1070static struct clk_rcg2 vdp_clk_src = { 1071 .cmd_rcgr = 0x1300, 1072 .hid_width = 5, 1073 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, 1074 .freq_tbl = ftbl_vpu_vdp_clk, 1075 .clkr.hw.init = &(struct clk_init_data){ 1076 .name = "vdp_clk_src", 1077 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, 1078 .num_parents = 4, 1079 .ops = &clk_rcg2_ops, 1080 }, 1081}; 1082 1083static struct freq_tbl ftbl_vpu_bus_clk[] = { 1084 F(40000000, P_GPLL0, 15, 0, 0), 1085 F(80000000, P_MMPLL0, 10, 0, 0), 1086 { } 1087}; 1088 1089static struct clk_rcg2 vpu_bus_clk_src = { 1090 .cmd_rcgr = 0x1340, 1091 .hid_width = 5, 1092 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, 1093 .freq_tbl = ftbl_vpu_bus_clk, 1094 .clkr.hw.init = &(struct clk_init_data){ 1095 .name = "vpu_bus_clk_src", 1096 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, 1097 .num_parents = 4, 1098 .ops = &clk_rcg2_ops, 1099 }, 1100}; 1101 1102static struct clk_branch mmss_cxo_clk = { 1103 .halt_reg = 0x5104, 1104 .clkr = { 1105 .enable_reg = 0x5104, 1106 .enable_mask = BIT(0), 1107 .hw.init = &(struct clk_init_data){ 1108 .name = "mmss_cxo_clk", 1109 .parent_names = (const char *[]){ "xo" }, 1110 .num_parents = 1, 1111 .flags = CLK_SET_RATE_PARENT, 1112 .ops = &clk_branch2_ops, 1113 }, 1114 }, 1115}; 1116 1117static struct clk_branch mmss_sleepclk_clk = { 1118 .halt_reg = 0x5100, 1119 .clkr = { 1120 .enable_reg = 0x5100, 1121 .enable_mask = BIT(0), 1122 .hw.init = &(struct clk_init_data){ 1123 .name = "mmss_sleepclk_clk", 1124 .parent_names = (const char *[]){ 1125 "sleep_clk_src", 1126 }, 1127 .num_parents = 1, 1128 .flags = CLK_SET_RATE_PARENT, 1129 .ops = &clk_branch2_ops, 1130 }, 1131 }, 1132}; 1133 1134static struct clk_branch avsync_ahb_clk = { 1135 .halt_reg = 0x2414, 1136 .clkr = { 1137 .enable_reg = 0x2414, 1138 .enable_mask = BIT(0), 1139 .hw.init = &(struct clk_init_data){ 1140 .name = "avsync_ahb_clk", 1141 .parent_names = (const char *[]){ 1142 "mmss_ahb_clk_src", 1143 }, 1144 .num_parents = 1, 1145 .flags = CLK_SET_RATE_PARENT, 1146 .ops = &clk_branch2_ops, 1147 }, 1148 }, 1149}; 1150 1151static struct clk_branch avsync_edppixel_clk = { 1152 .halt_reg = 0x2418, 1153 .clkr = { 1154 .enable_reg = 0x2418, 1155 .enable_mask = BIT(0), 1156 .hw.init = &(struct clk_init_data){ 1157 .name = "avsync_edppixel_clk", 1158 .parent_names = (const char *[]){ 1159 "edppixel_clk_src", 1160 }, 1161 .num_parents = 1, 1162 .flags = CLK_SET_RATE_PARENT, 1163 .ops = &clk_branch2_ops, 1164 }, 1165 }, 1166}; 1167 1168static struct clk_branch avsync_extpclk_clk = { 1169 .halt_reg = 0x2410, 1170 .clkr = { 1171 .enable_reg = 0x2410, 1172 .enable_mask = BIT(0), 1173 .hw.init = &(struct clk_init_data){ 1174 .name = "avsync_extpclk_clk", 1175 .parent_names = (const char *[]){ 1176 "extpclk_clk_src", 1177 }, 1178 .num_parents = 1, 1179 .flags = CLK_SET_RATE_PARENT, 1180 .ops = &clk_branch2_ops, 1181 }, 1182 }, 1183}; 1184 1185static struct clk_branch avsync_pclk0_clk = { 1186 .halt_reg = 0x241c, 1187 .clkr = { 1188 .enable_reg = 0x241c, 1189 .enable_mask = BIT(0), 1190 .hw.init = &(struct clk_init_data){ 1191 .name = "avsync_pclk0_clk", 1192 .parent_names = (const char *[]){ 1193 "pclk0_clk_src", 1194 }, 1195 .num_parents = 1, 1196 .flags = CLK_SET_RATE_PARENT, 1197 .ops = &clk_branch2_ops, 1198 }, 1199 }, 1200}; 1201 1202static struct clk_branch avsync_pclk1_clk = { 1203 .halt_reg = 0x2420, 1204 .clkr = { 1205 .enable_reg = 0x2420, 1206 .enable_mask = BIT(0), 1207 .hw.init = &(struct clk_init_data){ 1208 .name = "avsync_pclk1_clk", 1209 .parent_names = (const char *[]){ 1210 "pclk1_clk_src", 1211 }, 1212 .num_parents = 1, 1213 .flags = CLK_SET_RATE_PARENT, 1214 .ops = &clk_branch2_ops, 1215 }, 1216 }, 1217}; 1218 1219static struct clk_branch avsync_vp_clk = { 1220 .halt_reg = 0x2404, 1221 .clkr = { 1222 .enable_reg = 0x2404, 1223 .enable_mask = BIT(0), 1224 .hw.init = &(struct clk_init_data){ 1225 .name = "avsync_vp_clk", 1226 .parent_names = (const char *[]){ 1227 "vp_clk_src", 1228 }, 1229 .num_parents = 1, 1230 .flags = CLK_SET_RATE_PARENT, 1231 .ops = &clk_branch2_ops, 1232 }, 1233 }, 1234}; 1235 1236static struct clk_branch camss_ahb_clk = { 1237 .halt_reg = 0x348c, 1238 .clkr = { 1239 .enable_reg = 0x348c, 1240 .enable_mask = BIT(0), 1241 .hw.init = &(struct clk_init_data){ 1242 .name = "camss_ahb_clk", 1243 .parent_names = (const char *[]){ 1244 "mmss_ahb_clk_src", 1245 }, 1246 .num_parents = 1, 1247 .flags = CLK_SET_RATE_PARENT, 1248 .ops = &clk_branch2_ops, 1249 }, 1250 }, 1251}; 1252 1253static struct clk_branch camss_cci_cci_ahb_clk = { 1254 .halt_reg = 0x3348, 1255 .clkr = { 1256 .enable_reg = 0x3348, 1257 .enable_mask = BIT(0), 1258 .hw.init = &(struct clk_init_data){ 1259 .name = "camss_cci_cci_ahb_clk", 1260 .parent_names = (const char *[]){ 1261 "mmss_ahb_clk_src", 1262 }, 1263 .num_parents = 1, 1264 .ops = &clk_branch2_ops, 1265 }, 1266 }, 1267}; 1268 1269static struct clk_branch camss_cci_cci_clk = { 1270 .halt_reg = 0x3344, 1271 .clkr = { 1272 .enable_reg = 0x3344, 1273 .enable_mask = BIT(0), 1274 .hw.init = &(struct clk_init_data){ 1275 .name = "camss_cci_cci_clk", 1276 .parent_names = (const char *[]){ 1277 "cci_clk_src", 1278 }, 1279 .num_parents = 1, 1280 .flags = CLK_SET_RATE_PARENT, 1281 .ops = &clk_branch2_ops, 1282 }, 1283 }, 1284}; 1285 1286static struct clk_branch camss_csi0_ahb_clk = { 1287 .halt_reg = 0x30bc, 1288 .clkr = { 1289 .enable_reg = 0x30bc, 1290 .enable_mask = BIT(0), 1291 .hw.init = &(struct clk_init_data){ 1292 .name = "camss_csi0_ahb_clk", 1293 .parent_names = (const char *[]){ 1294 "mmss_ahb_clk_src", 1295 }, 1296 .num_parents = 1, 1297 .ops = &clk_branch2_ops, 1298 }, 1299 }, 1300}; 1301 1302static struct clk_branch camss_csi0_clk = { 1303 .halt_reg = 0x30b4, 1304 .clkr = { 1305 .enable_reg = 0x30b4, 1306 .enable_mask = BIT(0), 1307 .hw.init = &(struct clk_init_data){ 1308 .name = "camss_csi0_clk", 1309 .parent_names = (const char *[]){ 1310 "csi0_clk_src", 1311 }, 1312 .num_parents = 1, 1313 .flags = CLK_SET_RATE_PARENT, 1314 .ops = &clk_branch2_ops, 1315 }, 1316 }, 1317}; 1318 1319static struct clk_branch camss_csi0phy_clk = { 1320 .halt_reg = 0x30c4, 1321 .clkr = { 1322 .enable_reg = 0x30c4, 1323 .enable_mask = BIT(0), 1324 .hw.init = &(struct clk_init_data){ 1325 .name = "camss_csi0phy_clk", 1326 .parent_names = (const char *[]){ 1327 "csi0_clk_src", 1328 }, 1329 .num_parents = 1, 1330 .flags = CLK_SET_RATE_PARENT, 1331 .ops = &clk_branch2_ops, 1332 }, 1333 }, 1334}; 1335 1336static struct clk_branch camss_csi0pix_clk = { 1337 .halt_reg = 0x30e4, 1338 .clkr = { 1339 .enable_reg = 0x30e4, 1340 .enable_mask = BIT(0), 1341 .hw.init = &(struct clk_init_data){ 1342 .name = "camss_csi0pix_clk", 1343 .parent_names = (const char *[]){ 1344 "csi0_clk_src", 1345 }, 1346 .num_parents = 1, 1347 .flags = CLK_SET_RATE_PARENT, 1348 .ops = &clk_branch2_ops, 1349 }, 1350 }, 1351}; 1352 1353static struct clk_branch camss_csi0rdi_clk = { 1354 .halt_reg = 0x30d4, 1355 .clkr = { 1356 .enable_reg = 0x30d4, 1357 .enable_mask = BIT(0), 1358 .hw.init = &(struct clk_init_data){ 1359 .name = "camss_csi0rdi_clk", 1360 .parent_names = (const char *[]){ 1361 "csi0_clk_src", 1362 }, 1363 .num_parents = 1, 1364 .flags = CLK_SET_RATE_PARENT, 1365 .ops = &clk_branch2_ops, 1366 }, 1367 }, 1368}; 1369 1370static struct clk_branch camss_csi1_ahb_clk = { 1371 .halt_reg = 0x3128, 1372 .clkr = { 1373 .enable_reg = 0x3128, 1374 .enable_mask = BIT(0), 1375 .hw.init = &(struct clk_init_data){ 1376 .name = "camss_csi1_ahb_clk", 1377 .parent_names = (const char *[]){ 1378 "mmss_ahb_clk_src", 1379 }, 1380 .num_parents = 1, 1381 .flags = CLK_SET_RATE_PARENT, 1382 .ops = &clk_branch2_ops, 1383 }, 1384 }, 1385}; 1386 1387static struct clk_branch camss_csi1_clk = { 1388 .halt_reg = 0x3124, 1389 .clkr = { 1390 .enable_reg = 0x3124, 1391 .enable_mask = BIT(0), 1392 .hw.init = &(struct clk_init_data){ 1393 .name = "camss_csi1_clk", 1394 .parent_names = (const char *[]){ 1395 "csi1_clk_src", 1396 }, 1397 .num_parents = 1, 1398 .flags = CLK_SET_RATE_PARENT, 1399 .ops = &clk_branch2_ops, 1400 }, 1401 }, 1402}; 1403 1404static struct clk_branch camss_csi1phy_clk = { 1405 .halt_reg = 0x3134, 1406 .clkr = { 1407 .enable_reg = 0x3134, 1408 .enable_mask = BIT(0), 1409 .hw.init = &(struct clk_init_data){ 1410 .name = "camss_csi1phy_clk", 1411 .parent_names = (const char *[]){ 1412 "csi1_clk_src", 1413 }, 1414 .num_parents = 1, 1415 .flags = CLK_SET_RATE_PARENT, 1416 .ops = &clk_branch2_ops, 1417 }, 1418 }, 1419}; 1420 1421static struct clk_branch camss_csi1pix_clk = { 1422 .halt_reg = 0x3154, 1423 .clkr = { 1424 .enable_reg = 0x3154, 1425 .enable_mask = BIT(0), 1426 .hw.init = &(struct clk_init_data){ 1427 .name = "camss_csi1pix_clk", 1428 .parent_names = (const char *[]){ 1429 "csi1_clk_src", 1430 }, 1431 .num_parents = 1, 1432 .flags = CLK_SET_RATE_PARENT, 1433 .ops = &clk_branch2_ops, 1434 }, 1435 }, 1436}; 1437 1438static struct clk_branch camss_csi1rdi_clk = { 1439 .halt_reg = 0x3144, 1440 .clkr = { 1441 .enable_reg = 0x3144, 1442 .enable_mask = BIT(0), 1443 .hw.init = &(struct clk_init_data){ 1444 .name = "camss_csi1rdi_clk", 1445 .parent_names = (const char *[]){ 1446 "csi1_clk_src", 1447 }, 1448 .num_parents = 1, 1449 .flags = CLK_SET_RATE_PARENT, 1450 .ops = &clk_branch2_ops, 1451 }, 1452 }, 1453}; 1454 1455static struct clk_branch camss_csi2_ahb_clk = { 1456 .halt_reg = 0x3188, 1457 .clkr = { 1458 .enable_reg = 0x3188, 1459 .enable_mask = BIT(0), 1460 .hw.init = &(struct clk_init_data){ 1461 .name = "camss_csi2_ahb_clk", 1462 .parent_names = (const char *[]){ 1463 "mmss_ahb_clk_src", 1464 }, 1465 .num_parents = 1, 1466 .ops = &clk_branch2_ops, 1467 }, 1468 }, 1469}; 1470 1471static struct clk_branch camss_csi2_clk = { 1472 .halt_reg = 0x3184, 1473 .clkr = { 1474 .enable_reg = 0x3184, 1475 .enable_mask = BIT(0), 1476 .hw.init = &(struct clk_init_data){ 1477 .name = "camss_csi2_clk", 1478 .parent_names = (const char *[]){ 1479 "csi2_clk_src", 1480 }, 1481 .num_parents = 1, 1482 .flags = CLK_SET_RATE_PARENT, 1483 .ops = &clk_branch2_ops, 1484 }, 1485 }, 1486}; 1487 1488static struct clk_branch camss_csi2phy_clk = { 1489 .halt_reg = 0x3194, 1490 .clkr = { 1491 .enable_reg = 0x3194, 1492 .enable_mask = BIT(0), 1493 .hw.init = &(struct clk_init_data){ 1494 .name = "camss_csi2phy_clk", 1495 .parent_names = (const char *[]){ 1496 "csi2_clk_src", 1497 }, 1498 .num_parents = 1, 1499 .flags = CLK_SET_RATE_PARENT, 1500 .ops = &clk_branch2_ops, 1501 }, 1502 }, 1503}; 1504 1505static struct clk_branch camss_csi2pix_clk = { 1506 .halt_reg = 0x31b4, 1507 .clkr = { 1508 .enable_reg = 0x31b4, 1509 .enable_mask = BIT(0), 1510 .hw.init = &(struct clk_init_data){ 1511 .name = "camss_csi2pix_clk", 1512 .parent_names = (const char *[]){ 1513 "csi2_clk_src", 1514 }, 1515 .num_parents = 1, 1516 .flags = CLK_SET_RATE_PARENT, 1517 .ops = &clk_branch2_ops, 1518 }, 1519 }, 1520}; 1521 1522static struct clk_branch camss_csi2rdi_clk = { 1523 .halt_reg = 0x31a4, 1524 .clkr = { 1525 .enable_reg = 0x31a4, 1526 .enable_mask = BIT(0), 1527 .hw.init = &(struct clk_init_data){ 1528 .name = "camss_csi2rdi_clk", 1529 .parent_names = (const char *[]){ 1530 "csi2_clk_src", 1531 }, 1532 .num_parents = 1, 1533 .flags = CLK_SET_RATE_PARENT, 1534 .ops = &clk_branch2_ops, 1535 }, 1536 }, 1537}; 1538 1539static struct clk_branch camss_csi3_ahb_clk = { 1540 .halt_reg = 0x31e8, 1541 .clkr = { 1542 .enable_reg = 0x31e8, 1543 .enable_mask = BIT(0), 1544 .hw.init = &(struct clk_init_data){ 1545 .name = "camss_csi3_ahb_clk", 1546 .parent_names = (const char *[]){ 1547 "mmss_ahb_clk_src", 1548 }, 1549 .num_parents = 1, 1550 .ops = &clk_branch2_ops, 1551 }, 1552 }, 1553}; 1554 1555static struct clk_branch camss_csi3_clk = { 1556 .halt_reg = 0x31e4, 1557 .clkr = { 1558 .enable_reg = 0x31e4, 1559 .enable_mask = BIT(0), 1560 .hw.init = &(struct clk_init_data){ 1561 .name = "camss_csi3_clk", 1562 .parent_names = (const char *[]){ 1563 "csi3_clk_src", 1564 }, 1565 .num_parents = 1, 1566 .flags = CLK_SET_RATE_PARENT, 1567 .ops = &clk_branch2_ops, 1568 }, 1569 }, 1570}; 1571 1572static struct clk_branch camss_csi3phy_clk = { 1573 .halt_reg = 0x31f4, 1574 .clkr = { 1575 .enable_reg = 0x31f4, 1576 .enable_mask = BIT(0), 1577 .hw.init = &(struct clk_init_data){ 1578 .name = "camss_csi3phy_clk", 1579 .parent_names = (const char *[]){ 1580 "csi3_clk_src", 1581 }, 1582 .num_parents = 1, 1583 .flags = CLK_SET_RATE_PARENT, 1584 .ops = &clk_branch2_ops, 1585 }, 1586 }, 1587}; 1588 1589static struct clk_branch camss_csi3pix_clk = { 1590 .halt_reg = 0x3214, 1591 .clkr = { 1592 .enable_reg = 0x3214, 1593 .enable_mask = BIT(0), 1594 .hw.init = &(struct clk_init_data){ 1595 .name = "camss_csi3pix_clk", 1596 .parent_names = (const char *[]){ 1597 "csi3_clk_src", 1598 }, 1599 .num_parents = 1, 1600 .flags = CLK_SET_RATE_PARENT, 1601 .ops = &clk_branch2_ops, 1602 }, 1603 }, 1604}; 1605 1606static struct clk_branch camss_csi3rdi_clk = { 1607 .halt_reg = 0x3204, 1608 .clkr = { 1609 .enable_reg = 0x3204, 1610 .enable_mask = BIT(0), 1611 .hw.init = &(struct clk_init_data){ 1612 .name = "camss_csi3rdi_clk", 1613 .parent_names = (const char *[]){ 1614 "csi3_clk_src", 1615 }, 1616 .num_parents = 1, 1617 .flags = CLK_SET_RATE_PARENT, 1618 .ops = &clk_branch2_ops, 1619 }, 1620 }, 1621}; 1622 1623static struct clk_branch camss_csi_vfe0_clk = { 1624 .halt_reg = 0x3704, 1625 .clkr = { 1626 .enable_reg = 0x3704, 1627 .enable_mask = BIT(0), 1628 .hw.init = &(struct clk_init_data){ 1629 .name = "camss_csi_vfe0_clk", 1630 .parent_names = (const char *[]){ 1631 "vfe0_clk_src", 1632 }, 1633 .num_parents = 1, 1634 .flags = CLK_SET_RATE_PARENT, 1635 .ops = &clk_branch2_ops, 1636 }, 1637 }, 1638}; 1639 1640static struct clk_branch camss_csi_vfe1_clk = { 1641 .halt_reg = 0x3714, 1642 .clkr = { 1643 .enable_reg = 0x3714, 1644 .enable_mask = BIT(0), 1645 .hw.init = &(struct clk_init_data){ 1646 .name = "camss_csi_vfe1_clk", 1647 .parent_names = (const char *[]){ 1648 "vfe1_clk_src", 1649 }, 1650 .num_parents = 1, 1651 .flags = CLK_SET_RATE_PARENT, 1652 .ops = &clk_branch2_ops, 1653 }, 1654 }, 1655}; 1656 1657static struct clk_branch camss_gp0_clk = { 1658 .halt_reg = 0x3444, 1659 .clkr = { 1660 .enable_reg = 0x3444, 1661 .enable_mask = BIT(0), 1662 .hw.init = &(struct clk_init_data){ 1663 .name = "camss_gp0_clk", 1664 .parent_names = (const char *[]){ 1665 "camss_gp0_clk_src", 1666 }, 1667 .num_parents = 1, 1668 .flags = CLK_SET_RATE_PARENT, 1669 .ops = &clk_branch2_ops, 1670 }, 1671 }, 1672}; 1673 1674static struct clk_branch camss_gp1_clk = { 1675 .halt_reg = 0x3474, 1676 .clkr = { 1677 .enable_reg = 0x3474, 1678 .enable_mask = BIT(0), 1679 .hw.init = &(struct clk_init_data){ 1680 .name = "camss_gp1_clk", 1681 .parent_names = (const char *[]){ 1682 "camss_gp1_clk_src", 1683 }, 1684 .num_parents = 1, 1685 .flags = CLK_SET_RATE_PARENT, 1686 .ops = &clk_branch2_ops, 1687 }, 1688 }, 1689}; 1690 1691static struct clk_branch camss_ispif_ahb_clk = { 1692 .halt_reg = 0x3224, 1693 .clkr = { 1694 .enable_reg = 0x3224, 1695 .enable_mask = BIT(0), 1696 .hw.init = &(struct clk_init_data){ 1697 .name = "camss_ispif_ahb_clk", 1698 .parent_names = (const char *[]){ 1699 "mmss_ahb_clk_src", 1700 }, 1701 .num_parents = 1, 1702 .flags = CLK_SET_RATE_PARENT, 1703 .ops = &clk_branch2_ops, 1704 }, 1705 }, 1706}; 1707 1708static struct clk_branch camss_jpeg_jpeg0_clk = { 1709 .halt_reg = 0x35a8, 1710 .clkr = { 1711 .enable_reg = 0x35a8, 1712 .enable_mask = BIT(0), 1713 .hw.init = &(struct clk_init_data){ 1714 .name = "camss_jpeg_jpeg0_clk", 1715 .parent_names = (const char *[]){ 1716 "jpeg0_clk_src", 1717 }, 1718 .num_parents = 1, 1719 .flags = CLK_SET_RATE_PARENT, 1720 .ops = &clk_branch2_ops, 1721 }, 1722 }, 1723}; 1724 1725static struct clk_branch camss_jpeg_jpeg1_clk = { 1726 .halt_reg = 0x35ac, 1727 .clkr = { 1728 .enable_reg = 0x35ac, 1729 .enable_mask = BIT(0), 1730 .hw.init = &(struct clk_init_data){ 1731 .name = "camss_jpeg_jpeg1_clk", 1732 .parent_names = (const char *[]){ 1733 "jpeg1_clk_src", 1734 }, 1735 .num_parents = 1, 1736 .flags = CLK_SET_RATE_PARENT, 1737 .ops = &clk_branch2_ops, 1738 }, 1739 }, 1740}; 1741 1742static struct clk_branch camss_jpeg_jpeg2_clk = { 1743 .halt_reg = 0x35b0, 1744 .clkr = { 1745 .enable_reg = 0x35b0, 1746 .enable_mask = BIT(0), 1747 .hw.init = &(struct clk_init_data){ 1748 .name = "camss_jpeg_jpeg2_clk", 1749 .parent_names = (const char *[]){ 1750 "jpeg2_clk_src", 1751 }, 1752 .num_parents = 1, 1753 .flags = CLK_SET_RATE_PARENT, 1754 .ops = &clk_branch2_ops, 1755 }, 1756 }, 1757}; 1758 1759static struct clk_branch camss_jpeg_jpeg_ahb_clk = { 1760 .halt_reg = 0x35b4, 1761 .clkr = { 1762 .enable_reg = 0x35b4, 1763 .enable_mask = BIT(0), 1764 .hw.init = &(struct clk_init_data){ 1765 .name = "camss_jpeg_jpeg_ahb_clk", 1766 .parent_names = (const char *[]){ 1767 "mmss_ahb_clk_src", 1768 }, 1769 .num_parents = 1, 1770 .ops = &clk_branch2_ops, 1771 }, 1772 }, 1773}; 1774 1775static struct clk_branch camss_jpeg_jpeg_axi_clk = { 1776 .halt_reg = 0x35b8, 1777 .clkr = { 1778 .enable_reg = 0x35b8, 1779 .enable_mask = BIT(0), 1780 .hw.init = &(struct clk_init_data){ 1781 .name = "camss_jpeg_jpeg_axi_clk", 1782 .parent_names = (const char *[]){ 1783 "mmss_axi_clk_src", 1784 }, 1785 .num_parents = 1, 1786 .ops = &clk_branch2_ops, 1787 }, 1788 }, 1789}; 1790 1791static struct clk_branch camss_mclk0_clk = { 1792 .halt_reg = 0x3384, 1793 .clkr = { 1794 .enable_reg = 0x3384, 1795 .enable_mask = BIT(0), 1796 .hw.init = &(struct clk_init_data){ 1797 .name = "camss_mclk0_clk", 1798 .parent_names = (const char *[]){ 1799 "mclk0_clk_src", 1800 }, 1801 .num_parents = 1, 1802 .flags = CLK_SET_RATE_PARENT, 1803 .ops = &clk_branch2_ops, 1804 }, 1805 }, 1806}; 1807 1808static struct clk_branch camss_mclk1_clk = { 1809 .halt_reg = 0x33b4, 1810 .clkr = { 1811 .enable_reg = 0x33b4, 1812 .enable_mask = BIT(0), 1813 .hw.init = &(struct clk_init_data){ 1814 .name = "camss_mclk1_clk", 1815 .parent_names = (const char *[]){ 1816 "mclk1_clk_src", 1817 }, 1818 .num_parents = 1, 1819 .flags = CLK_SET_RATE_PARENT, 1820 .ops = &clk_branch2_ops, 1821 }, 1822 }, 1823}; 1824 1825static struct clk_branch camss_mclk2_clk = { 1826 .halt_reg = 0x33e4, 1827 .clkr = { 1828 .enable_reg = 0x33e4, 1829 .enable_mask = BIT(0), 1830 .hw.init = &(struct clk_init_data){ 1831 .name = "camss_mclk2_clk", 1832 .parent_names = (const char *[]){ 1833 "mclk2_clk_src", 1834 }, 1835 .num_parents = 1, 1836 .flags = CLK_SET_RATE_PARENT, 1837 .ops = &clk_branch2_ops, 1838 }, 1839 }, 1840}; 1841 1842static struct clk_branch camss_mclk3_clk = { 1843 .halt_reg = 0x3414, 1844 .clkr = { 1845 .enable_reg = 0x3414, 1846 .enable_mask = BIT(0), 1847 .hw.init = &(struct clk_init_data){ 1848 .name = "camss_mclk3_clk", 1849 .parent_names = (const char *[]){ 1850 "mclk3_clk_src", 1851 }, 1852 .num_parents = 1, 1853 .flags = CLK_SET_RATE_PARENT, 1854 .ops = &clk_branch2_ops, 1855 }, 1856 }, 1857}; 1858 1859static struct clk_branch camss_micro_ahb_clk = { 1860 .halt_reg = 0x3494, 1861 .clkr = { 1862 .enable_reg = 0x3494, 1863 .enable_mask = BIT(0), 1864 .hw.init = &(struct clk_init_data){ 1865 .name = "camss_micro_ahb_clk", 1866 .parent_names = (const char *[]){ 1867 "mmss_ahb_clk_src", 1868 }, 1869 .num_parents = 1, 1870 .ops = &clk_branch2_ops, 1871 }, 1872 }, 1873}; 1874 1875static struct clk_branch camss_phy0_csi0phytimer_clk = { 1876 .halt_reg = 0x3024, 1877 .clkr = { 1878 .enable_reg = 0x3024, 1879 .enable_mask = BIT(0), 1880 .hw.init = &(struct clk_init_data){ 1881 .name = "camss_phy0_csi0phytimer_clk", 1882 .parent_names = (const char *[]){ 1883 "csi0phytimer_clk_src", 1884 }, 1885 .num_parents = 1, 1886 .flags = CLK_SET_RATE_PARENT, 1887 .ops = &clk_branch2_ops, 1888 }, 1889 }, 1890}; 1891 1892static struct clk_branch camss_phy1_csi1phytimer_clk = { 1893 .halt_reg = 0x3054, 1894 .clkr = { 1895 .enable_reg = 0x3054, 1896 .enable_mask = BIT(0), 1897 .hw.init = &(struct clk_init_data){ 1898 .name = "camss_phy1_csi1phytimer_clk", 1899 .parent_names = (const char *[]){ 1900 "csi1phytimer_clk_src", 1901 }, 1902 .num_parents = 1, 1903 .flags = CLK_SET_RATE_PARENT, 1904 .ops = &clk_branch2_ops, 1905 }, 1906 }, 1907}; 1908 1909static struct clk_branch camss_phy2_csi2phytimer_clk = { 1910 .halt_reg = 0x3084, 1911 .clkr = { 1912 .enable_reg = 0x3084, 1913 .enable_mask = BIT(0), 1914 .hw.init = &(struct clk_init_data){ 1915 .name = "camss_phy2_csi2phytimer_clk", 1916 .parent_names = (const char *[]){ 1917 "csi2phytimer_clk_src", 1918 }, 1919 .num_parents = 1, 1920 .flags = CLK_SET_RATE_PARENT, 1921 .ops = &clk_branch2_ops, 1922 }, 1923 }, 1924}; 1925 1926static struct clk_branch camss_top_ahb_clk = { 1927 .halt_reg = 0x3484, 1928 .clkr = { 1929 .enable_reg = 0x3484, 1930 .enable_mask = BIT(0), 1931 .hw.init = &(struct clk_init_data){ 1932 .name = "camss_top_ahb_clk", 1933 .parent_names = (const char *[]){ 1934 "mmss_ahb_clk_src", 1935 }, 1936 .num_parents = 1, 1937 .flags = CLK_SET_RATE_PARENT, 1938 .ops = &clk_branch2_ops, 1939 }, 1940 }, 1941}; 1942 1943static struct clk_branch camss_vfe_cpp_ahb_clk = { 1944 .halt_reg = 0x36b4, 1945 .clkr = { 1946 .enable_reg = 0x36b4, 1947 .enable_mask = BIT(0), 1948 .hw.init = &(struct clk_init_data){ 1949 .name = "camss_vfe_cpp_ahb_clk", 1950 .parent_names = (const char *[]){ 1951 "mmss_ahb_clk_src", 1952 }, 1953 .num_parents = 1, 1954 .flags = CLK_SET_RATE_PARENT, 1955 .ops = &clk_branch2_ops, 1956 }, 1957 }, 1958}; 1959 1960static struct clk_branch camss_vfe_cpp_clk = { 1961 .halt_reg = 0x36b0, 1962 .clkr = { 1963 .enable_reg = 0x36b0, 1964 .enable_mask = BIT(0), 1965 .hw.init = &(struct clk_init_data){ 1966 .name = "camss_vfe_cpp_clk", 1967 .parent_names = (const char *[]){ 1968 "cpp_clk_src", 1969 }, 1970 .num_parents = 1, 1971 .flags = CLK_SET_RATE_PARENT, 1972 .ops = &clk_branch2_ops, 1973 }, 1974 }, 1975}; 1976 1977static struct clk_branch camss_vfe_vfe0_clk = { 1978 .halt_reg = 0x36a8, 1979 .clkr = { 1980 .enable_reg = 0x36a8, 1981 .enable_mask = BIT(0), 1982 .hw.init = &(struct clk_init_data){ 1983 .name = "camss_vfe_vfe0_clk", 1984 .parent_names = (const char *[]){ 1985 "vfe0_clk_src", 1986 }, 1987 .num_parents = 1, 1988 .flags = CLK_SET_RATE_PARENT, 1989 .ops = &clk_branch2_ops, 1990 }, 1991 }, 1992}; 1993 1994static struct clk_branch camss_vfe_vfe1_clk = { 1995 .halt_reg = 0x36ac, 1996 .clkr = { 1997 .enable_reg = 0x36ac, 1998 .enable_mask = BIT(0), 1999 .hw.init = &(struct clk_init_data){ 2000 .name = "camss_vfe_vfe1_clk", 2001 .parent_names = (const char *[]){ 2002 "vfe1_clk_src", 2003 }, 2004 .num_parents = 1, 2005 .flags = CLK_SET_RATE_PARENT, 2006 .ops = &clk_branch2_ops, 2007 }, 2008 }, 2009}; 2010 2011static struct clk_branch camss_vfe_vfe_ahb_clk = { 2012 .halt_reg = 0x36b8, 2013 .clkr = { 2014 .enable_reg = 0x36b8, 2015 .enable_mask = BIT(0), 2016 .hw.init = &(struct clk_init_data){ 2017 .name = "camss_vfe_vfe_ahb_clk", 2018 .parent_names = (const char *[]){ 2019 "mmss_ahb_clk_src", 2020 }, 2021 .num_parents = 1, 2022 .flags = CLK_SET_RATE_PARENT, 2023 .ops = &clk_branch2_ops, 2024 }, 2025 }, 2026}; 2027 2028static struct clk_branch camss_vfe_vfe_axi_clk = { 2029 .halt_reg = 0x36bc, 2030 .clkr = { 2031 .enable_reg = 0x36bc, 2032 .enable_mask = BIT(0), 2033 .hw.init = &(struct clk_init_data){ 2034 .name = "camss_vfe_vfe_axi_clk", 2035 .parent_names = (const char *[]){ 2036 "mmss_axi_clk_src", 2037 }, 2038 .num_parents = 1, 2039 .flags = CLK_SET_RATE_PARENT, 2040 .ops = &clk_branch2_ops, 2041 }, 2042 }, 2043}; 2044 2045static struct clk_branch mdss_ahb_clk = { 2046 .halt_reg = 0x2308, 2047 .clkr = { 2048 .enable_reg = 0x2308, 2049 .enable_mask = BIT(0), 2050 .hw.init = &(struct clk_init_data){ 2051 .name = "mdss_ahb_clk", 2052 .parent_names = (const char *[]){ 2053 "mmss_ahb_clk_src", 2054 }, 2055 .num_parents = 1, 2056 .flags = CLK_SET_RATE_PARENT, 2057 .ops = &clk_branch2_ops, 2058 }, 2059 }, 2060}; 2061 2062static struct clk_branch mdss_axi_clk = { 2063 .halt_reg = 0x2310, 2064 .clkr = { 2065 .enable_reg = 0x2310, 2066 .enable_mask = BIT(0), 2067 .hw.init = &(struct clk_init_data){ 2068 .name = "mdss_axi_clk", 2069 .parent_names = (const char *[]){ 2070 "mmss_axi_clk_src", 2071 }, 2072 .num_parents = 1, 2073 .flags = CLK_SET_RATE_PARENT, 2074 .ops = &clk_branch2_ops, 2075 }, 2076 }, 2077}; 2078 2079static struct clk_branch mdss_byte0_clk = { 2080 .halt_reg = 0x233c, 2081 .clkr = { 2082 .enable_reg = 0x233c, 2083 .enable_mask = BIT(0), 2084 .hw.init = &(struct clk_init_data){ 2085 .name = "mdss_byte0_clk", 2086 .parent_names = (const char *[]){ 2087 "byte0_clk_src", 2088 }, 2089 .num_parents = 1, 2090 .flags = CLK_SET_RATE_PARENT, 2091 .ops = &clk_branch2_ops, 2092 }, 2093 }, 2094}; 2095 2096static struct clk_branch mdss_byte1_clk = { 2097 .halt_reg = 0x2340, 2098 .clkr = { 2099 .enable_reg = 0x2340, 2100 .enable_mask = BIT(0), 2101 .hw.init = &(struct clk_init_data){ 2102 .name = "mdss_byte1_clk", 2103 .parent_names = (const char *[]){ 2104 "byte1_clk_src", 2105 }, 2106 .num_parents = 1, 2107 .flags = CLK_SET_RATE_PARENT, 2108 .ops = &clk_branch2_ops, 2109 }, 2110 }, 2111}; 2112 2113static struct clk_branch mdss_edpaux_clk = { 2114 .halt_reg = 0x2334, 2115 .clkr = { 2116 .enable_reg = 0x2334, 2117 .enable_mask = BIT(0), 2118 .hw.init = &(struct clk_init_data){ 2119 .name = "mdss_edpaux_clk", 2120 .parent_names = (const char *[]){ 2121 "edpaux_clk_src", 2122 }, 2123 .num_parents = 1, 2124 .flags = CLK_SET_RATE_PARENT, 2125 .ops = &clk_branch2_ops, 2126 }, 2127 }, 2128}; 2129 2130static struct clk_branch mdss_edplink_clk = { 2131 .halt_reg = 0x2330, 2132 .clkr = { 2133 .enable_reg = 0x2330, 2134 .enable_mask = BIT(0), 2135 .hw.init = &(struct clk_init_data){ 2136 .name = "mdss_edplink_clk", 2137 .parent_names = (const char *[]){ 2138 "edplink_clk_src", 2139 }, 2140 .num_parents = 1, 2141 .flags = CLK_SET_RATE_PARENT, 2142 .ops = &clk_branch2_ops, 2143 }, 2144 }, 2145}; 2146 2147static struct clk_branch mdss_edppixel_clk = { 2148 .halt_reg = 0x232c, 2149 .clkr = { 2150 .enable_reg = 0x232c, 2151 .enable_mask = BIT(0), 2152 .hw.init = &(struct clk_init_data){ 2153 .name = "mdss_edppixel_clk", 2154 .parent_names = (const char *[]){ 2155 "edppixel_clk_src", 2156 }, 2157 .num_parents = 1, 2158 .flags = CLK_SET_RATE_PARENT, 2159 .ops = &clk_branch2_ops, 2160 }, 2161 }, 2162}; 2163 2164static struct clk_branch mdss_esc0_clk = { 2165 .halt_reg = 0x2344, 2166 .clkr = { 2167 .enable_reg = 0x2344, 2168 .enable_mask = BIT(0), 2169 .hw.init = &(struct clk_init_data){ 2170 .name = "mdss_esc0_clk", 2171 .parent_names = (const char *[]){ 2172 "esc0_clk_src", 2173 }, 2174 .num_parents = 1, 2175 .flags = CLK_SET_RATE_PARENT, 2176 .ops = &clk_branch2_ops, 2177 }, 2178 }, 2179}; 2180 2181static struct clk_branch mdss_esc1_clk = { 2182 .halt_reg = 0x2348, 2183 .clkr = { 2184 .enable_reg = 0x2348, 2185 .enable_mask = BIT(0), 2186 .hw.init = &(struct clk_init_data){ 2187 .name = "mdss_esc1_clk", 2188 .parent_names = (const char *[]){ 2189 "esc1_clk_src", 2190 }, 2191 .num_parents = 1, 2192 .flags = CLK_SET_RATE_PARENT, 2193 .ops = &clk_branch2_ops, 2194 }, 2195 }, 2196}; 2197 2198static struct clk_branch mdss_extpclk_clk = { 2199 .halt_reg = 0x2324, 2200 .clkr = { 2201 .enable_reg = 0x2324, 2202 .enable_mask = BIT(0), 2203 .hw.init = &(struct clk_init_data){ 2204 .name = "mdss_extpclk_clk", 2205 .parent_names = (const char *[]){ 2206 "extpclk_clk_src", 2207 }, 2208 .num_parents = 1, 2209 .flags = CLK_SET_RATE_PARENT, 2210 .ops = &clk_branch2_ops, 2211 }, 2212 }, 2213}; 2214 2215static struct clk_branch mdss_hdmi_ahb_clk = { 2216 .halt_reg = 0x230c, 2217 .clkr = { 2218 .enable_reg = 0x230c, 2219 .enable_mask = BIT(0), 2220 .hw.init = &(struct clk_init_data){ 2221 .name = "mdss_hdmi_ahb_clk", 2222 .parent_names = (const char *[]){ 2223 "mmss_ahb_clk_src", 2224 }, 2225 .num_parents = 1, 2226 .flags = CLK_SET_RATE_PARENT, 2227 .ops = &clk_branch2_ops, 2228 }, 2229 }, 2230}; 2231 2232static struct clk_branch mdss_hdmi_clk = { 2233 .halt_reg = 0x2338, 2234 .clkr = { 2235 .enable_reg = 0x2338, 2236 .enable_mask = BIT(0), 2237 .hw.init = &(struct clk_init_data){ 2238 .name = "mdss_hdmi_clk", 2239 .parent_names = (const char *[]){ 2240 "hdmi_clk_src", 2241 }, 2242 .num_parents = 1, 2243 .flags = CLK_SET_RATE_PARENT, 2244 .ops = &clk_branch2_ops, 2245 }, 2246 }, 2247}; 2248 2249static struct clk_branch mdss_mdp_clk = { 2250 .halt_reg = 0x231c, 2251 .clkr = { 2252 .enable_reg = 0x231c, 2253 .enable_mask = BIT(0), 2254 .hw.init = &(struct clk_init_data){ 2255 .name = "mdss_mdp_clk", 2256 .parent_names = (const char *[]){ 2257 "mdp_clk_src", 2258 }, 2259 .num_parents = 1, 2260 .flags = CLK_SET_RATE_PARENT, 2261 .ops = &clk_branch2_ops, 2262 }, 2263 }, 2264}; 2265 2266static struct clk_branch mdss_mdp_lut_clk = { 2267 .halt_reg = 0x2320, 2268 .clkr = { 2269 .enable_reg = 0x2320, 2270 .enable_mask = BIT(0), 2271 .hw.init = &(struct clk_init_data){ 2272 .name = "mdss_mdp_lut_clk", 2273 .parent_names = (const char *[]){ 2274 "mdp_clk_src", 2275 }, 2276 .num_parents = 1, 2277 .flags = CLK_SET_RATE_PARENT, 2278 .ops = &clk_branch2_ops, 2279 }, 2280 }, 2281}; 2282 2283static struct clk_branch mdss_pclk0_clk = { 2284 .halt_reg = 0x2314, 2285 .clkr = { 2286 .enable_reg = 0x2314, 2287 .enable_mask = BIT(0), 2288 .hw.init = &(struct clk_init_data){ 2289 .name = "mdss_pclk0_clk", 2290 .parent_names = (const char *[]){ 2291 "pclk0_clk_src", 2292 }, 2293 .num_parents = 1, 2294 .flags = CLK_SET_RATE_PARENT, 2295 .ops = &clk_branch2_ops, 2296 }, 2297 }, 2298}; 2299 2300static struct clk_branch mdss_pclk1_clk = { 2301 .halt_reg = 0x2318, 2302 .clkr = { 2303 .enable_reg = 0x2318, 2304 .enable_mask = BIT(0), 2305 .hw.init = &(struct clk_init_data){ 2306 .name = "mdss_pclk1_clk", 2307 .parent_names = (const char *[]){ 2308 "pclk1_clk_src", 2309 }, 2310 .num_parents = 1, 2311 .flags = CLK_SET_RATE_PARENT, 2312 .ops = &clk_branch2_ops, 2313 }, 2314 }, 2315}; 2316 2317static struct clk_branch mdss_vsync_clk = { 2318 .halt_reg = 0x2328, 2319 .clkr = { 2320 .enable_reg = 0x2328, 2321 .enable_mask = BIT(0), 2322 .hw.init = &(struct clk_init_data){ 2323 .name = "mdss_vsync_clk", 2324 .parent_names = (const char *[]){ 2325 "vsync_clk_src", 2326 }, 2327 .num_parents = 1, 2328 .flags = CLK_SET_RATE_PARENT, 2329 .ops = &clk_branch2_ops, 2330 }, 2331 }, 2332}; 2333 2334static struct clk_branch mmss_rbcpr_ahb_clk = { 2335 .halt_reg = 0x4088, 2336 .clkr = { 2337 .enable_reg = 0x4088, 2338 .enable_mask = BIT(0), 2339 .hw.init = &(struct clk_init_data){ 2340 .name = "mmss_rbcpr_ahb_clk", 2341 .parent_names = (const char *[]){ 2342 "mmss_ahb_clk_src", 2343 }, 2344 .num_parents = 1, 2345 .flags = CLK_SET_RATE_PARENT, 2346 .ops = &clk_branch2_ops, 2347 }, 2348 }, 2349}; 2350 2351static struct clk_branch mmss_rbcpr_clk = { 2352 .halt_reg = 0x4084, 2353 .clkr = { 2354 .enable_reg = 0x4084, 2355 .enable_mask = BIT(0), 2356 .hw.init = &(struct clk_init_data){ 2357 .name = "mmss_rbcpr_clk", 2358 .parent_names = (const char *[]){ 2359 "rbcpr_clk_src", 2360 }, 2361 .num_parents = 1, 2362 .flags = CLK_SET_RATE_PARENT, 2363 .ops = &clk_branch2_ops, 2364 }, 2365 }, 2366}; 2367 2368static struct clk_branch mmss_spdm_ahb_clk = { 2369 .halt_reg = 0x0230, 2370 .clkr = { 2371 .enable_reg = 0x0230, 2372 .enable_mask = BIT(0), 2373 .hw.init = &(struct clk_init_data){ 2374 .name = "mmss_spdm_ahb_clk", 2375 .parent_names = (const char *[]){ 2376 "mmss_spdm_ahb_div_clk", 2377 }, 2378 .num_parents = 1, 2379 .flags = CLK_SET_RATE_PARENT, 2380 .ops = &clk_branch2_ops, 2381 }, 2382 }, 2383}; 2384 2385static struct clk_branch mmss_spdm_axi_clk = { 2386 .halt_reg = 0x0210, 2387 .clkr = { 2388 .enable_reg = 0x0210, 2389 .enable_mask = BIT(0), 2390 .hw.init = &(struct clk_init_data){ 2391 .name = "mmss_spdm_axi_clk", 2392 .parent_names = (const char *[]){ 2393 "mmss_spdm_axi_div_clk", 2394 }, 2395 .num_parents = 1, 2396 .flags = CLK_SET_RATE_PARENT, 2397 .ops = &clk_branch2_ops, 2398 }, 2399 }, 2400}; 2401 2402static struct clk_branch mmss_spdm_csi0_clk = { 2403 .halt_reg = 0x023c, 2404 .clkr = { 2405 .enable_reg = 0x023c, 2406 .enable_mask = BIT(0), 2407 .hw.init = &(struct clk_init_data){ 2408 .name = "mmss_spdm_csi0_clk", 2409 .parent_names = (const char *[]){ 2410 "mmss_spdm_csi0_div_clk", 2411 }, 2412 .num_parents = 1, 2413 .flags = CLK_SET_RATE_PARENT, 2414 .ops = &clk_branch2_ops, 2415 }, 2416 }, 2417}; 2418 2419static struct clk_branch mmss_spdm_gfx3d_clk = { 2420 .halt_reg = 0x022c, 2421 .clkr = { 2422 .enable_reg = 0x022c, 2423 .enable_mask = BIT(0), 2424 .hw.init = &(struct clk_init_data){ 2425 .name = "mmss_spdm_gfx3d_clk", 2426 .parent_names = (const char *[]){ 2427 "mmss_spdm_gfx3d_div_clk", 2428 }, 2429 .num_parents = 1, 2430 .flags = CLK_SET_RATE_PARENT, 2431 .ops = &clk_branch2_ops, 2432 }, 2433 }, 2434}; 2435 2436static struct clk_branch mmss_spdm_jpeg0_clk = { 2437 .halt_reg = 0x0204, 2438 .clkr = { 2439 .enable_reg = 0x0204, 2440 .enable_mask = BIT(0), 2441 .hw.init = &(struct clk_init_data){ 2442 .name = "mmss_spdm_jpeg0_clk", 2443 .parent_names = (const char *[]){ 2444 "mmss_spdm_jpeg0_div_clk", 2445 }, 2446 .num_parents = 1, 2447 .flags = CLK_SET_RATE_PARENT, 2448 .ops = &clk_branch2_ops, 2449 }, 2450 }, 2451}; 2452 2453static struct clk_branch mmss_spdm_jpeg1_clk = { 2454 .halt_reg = 0x0208, 2455 .clkr = { 2456 .enable_reg = 0x0208, 2457 .enable_mask = BIT(0), 2458 .hw.init = &(struct clk_init_data){ 2459 .name = "mmss_spdm_jpeg1_clk", 2460 .parent_names = (const char *[]){ 2461 "mmss_spdm_jpeg1_div_clk", 2462 }, 2463 .num_parents = 1, 2464 .flags = CLK_SET_RATE_PARENT, 2465 .ops = &clk_branch2_ops, 2466 }, 2467 }, 2468}; 2469 2470static struct clk_branch mmss_spdm_jpeg2_clk = { 2471 .halt_reg = 0x0224, 2472 .clkr = { 2473 .enable_reg = 0x0224, 2474 .enable_mask = BIT(0), 2475 .hw.init = &(struct clk_init_data){ 2476 .name = "mmss_spdm_jpeg2_clk", 2477 .parent_names = (const char *[]){ 2478 "mmss_spdm_jpeg2_div_clk", 2479 }, 2480 .num_parents = 1, 2481 .flags = CLK_SET_RATE_PARENT, 2482 .ops = &clk_branch2_ops, 2483 }, 2484 }, 2485}; 2486 2487static struct clk_branch mmss_spdm_mdp_clk = { 2488 .halt_reg = 0x020c, 2489 .clkr = { 2490 .enable_reg = 0x020c, 2491 .enable_mask = BIT(0), 2492 .hw.init = &(struct clk_init_data){ 2493 .name = "mmss_spdm_mdp_clk", 2494 .parent_names = (const char *[]){ 2495 "mmss_spdm_mdp_div_clk", 2496 }, 2497 .num_parents = 1, 2498 .flags = CLK_SET_RATE_PARENT, 2499 .ops = &clk_branch2_ops, 2500 }, 2501 }, 2502}; 2503 2504static struct clk_branch mmss_spdm_pclk0_clk = { 2505 .halt_reg = 0x0234, 2506 .clkr = { 2507 .enable_reg = 0x0234, 2508 .enable_mask = BIT(0), 2509 .hw.init = &(struct clk_init_data){ 2510 .name = "mmss_spdm_pclk0_clk", 2511 .parent_names = (const char *[]){ 2512 "mmss_spdm_pclk0_div_clk", 2513 }, 2514 .num_parents = 1, 2515 .flags = CLK_SET_RATE_PARENT, 2516 .ops = &clk_branch2_ops, 2517 }, 2518 }, 2519}; 2520 2521static struct clk_branch mmss_spdm_pclk1_clk = { 2522 .halt_reg = 0x0228, 2523 .clkr = { 2524 .enable_reg = 0x0228, 2525 .enable_mask = BIT(0), 2526 .hw.init = &(struct clk_init_data){ 2527 .name = "mmss_spdm_pclk1_clk", 2528 .parent_names = (const char *[]){ 2529 "mmss_spdm_pclk1_div_clk", 2530 }, 2531 .num_parents = 1, 2532 .flags = CLK_SET_RATE_PARENT, 2533 .ops = &clk_branch2_ops, 2534 }, 2535 }, 2536}; 2537 2538static struct clk_branch mmss_spdm_vcodec0_clk = { 2539 .halt_reg = 0x0214, 2540 .clkr = { 2541 .enable_reg = 0x0214, 2542 .enable_mask = BIT(0), 2543 .hw.init = &(struct clk_init_data){ 2544 .name = "mmss_spdm_vcodec0_clk", 2545 .parent_names = (const char *[]){ 2546 "mmss_spdm_vcodec0_div_clk", 2547 }, 2548 .num_parents = 1, 2549 .flags = CLK_SET_RATE_PARENT, 2550 .ops = &clk_branch2_ops, 2551 }, 2552 }, 2553}; 2554 2555static struct clk_branch mmss_spdm_vfe0_clk = { 2556 .halt_reg = 0x0218, 2557 .clkr = { 2558 .enable_reg = 0x0218, 2559 .enable_mask = BIT(0), 2560 .hw.init = &(struct clk_init_data){ 2561 .name = "mmss_spdm_vfe0_clk", 2562 .parent_names = (const char *[]){ 2563 "mmss_spdm_vfe0_div_clk", 2564 }, 2565 .num_parents = 1, 2566 .flags = CLK_SET_RATE_PARENT, 2567 .ops = &clk_branch2_ops, 2568 }, 2569 }, 2570}; 2571 2572static struct clk_branch mmss_spdm_vfe1_clk = { 2573 .halt_reg = 0x021c, 2574 .clkr = { 2575 .enable_reg = 0x021c, 2576 .enable_mask = BIT(0), 2577 .hw.init = &(struct clk_init_data){ 2578 .name = "mmss_spdm_vfe1_clk", 2579 .parent_names = (const char *[]){ 2580 "mmss_spdm_vfe1_div_clk", 2581 }, 2582 .num_parents = 1, 2583 .flags = CLK_SET_RATE_PARENT, 2584 .ops = &clk_branch2_ops, 2585 }, 2586 }, 2587}; 2588 2589static struct clk_branch mmss_spdm_rm_axi_clk = { 2590 .halt_reg = 0x0304, 2591 .clkr = { 2592 .enable_reg = 0x0304, 2593 .enable_mask = BIT(0), 2594 .hw.init = &(struct clk_init_data){ 2595 .name = "mmss_spdm_rm_axi_clk", 2596 .parent_names = (const char *[]){ 2597 "mmss_axi_clk_src", 2598 }, 2599 .num_parents = 1, 2600 .flags = CLK_SET_RATE_PARENT, 2601 .ops = &clk_branch2_ops, 2602 }, 2603 }, 2604}; 2605 2606static struct clk_branch mmss_spdm_rm_ocmemnoc_clk = { 2607 .halt_reg = 0x0308, 2608 .clkr = { 2609 .enable_reg = 0x0308, 2610 .enable_mask = BIT(0), 2611 .hw.init = &(struct clk_init_data){ 2612 .name = "mmss_spdm_rm_ocmemnoc_clk", 2613 .parent_names = (const char *[]){ 2614 "ocmemnoc_clk_src", 2615 }, 2616 .num_parents = 1, 2617 .flags = CLK_SET_RATE_PARENT, 2618 .ops = &clk_branch2_ops, 2619 }, 2620 }, 2621}; 2622 2623 2624static struct clk_branch mmss_misc_ahb_clk = { 2625 .halt_reg = 0x502c, 2626 .clkr = { 2627 .enable_reg = 0x502c, 2628 .enable_mask = BIT(0), 2629 .hw.init = &(struct clk_init_data){ 2630 .name = "mmss_misc_ahb_clk", 2631 .parent_names = (const char *[]){ 2632 "mmss_ahb_clk_src", 2633 }, 2634 .num_parents = 1, 2635 .flags = CLK_SET_RATE_PARENT, 2636 .ops = &clk_branch2_ops, 2637 }, 2638 }, 2639}; 2640 2641static struct clk_branch mmss_mmssnoc_ahb_clk = { 2642 .halt_reg = 0x5024, 2643 .clkr = { 2644 .enable_reg = 0x5024, 2645 .enable_mask = BIT(0), 2646 .hw.init = &(struct clk_init_data){ 2647 .name = "mmss_mmssnoc_ahb_clk", 2648 .parent_names = (const char *[]){ 2649 "mmss_ahb_clk_src", 2650 }, 2651 .num_parents = 1, 2652 .ops = &clk_branch2_ops, 2653 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2654 }, 2655 }, 2656}; 2657 2658static struct clk_branch mmss_mmssnoc_bto_ahb_clk = { 2659 .halt_reg = 0x5028, 2660 .clkr = { 2661 .enable_reg = 0x5028, 2662 .enable_mask = BIT(0), 2663 .hw.init = &(struct clk_init_data){ 2664 .name = "mmss_mmssnoc_bto_ahb_clk", 2665 .parent_names = (const char *[]){ 2666 "mmss_ahb_clk_src", 2667 }, 2668 .num_parents = 1, 2669 .ops = &clk_branch2_ops, 2670 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2671 }, 2672 }, 2673}; 2674 2675static struct clk_branch mmss_mmssnoc_axi_clk = { 2676 .halt_reg = 0x506c, 2677 .clkr = { 2678 .enable_reg = 0x506c, 2679 .enable_mask = BIT(0), 2680 .hw.init = &(struct clk_init_data){ 2681 .name = "mmss_mmssnoc_axi_clk", 2682 .parent_names = (const char *[]){ 2683 "mmss_axi_clk_src", 2684 }, 2685 .num_parents = 1, 2686 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2687 .ops = &clk_branch2_ops, 2688 }, 2689 }, 2690}; 2691 2692static struct clk_branch mmss_s0_axi_clk = { 2693 .halt_reg = 0x5064, 2694 .clkr = { 2695 .enable_reg = 0x5064, 2696 .enable_mask = BIT(0), 2697 .hw.init = &(struct clk_init_data){ 2698 .name = "mmss_s0_axi_clk", 2699 .parent_names = (const char *[]){ 2700 "mmss_axi_clk_src", 2701 }, 2702 .num_parents = 1, 2703 .ops = &clk_branch2_ops, 2704 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2705 }, 2706 }, 2707}; 2708 2709static struct clk_branch ocmemcx_ahb_clk = { 2710 .halt_reg = 0x405c, 2711 .clkr = { 2712 .enable_reg = 0x405c, 2713 .enable_mask = BIT(0), 2714 .hw.init = &(struct clk_init_data){ 2715 .name = "ocmemcx_ahb_clk", 2716 .parent_names = (const char *[]){ 2717 "mmss_ahb_clk_src", 2718 }, 2719 .num_parents = 1, 2720 .flags = CLK_SET_RATE_PARENT, 2721 .ops = &clk_branch2_ops, 2722 }, 2723 }, 2724}; 2725 2726static struct clk_branch ocmemcx_ocmemnoc_clk = { 2727 .halt_reg = 0x4058, 2728 .clkr = { 2729 .enable_reg = 0x4058, 2730 .enable_mask = BIT(0), 2731 .hw.init = &(struct clk_init_data){ 2732 .name = "ocmemcx_ocmemnoc_clk", 2733 .parent_names = (const char *[]){ 2734 "ocmemnoc_clk_src", 2735 }, 2736 .num_parents = 1, 2737 .flags = CLK_SET_RATE_PARENT, 2738 .ops = &clk_branch2_ops, 2739 }, 2740 }, 2741}; 2742 2743static struct clk_branch oxili_ocmemgx_clk = { 2744 .halt_reg = 0x402c, 2745 .clkr = { 2746 .enable_reg = 0x402c, 2747 .enable_mask = BIT(0), 2748 .hw.init = &(struct clk_init_data){ 2749 .name = "oxili_ocmemgx_clk", 2750 .parent_names = (const char *[]){ 2751 "gfx3d_clk_src", 2752 }, 2753 .num_parents = 1, 2754 .flags = CLK_SET_RATE_PARENT, 2755 .ops = &clk_branch2_ops, 2756 }, 2757 }, 2758}; 2759 2760static struct clk_branch oxili_gfx3d_clk = { 2761 .halt_reg = 0x4028, 2762 .clkr = { 2763 .enable_reg = 0x4028, 2764 .enable_mask = BIT(0), 2765 .hw.init = &(struct clk_init_data){ 2766 .name = "oxili_gfx3d_clk", 2767 .parent_names = (const char *[]){ 2768 "gfx3d_clk_src", 2769 }, 2770 .num_parents = 1, 2771 .flags = CLK_SET_RATE_PARENT, 2772 .ops = &clk_branch2_ops, 2773 }, 2774 }, 2775}; 2776 2777static struct clk_branch oxili_rbbmtimer_clk = { 2778 .halt_reg = 0x40b0, 2779 .clkr = { 2780 .enable_reg = 0x40b0, 2781 .enable_mask = BIT(0), 2782 .hw.init = &(struct clk_init_data){ 2783 .name = "oxili_rbbmtimer_clk", 2784 .parent_names = (const char *[]){ 2785 "rbbmtimer_clk_src", 2786 }, 2787 .num_parents = 1, 2788 .flags = CLK_SET_RATE_PARENT, 2789 .ops = &clk_branch2_ops, 2790 }, 2791 }, 2792}; 2793 2794static struct clk_branch oxilicx_ahb_clk = { 2795 .halt_reg = 0x403c, 2796 .clkr = { 2797 .enable_reg = 0x403c, 2798 .enable_mask = BIT(0), 2799 .hw.init = &(struct clk_init_data){ 2800 .name = "oxilicx_ahb_clk", 2801 .parent_names = (const char *[]){ 2802 "mmss_ahb_clk_src", 2803 }, 2804 .num_parents = 1, 2805 .flags = CLK_SET_RATE_PARENT, 2806 .ops = &clk_branch2_ops, 2807 }, 2808 }, 2809}; 2810 2811static struct clk_branch venus0_ahb_clk = { 2812 .halt_reg = 0x1030, 2813 .clkr = { 2814 .enable_reg = 0x1030, 2815 .enable_mask = BIT(0), 2816 .hw.init = &(struct clk_init_data){ 2817 .name = "venus0_ahb_clk", 2818 .parent_names = (const char *[]){ 2819 "mmss_ahb_clk_src", 2820 }, 2821 .num_parents = 1, 2822 .flags = CLK_SET_RATE_PARENT, 2823 .ops = &clk_branch2_ops, 2824 }, 2825 }, 2826}; 2827 2828static struct clk_branch venus0_axi_clk = { 2829 .halt_reg = 0x1034, 2830 .clkr = { 2831 .enable_reg = 0x1034, 2832 .enable_mask = BIT(0), 2833 .hw.init = &(struct clk_init_data){ 2834 .name = "venus0_axi_clk", 2835 .parent_names = (const char *[]){ 2836 "mmss_axi_clk_src", 2837 }, 2838 .num_parents = 1, 2839 .flags = CLK_SET_RATE_PARENT, 2840 .ops = &clk_branch2_ops, 2841 }, 2842 }, 2843}; 2844 2845static struct clk_branch venus0_core0_vcodec_clk = { 2846 .halt_reg = 0x1048, 2847 .clkr = { 2848 .enable_reg = 0x1048, 2849 .enable_mask = BIT(0), 2850 .hw.init = &(struct clk_init_data){ 2851 .name = "venus0_core0_vcodec_clk", 2852 .parent_names = (const char *[]){ 2853 "vcodec0_clk_src", 2854 }, 2855 .num_parents = 1, 2856 .flags = CLK_SET_RATE_PARENT, 2857 .ops = &clk_branch2_ops, 2858 }, 2859 }, 2860}; 2861 2862static struct clk_branch venus0_core1_vcodec_clk = { 2863 .halt_reg = 0x104c, 2864 .clkr = { 2865 .enable_reg = 0x104c, 2866 .enable_mask = BIT(0), 2867 .hw.init = &(struct clk_init_data){ 2868 .name = "venus0_core1_vcodec_clk", 2869 .parent_names = (const char *[]){ 2870 "vcodec0_clk_src", 2871 }, 2872 .num_parents = 1, 2873 .flags = CLK_SET_RATE_PARENT, 2874 .ops = &clk_branch2_ops, 2875 }, 2876 }, 2877}; 2878 2879static struct clk_branch venus0_ocmemnoc_clk = { 2880 .halt_reg = 0x1038, 2881 .clkr = { 2882 .enable_reg = 0x1038, 2883 .enable_mask = BIT(0), 2884 .hw.init = &(struct clk_init_data){ 2885 .name = "venus0_ocmemnoc_clk", 2886 .parent_names = (const char *[]){ 2887 "ocmemnoc_clk_src", 2888 }, 2889 .num_parents = 1, 2890 .flags = CLK_SET_RATE_PARENT, 2891 .ops = &clk_branch2_ops, 2892 }, 2893 }, 2894}; 2895 2896static struct clk_branch venus0_vcodec0_clk = { 2897 .halt_reg = 0x1028, 2898 .clkr = { 2899 .enable_reg = 0x1028, 2900 .enable_mask = BIT(0), 2901 .hw.init = &(struct clk_init_data){ 2902 .name = "venus0_vcodec0_clk", 2903 .parent_names = (const char *[]){ 2904 "vcodec0_clk_src", 2905 }, 2906 .num_parents = 1, 2907 .flags = CLK_SET_RATE_PARENT, 2908 .ops = &clk_branch2_ops, 2909 }, 2910 }, 2911}; 2912 2913static struct clk_branch vpu_ahb_clk = { 2914 .halt_reg = 0x1430, 2915 .clkr = { 2916 .enable_reg = 0x1430, 2917 .enable_mask = BIT(0), 2918 .hw.init = &(struct clk_init_data){ 2919 .name = "vpu_ahb_clk", 2920 .parent_names = (const char *[]){ 2921 "mmss_ahb_clk_src", 2922 }, 2923 .num_parents = 1, 2924 .flags = CLK_SET_RATE_PARENT, 2925 .ops = &clk_branch2_ops, 2926 }, 2927 }, 2928}; 2929 2930static struct clk_branch vpu_axi_clk = { 2931 .halt_reg = 0x143c, 2932 .clkr = { 2933 .enable_reg = 0x143c, 2934 .enable_mask = BIT(0), 2935 .hw.init = &(struct clk_init_data){ 2936 .name = "vpu_axi_clk", 2937 .parent_names = (const char *[]){ 2938 "mmss_axi_clk_src", 2939 }, 2940 .num_parents = 1, 2941 .flags = CLK_SET_RATE_PARENT, 2942 .ops = &clk_branch2_ops, 2943 }, 2944 }, 2945}; 2946 2947static struct clk_branch vpu_bus_clk = { 2948 .halt_reg = 0x1440, 2949 .clkr = { 2950 .enable_reg = 0x1440, 2951 .enable_mask = BIT(0), 2952 .hw.init = &(struct clk_init_data){ 2953 .name = "vpu_bus_clk", 2954 .parent_names = (const char *[]){ 2955 "vpu_bus_clk_src", 2956 }, 2957 .num_parents = 1, 2958 .flags = CLK_SET_RATE_PARENT, 2959 .ops = &clk_branch2_ops, 2960 }, 2961 }, 2962}; 2963 2964static struct clk_branch vpu_cxo_clk = { 2965 .halt_reg = 0x1434, 2966 .clkr = { 2967 .enable_reg = 0x1434, 2968 .enable_mask = BIT(0), 2969 .hw.init = &(struct clk_init_data){ 2970 .name = "vpu_cxo_clk", 2971 .parent_names = (const char *[]){ "xo" }, 2972 .num_parents = 1, 2973 .flags = CLK_SET_RATE_PARENT, 2974 .ops = &clk_branch2_ops, 2975 }, 2976 }, 2977}; 2978 2979static struct clk_branch vpu_maple_clk = { 2980 .halt_reg = 0x142c, 2981 .clkr = { 2982 .enable_reg = 0x142c, 2983 .enable_mask = BIT(0), 2984 .hw.init = &(struct clk_init_data){ 2985 .name = "vpu_maple_clk", 2986 .parent_names = (const char *[]){ 2987 "maple_clk_src", 2988 }, 2989 .num_parents = 1, 2990 .flags = CLK_SET_RATE_PARENT, 2991 .ops = &clk_branch2_ops, 2992 }, 2993 }, 2994}; 2995 2996static struct clk_branch vpu_sleep_clk = { 2997 .halt_reg = 0x1438, 2998 .clkr = { 2999 .enable_reg = 0x1438, 3000 .enable_mask = BIT(0), 3001 .hw.init = &(struct clk_init_data){ 3002 .name = "vpu_sleep_clk", 3003 .parent_names = (const char *[]){ 3004 "sleep_clk_src", 3005 }, 3006 .num_parents = 1, 3007 .flags = CLK_SET_RATE_PARENT, 3008 .ops = &clk_branch2_ops, 3009 }, 3010 }, 3011}; 3012 3013static struct clk_branch vpu_vdp_clk = { 3014 .halt_reg = 0x1428, 3015 .clkr = { 3016 .enable_reg = 0x1428, 3017 .enable_mask = BIT(0), 3018 .hw.init = &(struct clk_init_data){ 3019 .name = "vpu_vdp_clk", 3020 .parent_names = (const char *[]){ 3021 "vdp_clk_src", 3022 }, 3023 .num_parents = 1, 3024 .flags = CLK_SET_RATE_PARENT, 3025 .ops = &clk_branch2_ops, 3026 }, 3027 }, 3028}; 3029 3030static const struct pll_config mmpll1_config = { 3031 .l = 60, 3032 .m = 25, 3033 .n = 32, 3034 .vco_val = 0x0, 3035 .vco_mask = 0x3 << 20, 3036 .pre_div_val = 0x0, 3037 .pre_div_mask = 0x7 << 12, 3038 .post_div_val = 0x0, 3039 .post_div_mask = 0x3 << 8, 3040 .mn_ena_mask = BIT(24), 3041 .main_output_mask = BIT(0), 3042}; 3043 3044static const struct pll_config mmpll3_config = { 3045 .l = 48, 3046 .m = 7, 3047 .n = 16, 3048 .vco_val = 0x0, 3049 .vco_mask = 0x3 << 20, 3050 .pre_div_val = 0x0, 3051 .pre_div_mask = 0x7 << 12, 3052 .post_div_val = 0x0, 3053 .post_div_mask = 0x3 << 8, 3054 .mn_ena_mask = BIT(24), 3055 .main_output_mask = BIT(0), 3056 .aux_output_mask = BIT(1), 3057}; 3058 3059static struct gdsc venus0_gdsc = { 3060 .gdscr = 0x1024, 3061 .pd = { 3062 .name = "venus0", 3063 }, 3064 .pwrsts = PWRSTS_OFF_ON, 3065}; 3066 3067static struct gdsc venus0_core0_gdsc = { 3068 .gdscr = 0x1040, 3069 .pd = { 3070 .name = "venus0_core0", 3071 }, 3072 .pwrsts = PWRSTS_OFF_ON, 3073}; 3074 3075static struct gdsc venus0_core1_gdsc = { 3076 .gdscr = 0x1044, 3077 .pd = { 3078 .name = "venus0_core1", 3079 }, 3080 .pwrsts = PWRSTS_OFF_ON, 3081}; 3082 3083static struct gdsc mdss_gdsc = { 3084 .gdscr = 0x2304, 3085 .cxcs = (unsigned int []){ 0x231c, 0x2320 }, 3086 .cxc_count = 2, 3087 .pd = { 3088 .name = "mdss", 3089 }, 3090 .pwrsts = PWRSTS_OFF_ON, 3091}; 3092 3093static struct gdsc camss_jpeg_gdsc = { 3094 .gdscr = 0x35a4, 3095 .pd = { 3096 .name = "camss_jpeg", 3097 }, 3098 .pwrsts = PWRSTS_OFF_ON, 3099}; 3100 3101static struct gdsc camss_vfe_gdsc = { 3102 .gdscr = 0x36a4, 3103 .cxcs = (unsigned int []){ 0x36a8, 0x36ac, 0x36b0 }, 3104 .cxc_count = 3, 3105 .pd = { 3106 .name = "camss_vfe", 3107 }, 3108 .pwrsts = PWRSTS_OFF_ON, 3109}; 3110 3111static struct gdsc oxili_gdsc = { 3112 .gdscr = 0x4024, 3113 .cxcs = (unsigned int []){ 0x4028 }, 3114 .cxc_count = 1, 3115 .pd = { 3116 .name = "oxili", 3117 }, 3118 .pwrsts = PWRSTS_OFF_ON, 3119}; 3120 3121static struct gdsc oxilicx_gdsc = { 3122 .gdscr = 0x4034, 3123 .pd = { 3124 .name = "oxilicx", 3125 }, 3126 .pwrsts = PWRSTS_OFF_ON, 3127}; 3128 3129static struct clk_regmap *mmcc_apq8084_clocks[] = { 3130 [MMSS_AHB_CLK_SRC] = &mmss_ahb_clk_src.clkr, 3131 [MMSS_AXI_CLK_SRC] = &mmss_axi_clk_src.clkr, 3132 [MMPLL0] = &mmpll0.clkr, 3133 [MMPLL0_VOTE] = &mmpll0_vote, 3134 [MMPLL1] = &mmpll1.clkr, 3135 [MMPLL1_VOTE] = &mmpll1_vote, 3136 [MMPLL2] = &mmpll2.clkr, 3137 [MMPLL3] = &mmpll3.clkr, 3138 [MMPLL4] = &mmpll4.clkr, 3139 [CSI0_CLK_SRC] = &csi0_clk_src.clkr, 3140 [CSI1_CLK_SRC] = &csi1_clk_src.clkr, 3141 [CSI2_CLK_SRC] = &csi2_clk_src.clkr, 3142 [CSI3_CLK_SRC] = &csi3_clk_src.clkr, 3143 [VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr, 3144 [VFE0_CLK_SRC] = &vfe0_clk_src.clkr, 3145 [VFE1_CLK_SRC] = &vfe1_clk_src.clkr, 3146 [MDP_CLK_SRC] = &mdp_clk_src.clkr, 3147 [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr, 3148 [PCLK1_CLK_SRC] = &pclk1_clk_src.clkr, 3149 [OCMEMNOC_CLK_SRC] = &ocmemnoc_clk_src.clkr, 3150 [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr, 3151 [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr, 3152 [JPEG1_CLK_SRC] = &jpeg1_clk_src.clkr, 3153 [JPEG2_CLK_SRC] = &jpeg2_clk_src.clkr, 3154 [EDPPIXEL_CLK_SRC] = &edppixel_clk_src.clkr, 3155 [EXTPCLK_CLK_SRC] = &extpclk_clk_src.clkr, 3156 [VP_CLK_SRC] = &vp_clk_src.clkr, 3157 [CCI_CLK_SRC] = &cci_clk_src.clkr, 3158 [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr, 3159 [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr, 3160 [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr, 3161 [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr, 3162 [MCLK2_CLK_SRC] = &mclk2_clk_src.clkr, 3163 [MCLK3_CLK_SRC] = &mclk3_clk_src.clkr, 3164 [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr, 3165 [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr, 3166 [CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr, 3167 [CPP_CLK_SRC] = &cpp_clk_src.clkr, 3168 [BYTE0_CLK_SRC] = &byte0_clk_src.clkr, 3169 [BYTE1_CLK_SRC] = &byte1_clk_src.clkr, 3170 [EDPAUX_CLK_SRC] = &edpaux_clk_src.clkr, 3171 [EDPLINK_CLK_SRC] = &edplink_clk_src.clkr, 3172 [ESC0_CLK_SRC] = &esc0_clk_src.clkr, 3173 [ESC1_CLK_SRC] = &esc1_clk_src.clkr, 3174 [HDMI_CLK_SRC] = &hdmi_clk_src.clkr, 3175 [VSYNC_CLK_SRC] = &vsync_clk_src.clkr, 3176 [MMSS_RBCPR_CLK_SRC] = &rbcpr_clk_src.clkr, 3177 [RBBMTIMER_CLK_SRC] = &rbbmtimer_clk_src.clkr, 3178 [MAPLE_CLK_SRC] = &maple_clk_src.clkr, 3179 [VDP_CLK_SRC] = &vdp_clk_src.clkr, 3180 [VPU_BUS_CLK_SRC] = &vpu_bus_clk_src.clkr, 3181 [MMSS_CXO_CLK] = &mmss_cxo_clk.clkr, 3182 [MMSS_SLEEPCLK_CLK] = &mmss_sleepclk_clk.clkr, 3183 [AVSYNC_AHB_CLK] = &avsync_ahb_clk.clkr, 3184 [AVSYNC_EDPPIXEL_CLK] = &avsync_edppixel_clk.clkr, 3185 [AVSYNC_EXTPCLK_CLK] = &avsync_extpclk_clk.clkr, 3186 [AVSYNC_PCLK0_CLK] = &avsync_pclk0_clk.clkr, 3187 [AVSYNC_PCLK1_CLK] = &avsync_pclk1_clk.clkr, 3188 [AVSYNC_VP_CLK] = &avsync_vp_clk.clkr, 3189 [CAMSS_AHB_CLK] = &camss_ahb_clk.clkr, 3190 [CAMSS_CCI_CCI_AHB_CLK] = &camss_cci_cci_ahb_clk.clkr, 3191 [CAMSS_CCI_CCI_CLK] = &camss_cci_cci_clk.clkr, 3192 [CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr, 3193 [CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr, 3194 [CAMSS_CSI0PHY_CLK] = &camss_csi0phy_clk.clkr, 3195 [CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr, 3196 [CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr, 3197 [CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr, 3198 [CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr, 3199 [CAMSS_CSI1PHY_CLK] = &camss_csi1phy_clk.clkr, 3200 [CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr, 3201 [CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr, 3202 [CAMSS_CSI2_AHB_CLK] = &camss_csi2_ahb_clk.clkr, 3203 [CAMSS_CSI2_CLK] = &camss_csi2_clk.clkr, 3204 [CAMSS_CSI2PHY_CLK] = &camss_csi2phy_clk.clkr, 3205 [CAMSS_CSI2PIX_CLK] = &camss_csi2pix_clk.clkr, 3206 [CAMSS_CSI2RDI_CLK] = &camss_csi2rdi_clk.clkr, 3207 [CAMSS_CSI3_AHB_CLK] = &camss_csi3_ahb_clk.clkr, 3208 [CAMSS_CSI3_CLK] = &camss_csi3_clk.clkr, 3209 [CAMSS_CSI3PHY_CLK] = &camss_csi3phy_clk.clkr, 3210 [CAMSS_CSI3PIX_CLK] = &camss_csi3pix_clk.clkr, 3211 [CAMSS_CSI3RDI_CLK] = &camss_csi3rdi_clk.clkr, 3212 [CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr, 3213 [CAMSS_CSI_VFE1_CLK] = &camss_csi_vfe1_clk.clkr, 3214 [CAMSS_GP0_CLK] = &camss_gp0_clk.clkr, 3215 [CAMSS_GP1_CLK] = &camss_gp1_clk.clkr, 3216 [CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr, 3217 [CAMSS_JPEG_JPEG0_CLK] = &camss_jpeg_jpeg0_clk.clkr, 3218 [CAMSS_JPEG_JPEG1_CLK] = &camss_jpeg_jpeg1_clk.clkr, 3219 [CAMSS_JPEG_JPEG2_CLK] = &camss_jpeg_jpeg2_clk.clkr, 3220 [CAMSS_JPEG_JPEG_AHB_CLK] = &camss_jpeg_jpeg_ahb_clk.clkr, 3221 [CAMSS_JPEG_JPEG_AXI_CLK] = &camss_jpeg_jpeg_axi_clk.clkr, 3222 [CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr, 3223 [CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr, 3224 [CAMSS_MCLK2_CLK] = &camss_mclk2_clk.clkr, 3225 [CAMSS_MCLK3_CLK] = &camss_mclk3_clk.clkr, 3226 [CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr, 3227 [CAMSS_PHY0_CSI0PHYTIMER_CLK] = &camss_phy0_csi0phytimer_clk.clkr, 3228 [CAMSS_PHY1_CSI1PHYTIMER_CLK] = &camss_phy1_csi1phytimer_clk.clkr, 3229 [CAMSS_PHY2_CSI2PHYTIMER_CLK] = &camss_phy2_csi2phytimer_clk.clkr, 3230 [CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr, 3231 [CAMSS_VFE_CPP_AHB_CLK] = &camss_vfe_cpp_ahb_clk.clkr, 3232 [CAMSS_VFE_CPP_CLK] = &camss_vfe_cpp_clk.clkr, 3233 [CAMSS_VFE_VFE0_CLK] = &camss_vfe_vfe0_clk.clkr, 3234 [CAMSS_VFE_VFE1_CLK] = &camss_vfe_vfe1_clk.clkr, 3235 [CAMSS_VFE_VFE_AHB_CLK] = &camss_vfe_vfe_ahb_clk.clkr, 3236 [CAMSS_VFE_VFE_AXI_CLK] = &camss_vfe_vfe_axi_clk.clkr, 3237 [MDSS_AHB_CLK] = &mdss_ahb_clk.clkr, 3238 [MDSS_AXI_CLK] = &mdss_axi_clk.clkr, 3239 [MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr, 3240 [MDSS_BYTE1_CLK] = &mdss_byte1_clk.clkr, 3241 [MDSS_EDPAUX_CLK] = &mdss_edpaux_clk.clkr, 3242 [MDSS_EDPLINK_CLK] = &mdss_edplink_clk.clkr, 3243 [MDSS_EDPPIXEL_CLK] = &mdss_edppixel_clk.clkr, 3244 [MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr, 3245 [MDSS_ESC1_CLK] = &mdss_esc1_clk.clkr, 3246 [MDSS_EXTPCLK_CLK] = &mdss_extpclk_clk.clkr, 3247 [MDSS_HDMI_AHB_CLK] = &mdss_hdmi_ahb_clk.clkr, 3248 [MDSS_HDMI_CLK] = &mdss_hdmi_clk.clkr, 3249 [MDSS_MDP_CLK] = &mdss_mdp_clk.clkr, 3250 [MDSS_MDP_LUT_CLK] = &mdss_mdp_lut_clk.clkr, 3251 [MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr, 3252 [MDSS_PCLK1_CLK] = &mdss_pclk1_clk.clkr, 3253 [MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr, 3254 [MMSS_RBCPR_AHB_CLK] = &mmss_rbcpr_ahb_clk.clkr, 3255 [MMSS_RBCPR_CLK] = &mmss_rbcpr_clk.clkr, 3256 [MMSS_SPDM_AHB_CLK] = &mmss_spdm_ahb_clk.clkr, 3257 [MMSS_SPDM_AXI_CLK] = &mmss_spdm_axi_clk.clkr, 3258 [MMSS_SPDM_CSI0_CLK] = &mmss_spdm_csi0_clk.clkr, 3259 [MMSS_SPDM_GFX3D_CLK] = &mmss_spdm_gfx3d_clk.clkr, 3260 [MMSS_SPDM_JPEG0_CLK] = &mmss_spdm_jpeg0_clk.clkr, 3261 [MMSS_SPDM_JPEG1_CLK] = &mmss_spdm_jpeg1_clk.clkr, 3262 [MMSS_SPDM_JPEG2_CLK] = &mmss_spdm_jpeg2_clk.clkr, 3263 [MMSS_SPDM_MDP_CLK] = &mmss_spdm_mdp_clk.clkr, 3264 [MMSS_SPDM_PCLK0_CLK] = &mmss_spdm_pclk0_clk.clkr, 3265 [MMSS_SPDM_PCLK1_CLK] = &mmss_spdm_pclk1_clk.clkr, 3266 [MMSS_SPDM_VCODEC0_CLK] = &mmss_spdm_vcodec0_clk.clkr, 3267 [MMSS_SPDM_VFE0_CLK] = &mmss_spdm_vfe0_clk.clkr, 3268 [MMSS_SPDM_VFE1_CLK] = &mmss_spdm_vfe1_clk.clkr, 3269 [MMSS_SPDM_RM_AXI_CLK] = &mmss_spdm_rm_axi_clk.clkr, 3270 [MMSS_SPDM_RM_OCMEMNOC_CLK] = &mmss_spdm_rm_ocmemnoc_clk.clkr, 3271 [MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr, 3272 [MMSS_MMSSNOC_AHB_CLK] = &mmss_mmssnoc_ahb_clk.clkr, 3273 [MMSS_MMSSNOC_BTO_AHB_CLK] = &mmss_mmssnoc_bto_ahb_clk.clkr, 3274 [MMSS_MMSSNOC_AXI_CLK] = &mmss_mmssnoc_axi_clk.clkr, 3275 [MMSS_S0_AXI_CLK] = &mmss_s0_axi_clk.clkr, 3276 [OCMEMCX_AHB_CLK] = &ocmemcx_ahb_clk.clkr, 3277 [OCMEMCX_OCMEMNOC_CLK] = &ocmemcx_ocmemnoc_clk.clkr, 3278 [OXILI_OCMEMGX_CLK] = &oxili_ocmemgx_clk.clkr, 3279 [OXILI_GFX3D_CLK] = &oxili_gfx3d_clk.clkr, 3280 [OXILI_RBBMTIMER_CLK] = &oxili_rbbmtimer_clk.clkr, 3281 [OXILICX_AHB_CLK] = &oxilicx_ahb_clk.clkr, 3282 [VENUS0_AHB_CLK] = &venus0_ahb_clk.clkr, 3283 [VENUS0_AXI_CLK] = &venus0_axi_clk.clkr, 3284 [VENUS0_CORE0_VCODEC_CLK] = &venus0_core0_vcodec_clk.clkr, 3285 [VENUS0_CORE1_VCODEC_CLK] = &venus0_core1_vcodec_clk.clkr, 3286 [VENUS0_OCMEMNOC_CLK] = &venus0_ocmemnoc_clk.clkr, 3287 [VENUS0_VCODEC0_CLK] = &venus0_vcodec0_clk.clkr, 3288 [VPU_AHB_CLK] = &vpu_ahb_clk.clkr, 3289 [VPU_AXI_CLK] = &vpu_axi_clk.clkr, 3290 [VPU_BUS_CLK] = &vpu_bus_clk.clkr, 3291 [VPU_CXO_CLK] = &vpu_cxo_clk.clkr, 3292 [VPU_MAPLE_CLK] = &vpu_maple_clk.clkr, 3293 [VPU_SLEEP_CLK] = &vpu_sleep_clk.clkr, 3294 [VPU_VDP_CLK] = &vpu_vdp_clk.clkr, 3295}; 3296 3297static const struct qcom_reset_map mmcc_apq8084_resets[] = { 3298 [MMSS_SPDM_RESET] = { 0x0200 }, 3299 [MMSS_SPDM_RM_RESET] = { 0x0300 }, 3300 [VENUS0_RESET] = { 0x1020 }, 3301 [VPU_RESET] = { 0x1400 }, 3302 [MDSS_RESET] = { 0x2300 }, 3303 [AVSYNC_RESET] = { 0x2400 }, 3304 [CAMSS_PHY0_RESET] = { 0x3020 }, 3305 [CAMSS_PHY1_RESET] = { 0x3050 }, 3306 [CAMSS_PHY2_RESET] = { 0x3080 }, 3307 [CAMSS_CSI0_RESET] = { 0x30b0 }, 3308 [CAMSS_CSI0PHY_RESET] = { 0x30c0 }, 3309 [CAMSS_CSI0RDI_RESET] = { 0x30d0 }, 3310 [CAMSS_CSI0PIX_RESET] = { 0x30e0 }, 3311 [CAMSS_CSI1_RESET] = { 0x3120 }, 3312 [CAMSS_CSI1PHY_RESET] = { 0x3130 }, 3313 [CAMSS_CSI1RDI_RESET] = { 0x3140 }, 3314 [CAMSS_CSI1PIX_RESET] = { 0x3150 }, 3315 [CAMSS_CSI2_RESET] = { 0x3180 }, 3316 [CAMSS_CSI2PHY_RESET] = { 0x3190 }, 3317 [CAMSS_CSI2RDI_RESET] = { 0x31a0 }, 3318 [CAMSS_CSI2PIX_RESET] = { 0x31b0 }, 3319 [CAMSS_CSI3_RESET] = { 0x31e0 }, 3320 [CAMSS_CSI3PHY_RESET] = { 0x31f0 }, 3321 [CAMSS_CSI3RDI_RESET] = { 0x3200 }, 3322 [CAMSS_CSI3PIX_RESET] = { 0x3210 }, 3323 [CAMSS_ISPIF_RESET] = { 0x3220 }, 3324 [CAMSS_CCI_RESET] = { 0x3340 }, 3325 [CAMSS_MCLK0_RESET] = { 0x3380 }, 3326 [CAMSS_MCLK1_RESET] = { 0x33b0 }, 3327 [CAMSS_MCLK2_RESET] = { 0x33e0 }, 3328 [CAMSS_MCLK3_RESET] = { 0x3410 }, 3329 [CAMSS_GP0_RESET] = { 0x3440 }, 3330 [CAMSS_GP1_RESET] = { 0x3470 }, 3331 [CAMSS_TOP_RESET] = { 0x3480 }, 3332 [CAMSS_AHB_RESET] = { 0x3488 }, 3333 [CAMSS_MICRO_RESET] = { 0x3490 }, 3334 [CAMSS_JPEG_RESET] = { 0x35a0 }, 3335 [CAMSS_VFE_RESET] = { 0x36a0 }, 3336 [CAMSS_CSI_VFE0_RESET] = { 0x3700 }, 3337 [CAMSS_CSI_VFE1_RESET] = { 0x3710 }, 3338 [OXILI_RESET] = { 0x4020 }, 3339 [OXILICX_RESET] = { 0x4030 }, 3340 [OCMEMCX_RESET] = { 0x4050 }, 3341 [MMSS_RBCRP_RESET] = { 0x4080 }, 3342 [MMSSNOCAHB_RESET] = { 0x5020 }, 3343 [MMSSNOCAXI_RESET] = { 0x5060 }, 3344}; 3345 3346static struct gdsc *mmcc_apq8084_gdscs[] = { 3347 [VENUS0_GDSC] = &venus0_gdsc, 3348 [VENUS0_CORE0_GDSC] = &venus0_core0_gdsc, 3349 [VENUS0_CORE1_GDSC] = &venus0_core1_gdsc, 3350 [MDSS_GDSC] = &mdss_gdsc, 3351 [CAMSS_JPEG_GDSC] = &camss_jpeg_gdsc, 3352 [CAMSS_VFE_GDSC] = &camss_vfe_gdsc, 3353 [OXILI_GDSC] = &oxili_gdsc, 3354 [OXILICX_GDSC] = &oxilicx_gdsc, 3355}; 3356 3357static const struct regmap_config mmcc_apq8084_regmap_config = { 3358 .reg_bits = 32, 3359 .reg_stride = 4, 3360 .val_bits = 32, 3361 .max_register = 0x5104, 3362 .fast_io = true, 3363}; 3364 3365static const struct qcom_cc_desc mmcc_apq8084_desc = { 3366 .config = &mmcc_apq8084_regmap_config, 3367 .clks = mmcc_apq8084_clocks, 3368 .num_clks = ARRAY_SIZE(mmcc_apq8084_clocks), 3369 .resets = mmcc_apq8084_resets, 3370 .num_resets = ARRAY_SIZE(mmcc_apq8084_resets), 3371 .gdscs = mmcc_apq8084_gdscs, 3372 .num_gdscs = ARRAY_SIZE(mmcc_apq8084_gdscs), 3373}; 3374 3375static const struct of_device_id mmcc_apq8084_match_table[] = { 3376 { .compatible = "qcom,mmcc-apq8084" }, 3377 { } 3378}; 3379MODULE_DEVICE_TABLE(of, mmcc_apq8084_match_table); 3380 3381static int mmcc_apq8084_probe(struct platform_device *pdev) 3382{ 3383 int ret; 3384 struct regmap *regmap; 3385 3386 ret = qcom_cc_probe(pdev, &mmcc_apq8084_desc); 3387 if (ret) 3388 return ret; 3389 3390 regmap = dev_get_regmap(&pdev->dev, NULL); 3391 clk_pll_configure_sr_hpm_lp(&mmpll1, regmap, &mmpll1_config, true); 3392 clk_pll_configure_sr_hpm_lp(&mmpll3, regmap, &mmpll3_config, false); 3393 3394 return 0; 3395} 3396 3397static struct platform_driver mmcc_apq8084_driver = { 3398 .probe = mmcc_apq8084_probe, 3399 .driver = { 3400 .name = "mmcc-apq8084", 3401 .of_match_table = mmcc_apq8084_match_table, 3402 }, 3403}; 3404module_platform_driver(mmcc_apq8084_driver); 3405 3406MODULE_DESCRIPTION("QCOM MMCC APQ8084 Driver"); 3407MODULE_LICENSE("GPL v2"); 3408MODULE_ALIAS("platform:mmcc-apq8084"); 3409