1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 4 */ 5 6#include <linux/clk-provider.h> 7#include <linux/err.h> 8#include <linux/kernel.h> 9#include <linux/module.h> 10#include <linux/of_device.h> 11#include <linux/of.h> 12#include <linux/regmap.h> 13 14#include <dt-bindings/clock/qcom,gcc-sm8250.h> 15 16#include "clk-alpha-pll.h" 17#include "clk-branch.h" 18#include "clk-rcg.h" 19#include "clk-regmap.h" 20#include "clk-regmap-divider.h" 21#include "common.h" 22#include "gdsc.h" 23#include "reset.h" 24 25enum { 26 P_BI_TCXO, 27 P_AUD_REF_CLK, 28 P_CORE_BI_PLL_TEST_SE, 29 P_GPLL0_OUT_EVEN, 30 P_GPLL0_OUT_MAIN, 31 P_GPLL4_OUT_MAIN, 32 P_GPLL9_OUT_MAIN, 33 P_SLEEP_CLK, 34}; 35 36static struct clk_alpha_pll gpll0 = { 37 .offset = 0x0, 38 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 39 .clkr = { 40 .enable_reg = 0x52018, 41 .enable_mask = BIT(0), 42 .hw.init = &(struct clk_init_data){ 43 .name = "gpll0", 44 .parent_data = &(const struct clk_parent_data){ 45 .fw_name = "bi_tcxo", 46 }, 47 .num_parents = 1, 48 .ops = &clk_alpha_pll_fixed_lucid_ops, 49 }, 50 }, 51}; 52 53static const struct clk_div_table post_div_table_gpll0_out_even[] = { 54 { 0x1, 2 }, 55 { } 56}; 57 58static struct clk_alpha_pll_postdiv gpll0_out_even = { 59 .offset = 0x0, 60 .post_div_shift = 8, 61 .post_div_table = post_div_table_gpll0_out_even, 62 .num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_even), 63 .width = 4, 64 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 65 .clkr.hw.init = &(struct clk_init_data){ 66 .name = "gpll0_out_even", 67 .parent_data = &(const struct clk_parent_data){ 68 .hw = &gpll0.clkr.hw, 69 }, 70 .num_parents = 1, 71 .ops = &clk_alpha_pll_postdiv_lucid_ops, 72 }, 73}; 74 75static struct clk_alpha_pll gpll4 = { 76 .offset = 0x76000, 77 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 78 .clkr = { 79 .enable_reg = 0x52018, 80 .enable_mask = BIT(4), 81 .hw.init = &(struct clk_init_data){ 82 .name = "gpll4", 83 .parent_data = &(const struct clk_parent_data){ 84 .fw_name = "bi_tcxo", 85 }, 86 .num_parents = 1, 87 .ops = &clk_alpha_pll_fixed_lucid_ops, 88 }, 89 }, 90}; 91 92static struct clk_alpha_pll gpll9 = { 93 .offset = 0x1c000, 94 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 95 .clkr = { 96 .enable_reg = 0x52018, 97 .enable_mask = BIT(9), 98 .hw.init = &(struct clk_init_data){ 99 .name = "gpll9", 100 .parent_data = &(const struct clk_parent_data){ 101 .fw_name = "bi_tcxo", 102 }, 103 .num_parents = 1, 104 .ops = &clk_alpha_pll_fixed_lucid_ops, 105 }, 106 }, 107}; 108 109static const struct parent_map gcc_parent_map_0[] = { 110 { P_BI_TCXO, 0 }, 111 { P_GPLL0_OUT_MAIN, 1 }, 112 { P_GPLL0_OUT_EVEN, 6 }, 113}; 114 115static const struct clk_parent_data gcc_parent_data_0[] = { 116 { .fw_name = "bi_tcxo" }, 117 { .hw = &gpll0.clkr.hw }, 118 { .hw = &gpll0_out_even.clkr.hw }, 119}; 120 121static const struct clk_parent_data gcc_parent_data_0_ao[] = { 122 { .fw_name = "bi_tcxo_ao" }, 123 { .hw = &gpll0.clkr.hw }, 124 { .hw = &gpll0_out_even.clkr.hw }, 125}; 126 127static const struct parent_map gcc_parent_map_1[] = { 128 { P_BI_TCXO, 0 }, 129 { P_GPLL0_OUT_MAIN, 1 }, 130 { P_SLEEP_CLK, 5 }, 131 { P_GPLL0_OUT_EVEN, 6 }, 132}; 133 134static const struct clk_parent_data gcc_parent_data_1[] = { 135 { .fw_name = "bi_tcxo" }, 136 { .hw = &gpll0.clkr.hw }, 137 { .fw_name = "sleep_clk" }, 138 { .hw = &gpll0_out_even.clkr.hw }, 139}; 140 141static const struct parent_map gcc_parent_map_2[] = { 142 { P_BI_TCXO, 0 }, 143 { P_SLEEP_CLK, 5 }, 144}; 145 146static const struct clk_parent_data gcc_parent_data_2[] = { 147 { .fw_name = "bi_tcxo" }, 148 { .fw_name = "sleep_clk" }, 149}; 150 151static const struct parent_map gcc_parent_map_3[] = { 152 { P_BI_TCXO, 0 }, 153}; 154 155static const struct clk_parent_data gcc_parent_data_3[] = { 156 { .fw_name = "bi_tcxo" }, 157}; 158 159static const struct parent_map gcc_parent_map_4[] = { 160 { P_BI_TCXO, 0 }, 161 { P_GPLL0_OUT_MAIN, 1 }, 162 { P_GPLL9_OUT_MAIN, 2 }, 163 { P_GPLL4_OUT_MAIN, 5 }, 164 { P_GPLL0_OUT_EVEN, 6 }, 165}; 166 167static const struct clk_parent_data gcc_parent_data_4[] = { 168 { .fw_name = "bi_tcxo" }, 169 { .hw = &gpll0.clkr.hw }, 170 { .hw = &gpll9.clkr.hw }, 171 { .hw = &gpll4.clkr.hw }, 172 { .hw = &gpll0_out_even.clkr.hw }, 173}; 174 175static const struct parent_map gcc_parent_map_5[] = { 176 { P_BI_TCXO, 0 }, 177 { P_GPLL0_OUT_MAIN, 1 }, 178 { P_AUD_REF_CLK, 2 }, 179 { P_GPLL0_OUT_EVEN, 6 }, 180}; 181 182static const struct clk_parent_data gcc_parent_data_5[] = { 183 { .fw_name = "bi_tcxo" }, 184 { .hw = &gpll0.clkr.hw }, 185 { .fw_name = "aud_ref_clk" }, 186 { .hw = &gpll0_out_even.clkr.hw }, 187}; 188 189static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = { 190 F(19200000, P_BI_TCXO, 1, 0, 0), 191 { } 192}; 193 194static struct clk_rcg2 gcc_cpuss_ahb_clk_src = { 195 .cmd_rcgr = 0x48010, 196 .mnd_width = 0, 197 .hid_width = 5, 198 .parent_map = gcc_parent_map_0, 199 .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src, 200 .clkr.hw.init = &(struct clk_init_data){ 201 .name = "gcc_cpuss_ahb_clk_src", 202 .parent_data = gcc_parent_data_0_ao, 203 .num_parents = ARRAY_SIZE(gcc_parent_data_0_ao), 204 .flags = CLK_SET_RATE_PARENT, 205 .ops = &clk_rcg2_ops, 206 }, 207}; 208 209static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { 210 F(19200000, P_BI_TCXO, 1, 0, 0), 211 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), 212 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), 213 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 214 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), 215 { } 216}; 217 218static struct clk_rcg2 gcc_gp1_clk_src = { 219 .cmd_rcgr = 0x64004, 220 .mnd_width = 8, 221 .hid_width = 5, 222 .parent_map = gcc_parent_map_1, 223 .freq_tbl = ftbl_gcc_gp1_clk_src, 224 .clkr.hw.init = &(struct clk_init_data){ 225 .name = "gcc_gp1_clk_src", 226 .parent_data = gcc_parent_data_1, 227 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 228 .ops = &clk_rcg2_ops, 229 }, 230}; 231 232static struct clk_rcg2 gcc_gp2_clk_src = { 233 .cmd_rcgr = 0x65004, 234 .mnd_width = 8, 235 .hid_width = 5, 236 .parent_map = gcc_parent_map_1, 237 .freq_tbl = ftbl_gcc_gp1_clk_src, 238 .clkr.hw.init = &(struct clk_init_data){ 239 .name = "gcc_gp2_clk_src", 240 .parent_data = gcc_parent_data_1, 241 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 242 .ops = &clk_rcg2_ops, 243 }, 244}; 245 246static struct clk_rcg2 gcc_gp3_clk_src = { 247 .cmd_rcgr = 0x66004, 248 .mnd_width = 8, 249 .hid_width = 5, 250 .parent_map = gcc_parent_map_1, 251 .freq_tbl = ftbl_gcc_gp1_clk_src, 252 .clkr.hw.init = &(struct clk_init_data){ 253 .name = "gcc_gp3_clk_src", 254 .parent_data = gcc_parent_data_1, 255 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 256 .ops = &clk_rcg2_ops, 257 }, 258}; 259 260static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = { 261 F(9600000, P_BI_TCXO, 2, 0, 0), 262 F(19200000, P_BI_TCXO, 1, 0, 0), 263 { } 264}; 265 266static struct clk_rcg2 gcc_pcie_0_aux_clk_src = { 267 .cmd_rcgr = 0x6b038, 268 .mnd_width = 16, 269 .hid_width = 5, 270 .parent_map = gcc_parent_map_2, 271 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 272 .clkr.hw.init = &(struct clk_init_data){ 273 .name = "gcc_pcie_0_aux_clk_src", 274 .parent_data = gcc_parent_data_2, 275 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 276 .ops = &clk_rcg2_ops, 277 }, 278}; 279 280static struct clk_rcg2 gcc_pcie_1_aux_clk_src = { 281 .cmd_rcgr = 0x8d038, 282 .mnd_width = 16, 283 .hid_width = 5, 284 .parent_map = gcc_parent_map_2, 285 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 286 .clkr.hw.init = &(struct clk_init_data){ 287 .name = "gcc_pcie_1_aux_clk_src", 288 .parent_data = gcc_parent_data_2, 289 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 290 .ops = &clk_rcg2_ops, 291 }, 292}; 293 294static struct clk_rcg2 gcc_pcie_2_aux_clk_src = { 295 .cmd_rcgr = 0x6038, 296 .mnd_width = 16, 297 .hid_width = 5, 298 .parent_map = gcc_parent_map_2, 299 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 300 .clkr.hw.init = &(struct clk_init_data){ 301 .name = "gcc_pcie_2_aux_clk_src", 302 .parent_data = gcc_parent_data_2, 303 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 304 .ops = &clk_rcg2_ops, 305 }, 306}; 307 308static const struct freq_tbl ftbl_gcc_pcie_phy_refgen_clk_src[] = { 309 F(19200000, P_BI_TCXO, 1, 0, 0), 310 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 311 { } 312}; 313 314static struct clk_rcg2 gcc_pcie_phy_refgen_clk_src = { 315 .cmd_rcgr = 0x6f014, 316 .mnd_width = 0, 317 .hid_width = 5, 318 .parent_map = gcc_parent_map_0, 319 .freq_tbl = ftbl_gcc_pcie_phy_refgen_clk_src, 320 .clkr.hw.init = &(struct clk_init_data){ 321 .name = "gcc_pcie_phy_refgen_clk_src", 322 .parent_data = gcc_parent_data_0_ao, 323 .num_parents = ARRAY_SIZE(gcc_parent_data_0_ao), 324 .ops = &clk_rcg2_ops, 325 }, 326}; 327 328static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { 329 F(9600000, P_BI_TCXO, 2, 0, 0), 330 F(19200000, P_BI_TCXO, 1, 0, 0), 331 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), 332 { } 333}; 334 335static struct clk_rcg2 gcc_pdm2_clk_src = { 336 .cmd_rcgr = 0x33010, 337 .mnd_width = 0, 338 .hid_width = 5, 339 .parent_map = gcc_parent_map_0, 340 .freq_tbl = ftbl_gcc_pdm2_clk_src, 341 .clkr.hw.init = &(struct clk_init_data){ 342 .name = "gcc_pdm2_clk_src", 343 .parent_data = gcc_parent_data_0, 344 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 345 .ops = &clk_rcg2_ops, 346 }, 347}; 348 349static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { 350 F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625), 351 F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625), 352 F(19200000, P_BI_TCXO, 1, 0, 0), 353 F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625), 354 F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75), 355 F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25), 356 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), 357 F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75), 358 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), 359 F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15), 360 F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25), 361 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 362 F(102400000, P_GPLL0_OUT_EVEN, 1, 128, 375), 363 F(112000000, P_GPLL0_OUT_EVEN, 1, 28, 75), 364 F(117964800, P_GPLL0_OUT_EVEN, 1, 6144, 15625), 365 F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0), 366 { } 367}; 368 369static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = { 370 .name = "gcc_qupv3_wrap0_s0_clk_src", 371 .parent_data = gcc_parent_data_0, 372 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 373 .ops = &clk_rcg2_ops, 374}; 375 376static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { 377 .cmd_rcgr = 0x17010, 378 .mnd_width = 16, 379 .hid_width = 5, 380 .parent_map = gcc_parent_map_0, 381 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 382 .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init, 383}; 384 385static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = { 386 .name = "gcc_qupv3_wrap0_s1_clk_src", 387 .parent_data = gcc_parent_data_0, 388 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 389 .ops = &clk_rcg2_ops, 390}; 391 392static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { 393 .cmd_rcgr = 0x17140, 394 .mnd_width = 16, 395 .hid_width = 5, 396 .parent_map = gcc_parent_map_0, 397 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 398 .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init, 399}; 400 401static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s2_clk_src[] = { 402 F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625), 403 F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625), 404 F(19200000, P_BI_TCXO, 1, 0, 0), 405 F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625), 406 F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75), 407 F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25), 408 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), 409 F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75), 410 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), 411 F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15), 412 F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25), 413 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 414 { } 415}; 416 417static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = { 418 .name = "gcc_qupv3_wrap0_s2_clk_src", 419 .parent_data = gcc_parent_data_0, 420 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 421 .ops = &clk_rcg2_ops, 422}; 423 424static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { 425 .cmd_rcgr = 0x17270, 426 .mnd_width = 16, 427 .hid_width = 5, 428 .parent_map = gcc_parent_map_0, 429 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 430 .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init, 431}; 432 433static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = { 434 .name = "gcc_qupv3_wrap0_s3_clk_src", 435 .parent_data = gcc_parent_data_0, 436 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 437 .ops = &clk_rcg2_ops, 438}; 439 440static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { 441 .cmd_rcgr = 0x173a0, 442 .mnd_width = 16, 443 .hid_width = 5, 444 .parent_map = gcc_parent_map_0, 445 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 446 .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init, 447}; 448 449static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = { 450 .name = "gcc_qupv3_wrap0_s4_clk_src", 451 .parent_data = gcc_parent_data_0, 452 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 453 .ops = &clk_rcg2_ops, 454}; 455 456static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { 457 .cmd_rcgr = 0x174d0, 458 .mnd_width = 16, 459 .hid_width = 5, 460 .parent_map = gcc_parent_map_0, 461 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 462 .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init, 463}; 464 465static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = { 466 .name = "gcc_qupv3_wrap0_s5_clk_src", 467 .parent_data = gcc_parent_data_0, 468 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 469 .ops = &clk_rcg2_ops, 470}; 471 472static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { 473 .cmd_rcgr = 0x17600, 474 .mnd_width = 16, 475 .hid_width = 5, 476 .parent_map = gcc_parent_map_0, 477 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 478 .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init, 479}; 480 481static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = { 482 .name = "gcc_qupv3_wrap0_s6_clk_src", 483 .parent_data = gcc_parent_data_0, 484 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 485 .ops = &clk_rcg2_ops, 486}; 487 488static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = { 489 .cmd_rcgr = 0x17730, 490 .mnd_width = 16, 491 .hid_width = 5, 492 .parent_map = gcc_parent_map_0, 493 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 494 .clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init, 495}; 496 497static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = { 498 .name = "gcc_qupv3_wrap0_s7_clk_src", 499 .parent_data = gcc_parent_data_0, 500 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 501 .ops = &clk_rcg2_ops, 502}; 503 504static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = { 505 .cmd_rcgr = 0x17860, 506 .mnd_width = 16, 507 .hid_width = 5, 508 .parent_map = gcc_parent_map_0, 509 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 510 .clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init, 511}; 512 513static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = { 514 .name = "gcc_qupv3_wrap1_s0_clk_src", 515 .parent_data = gcc_parent_data_0, 516 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 517 .ops = &clk_rcg2_ops, 518}; 519 520static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { 521 .cmd_rcgr = 0x18010, 522 .mnd_width = 16, 523 .hid_width = 5, 524 .parent_map = gcc_parent_map_0, 525 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 526 .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init, 527}; 528 529static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = { 530 .name = "gcc_qupv3_wrap1_s1_clk_src", 531 .parent_data = gcc_parent_data_0, 532 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 533 .ops = &clk_rcg2_ops, 534}; 535 536static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { 537 .cmd_rcgr = 0x18140, 538 .mnd_width = 16, 539 .hid_width = 5, 540 .parent_map = gcc_parent_map_0, 541 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 542 .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init, 543}; 544 545static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = { 546 .name = "gcc_qupv3_wrap1_s2_clk_src", 547 .parent_data = gcc_parent_data_0, 548 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 549 .ops = &clk_rcg2_ops, 550}; 551 552static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = { 553 .cmd_rcgr = 0x18270, 554 .mnd_width = 16, 555 .hid_width = 5, 556 .parent_map = gcc_parent_map_0, 557 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 558 .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init, 559}; 560 561static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = { 562 .name = "gcc_qupv3_wrap1_s3_clk_src", 563 .parent_data = gcc_parent_data_0, 564 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 565 .ops = &clk_rcg2_ops, 566}; 567 568static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { 569 .cmd_rcgr = 0x183a0, 570 .mnd_width = 16, 571 .hid_width = 5, 572 .parent_map = gcc_parent_map_0, 573 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 574 .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init, 575}; 576 577static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = { 578 .name = "gcc_qupv3_wrap1_s4_clk_src", 579 .parent_data = gcc_parent_data_0, 580 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 581 .ops = &clk_rcg2_ops, 582}; 583 584static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { 585 .cmd_rcgr = 0x184d0, 586 .mnd_width = 16, 587 .hid_width = 5, 588 .parent_map = gcc_parent_map_0, 589 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 590 .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init, 591}; 592 593static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = { 594 .name = "gcc_qupv3_wrap1_s5_clk_src", 595 .parent_data = gcc_parent_data_0, 596 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 597 .ops = &clk_rcg2_ops, 598}; 599 600static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { 601 .cmd_rcgr = 0x18600, 602 .mnd_width = 16, 603 .hid_width = 5, 604 .parent_map = gcc_parent_map_0, 605 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 606 .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init, 607}; 608 609static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = { 610 .name = "gcc_qupv3_wrap2_s0_clk_src", 611 .parent_data = gcc_parent_data_0, 612 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 613 .ops = &clk_rcg2_ops, 614}; 615 616static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = { 617 .cmd_rcgr = 0x1e010, 618 .mnd_width = 16, 619 .hid_width = 5, 620 .parent_map = gcc_parent_map_0, 621 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 622 .clkr.hw.init = &gcc_qupv3_wrap2_s0_clk_src_init, 623}; 624 625static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = { 626 .name = "gcc_qupv3_wrap2_s1_clk_src", 627 .parent_data = gcc_parent_data_0, 628 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 629 .ops = &clk_rcg2_ops, 630}; 631 632static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = { 633 .cmd_rcgr = 0x1e140, 634 .mnd_width = 16, 635 .hid_width = 5, 636 .parent_map = gcc_parent_map_0, 637 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 638 .clkr.hw.init = &gcc_qupv3_wrap2_s1_clk_src_init, 639}; 640 641static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = { 642 .name = "gcc_qupv3_wrap2_s2_clk_src", 643 .parent_data = gcc_parent_data_0, 644 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 645 .ops = &clk_rcg2_ops, 646}; 647 648static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = { 649 .cmd_rcgr = 0x1e270, 650 .mnd_width = 16, 651 .hid_width = 5, 652 .parent_map = gcc_parent_map_0, 653 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 654 .clkr.hw.init = &gcc_qupv3_wrap2_s2_clk_src_init, 655}; 656 657static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = { 658 .name = "gcc_qupv3_wrap2_s3_clk_src", 659 .parent_data = gcc_parent_data_0, 660 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 661 .ops = &clk_rcg2_ops, 662}; 663 664static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = { 665 .cmd_rcgr = 0x1e3a0, 666 .mnd_width = 16, 667 .hid_width = 5, 668 .parent_map = gcc_parent_map_0, 669 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 670 .clkr.hw.init = &gcc_qupv3_wrap2_s3_clk_src_init, 671}; 672 673static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = { 674 .name = "gcc_qupv3_wrap2_s4_clk_src", 675 .parent_data = gcc_parent_data_0, 676 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 677 .ops = &clk_rcg2_ops, 678}; 679 680static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = { 681 .cmd_rcgr = 0x1e4d0, 682 .mnd_width = 16, 683 .hid_width = 5, 684 .parent_map = gcc_parent_map_0, 685 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 686 .clkr.hw.init = &gcc_qupv3_wrap2_s4_clk_src_init, 687}; 688 689static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = { 690 .name = "gcc_qupv3_wrap2_s5_clk_src", 691 .parent_data = gcc_parent_data_0, 692 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 693 .ops = &clk_rcg2_ops, 694}; 695 696static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = { 697 .cmd_rcgr = 0x1e600, 698 .mnd_width = 16, 699 .hid_width = 5, 700 .parent_map = gcc_parent_map_0, 701 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 702 .clkr.hw.init = &gcc_qupv3_wrap2_s5_clk_src_init, 703}; 704 705static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { 706 F(400000, P_BI_TCXO, 12, 1, 4), 707 F(19200000, P_BI_TCXO, 1, 0, 0), 708 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), 709 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), 710 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 711 F(202000000, P_GPLL9_OUT_MAIN, 4, 0, 0), 712 { } 713}; 714 715static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { 716 .cmd_rcgr = 0x1400c, 717 .mnd_width = 8, 718 .hid_width = 5, 719 .parent_map = gcc_parent_map_4, 720 .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src, 721 .clkr.hw.init = &(struct clk_init_data){ 722 .name = "gcc_sdcc2_apps_clk_src", 723 .parent_data = gcc_parent_data_4, 724 .num_parents = ARRAY_SIZE(gcc_parent_data_4), 725 .flags = CLK_OPS_PARENT_ENABLE, 726 .ops = &clk_rcg2_floor_ops, 727 }, 728}; 729 730static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = { 731 F(400000, P_BI_TCXO, 12, 1, 4), 732 F(19200000, P_BI_TCXO, 1, 0, 0), 733 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), 734 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), 735 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 736 { } 737}; 738 739static struct clk_rcg2 gcc_sdcc4_apps_clk_src = { 740 .cmd_rcgr = 0x1600c, 741 .mnd_width = 8, 742 .hid_width = 5, 743 .parent_map = gcc_parent_map_0, 744 .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src, 745 .clkr.hw.init = &(struct clk_init_data){ 746 .name = "gcc_sdcc4_apps_clk_src", 747 .parent_data = gcc_parent_data_0, 748 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 749 .ops = &clk_rcg2_floor_ops, 750 }, 751}; 752 753static const struct freq_tbl ftbl_gcc_tsif_ref_clk_src[] = { 754 F(105495, P_BI_TCXO, 2, 1, 91), 755 { } 756}; 757 758static struct clk_rcg2 gcc_tsif_ref_clk_src = { 759 .cmd_rcgr = 0x36010, 760 .mnd_width = 8, 761 .hid_width = 5, 762 .parent_map = gcc_parent_map_5, 763 .freq_tbl = ftbl_gcc_tsif_ref_clk_src, 764 .clkr.hw.init = &(struct clk_init_data){ 765 .name = "gcc_tsif_ref_clk_src", 766 .parent_data = gcc_parent_data_5, 767 .num_parents = ARRAY_SIZE(gcc_parent_data_5), 768 .ops = &clk_rcg2_ops, 769 }, 770}; 771 772static const struct freq_tbl ftbl_gcc_ufs_card_axi_clk_src[] = { 773 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), 774 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), 775 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 776 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), 777 { } 778}; 779 780static struct clk_rcg2 gcc_ufs_card_axi_clk_src = { 781 .cmd_rcgr = 0x75024, 782 .mnd_width = 8, 783 .hid_width = 5, 784 .parent_map = gcc_parent_map_0, 785 .freq_tbl = ftbl_gcc_ufs_card_axi_clk_src, 786 .clkr.hw.init = &(struct clk_init_data){ 787 .name = "gcc_ufs_card_axi_clk_src", 788 .parent_data = gcc_parent_data_0, 789 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 790 .ops = &clk_rcg2_ops, 791 }, 792}; 793 794static const struct freq_tbl ftbl_gcc_ufs_card_ice_core_clk_src[] = { 795 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), 796 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), 797 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), 798 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), 799 { } 800}; 801 802static struct clk_rcg2 gcc_ufs_card_ice_core_clk_src = { 803 .cmd_rcgr = 0x7506c, 804 .mnd_width = 0, 805 .hid_width = 5, 806 .parent_map = gcc_parent_map_0, 807 .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src, 808 .clkr.hw.init = &(struct clk_init_data){ 809 .name = "gcc_ufs_card_ice_core_clk_src", 810 .parent_data = gcc_parent_data_0, 811 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 812 .ops = &clk_rcg2_ops, 813 }, 814}; 815 816static const struct freq_tbl ftbl_gcc_ufs_card_phy_aux_clk_src[] = { 817 F(19200000, P_BI_TCXO, 1, 0, 0), 818 { } 819}; 820 821static struct clk_rcg2 gcc_ufs_card_phy_aux_clk_src = { 822 .cmd_rcgr = 0x750a0, 823 .mnd_width = 0, 824 .hid_width = 5, 825 .parent_map = gcc_parent_map_3, 826 .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src, 827 .clkr.hw.init = &(struct clk_init_data){ 828 .name = "gcc_ufs_card_phy_aux_clk_src", 829 .parent_data = gcc_parent_data_3, 830 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 831 .ops = &clk_rcg2_ops, 832 }, 833}; 834 835static const struct freq_tbl ftbl_gcc_ufs_card_unipro_core_clk_src[] = { 836 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), 837 F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0), 838 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), 839 { } 840}; 841 842static struct clk_rcg2 gcc_ufs_card_unipro_core_clk_src = { 843 .cmd_rcgr = 0x75084, 844 .mnd_width = 0, 845 .hid_width = 5, 846 .parent_map = gcc_parent_map_0, 847 .freq_tbl = ftbl_gcc_ufs_card_unipro_core_clk_src, 848 .clkr.hw.init = &(struct clk_init_data){ 849 .name = "gcc_ufs_card_unipro_core_clk_src", 850 .parent_data = gcc_parent_data_0, 851 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 852 .ops = &clk_rcg2_ops, 853 }, 854}; 855 856static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = { 857 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), 858 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), 859 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), 860 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), 861 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), 862 { } 863}; 864 865static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { 866 .cmd_rcgr = 0x77024, 867 .mnd_width = 8, 868 .hid_width = 5, 869 .parent_map = gcc_parent_map_0, 870 .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src, 871 .clkr.hw.init = &(struct clk_init_data){ 872 .name = "gcc_ufs_phy_axi_clk_src", 873 .parent_data = gcc_parent_data_0, 874 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 875 .ops = &clk_rcg2_ops, 876 }, 877}; 878 879static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = { 880 .cmd_rcgr = 0x7706c, 881 .mnd_width = 0, 882 .hid_width = 5, 883 .parent_map = gcc_parent_map_0, 884 .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src, 885 .clkr.hw.init = &(struct clk_init_data){ 886 .name = "gcc_ufs_phy_ice_core_clk_src", 887 .parent_data = gcc_parent_data_0, 888 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 889 .ops = &clk_rcg2_ops, 890 }, 891}; 892 893static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = { 894 .cmd_rcgr = 0x770a0, 895 .mnd_width = 0, 896 .hid_width = 5, 897 .parent_map = gcc_parent_map_3, 898 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 899 .clkr.hw.init = &(struct clk_init_data){ 900 .name = "gcc_ufs_phy_phy_aux_clk_src", 901 .parent_data = gcc_parent_data_3, 902 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 903 .ops = &clk_rcg2_ops, 904 }, 905}; 906 907static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = { 908 .cmd_rcgr = 0x77084, 909 .mnd_width = 0, 910 .hid_width = 5, 911 .parent_map = gcc_parent_map_0, 912 .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src, 913 .clkr.hw.init = &(struct clk_init_data){ 914 .name = "gcc_ufs_phy_unipro_core_clk_src", 915 .parent_data = gcc_parent_data_0, 916 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 917 .ops = &clk_rcg2_ops, 918 }, 919}; 920 921static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { 922 F(33333333, P_GPLL0_OUT_EVEN, 9, 0, 0), 923 F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0), 924 F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0), 925 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), 926 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), 927 { } 928}; 929 930static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { 931 .cmd_rcgr = 0xf020, 932 .mnd_width = 8, 933 .hid_width = 5, 934 .parent_map = gcc_parent_map_0, 935 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, 936 .clkr.hw.init = &(struct clk_init_data){ 937 .name = "gcc_usb30_prim_master_clk_src", 938 .parent_data = gcc_parent_data_0, 939 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 940 .ops = &clk_rcg2_ops, 941 }, 942}; 943 944static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { 945 .cmd_rcgr = 0xf038, 946 .mnd_width = 0, 947 .hid_width = 5, 948 .parent_map = gcc_parent_map_0, 949 .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src, 950 .clkr.hw.init = &(struct clk_init_data){ 951 .name = "gcc_usb30_prim_mock_utmi_clk_src", 952 .parent_data = gcc_parent_data_0, 953 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 954 .ops = &clk_rcg2_ops, 955 }, 956}; 957 958static struct clk_rcg2 gcc_usb30_sec_master_clk_src = { 959 .cmd_rcgr = 0x10020, 960 .mnd_width = 8, 961 .hid_width = 5, 962 .parent_map = gcc_parent_map_0, 963 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, 964 .clkr.hw.init = &(struct clk_init_data){ 965 .name = "gcc_usb30_sec_master_clk_src", 966 .parent_data = gcc_parent_data_0, 967 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 968 .ops = &clk_rcg2_ops, 969 }, 970}; 971 972static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = { 973 .cmd_rcgr = 0x10038, 974 .mnd_width = 0, 975 .hid_width = 5, 976 .parent_map = gcc_parent_map_0, 977 .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src, 978 .clkr.hw.init = &(struct clk_init_data){ 979 .name = "gcc_usb30_sec_mock_utmi_clk_src", 980 .parent_data = gcc_parent_data_0, 981 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 982 .ops = &clk_rcg2_ops, 983 }, 984}; 985 986static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { 987 .cmd_rcgr = 0xf064, 988 .mnd_width = 0, 989 .hid_width = 5, 990 .parent_map = gcc_parent_map_2, 991 .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src, 992 .clkr.hw.init = &(struct clk_init_data){ 993 .name = "gcc_usb3_prim_phy_aux_clk_src", 994 .parent_data = gcc_parent_data_2, 995 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 996 .ops = &clk_rcg2_ops, 997 }, 998}; 999 1000static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = { 1001 .cmd_rcgr = 0x10064, 1002 .mnd_width = 0, 1003 .hid_width = 5, 1004 .parent_map = gcc_parent_map_2, 1005 .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src, 1006 .clkr.hw.init = &(struct clk_init_data){ 1007 .name = "gcc_usb3_sec_phy_aux_clk_src", 1008 .parent_data = gcc_parent_data_2, 1009 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 1010 .ops = &clk_rcg2_ops, 1011 }, 1012}; 1013 1014static struct clk_regmap_div gcc_cpuss_ahb_postdiv_clk_src = { 1015 .reg = 0x48028, 1016 .shift = 0, 1017 .width = 4, 1018 .clkr.hw.init = &(struct clk_init_data) { 1019 .name = "gcc_cpuss_ahb_postdiv_clk_src", 1020 .parent_data = &(const struct clk_parent_data){ 1021 .hw = &gcc_cpuss_ahb_clk_src.clkr.hw, 1022 }, 1023 .num_parents = 1, 1024 .flags = CLK_SET_RATE_PARENT, 1025 .ops = &clk_regmap_div_ro_ops, 1026 }, 1027}; 1028 1029static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = { 1030 .reg = 0xf050, 1031 .shift = 0, 1032 .width = 2, 1033 .clkr.hw.init = &(struct clk_init_data) { 1034 .name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src", 1035 .parent_data = &(const struct clk_parent_data){ 1036 .hw = &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw, 1037 }, 1038 .num_parents = 1, 1039 .flags = CLK_SET_RATE_PARENT, 1040 .ops = &clk_regmap_div_ro_ops, 1041 }, 1042}; 1043 1044static struct clk_regmap_div gcc_usb30_sec_mock_utmi_postdiv_clk_src = { 1045 .reg = 0x10050, 1046 .shift = 0, 1047 .width = 2, 1048 .clkr.hw.init = &(struct clk_init_data) { 1049 .name = "gcc_usb30_sec_mock_utmi_postdiv_clk_src", 1050 .parent_data = &(const struct clk_parent_data){ 1051 .hw = &gcc_usb30_sec_mock_utmi_clk_src.clkr.hw, 1052 }, 1053 .num_parents = 1, 1054 .flags = CLK_SET_RATE_PARENT, 1055 .ops = &clk_regmap_div_ro_ops, 1056 }, 1057}; 1058 1059static struct clk_branch gcc_aggre_noc_pcie_tbu_clk = { 1060 .halt_reg = 0x9000c, 1061 .halt_check = BRANCH_HALT_VOTED, 1062 .clkr = { 1063 .enable_reg = 0x9000c, 1064 .enable_mask = BIT(0), 1065 .hw.init = &(struct clk_init_data){ 1066 .name = "gcc_aggre_noc_pcie_tbu_clk", 1067 .ops = &clk_branch2_ops, 1068 }, 1069 }, 1070}; 1071 1072static struct clk_branch gcc_aggre_ufs_card_axi_clk = { 1073 .halt_reg = 0x750cc, 1074 .halt_check = BRANCH_HALT_VOTED, 1075 .hwcg_reg = 0x750cc, 1076 .hwcg_bit = 1, 1077 .clkr = { 1078 .enable_reg = 0x750cc, 1079 .enable_mask = BIT(0), 1080 .hw.init = &(struct clk_init_data){ 1081 .name = "gcc_aggre_ufs_card_axi_clk", 1082 .parent_data = &(const struct clk_parent_data){ 1083 .hw = &gcc_ufs_card_axi_clk_src.clkr.hw, 1084 }, 1085 .num_parents = 1, 1086 .flags = CLK_SET_RATE_PARENT, 1087 .ops = &clk_branch2_ops, 1088 }, 1089 }, 1090}; 1091 1092static struct clk_branch gcc_aggre_ufs_phy_axi_clk = { 1093 .halt_reg = 0x770cc, 1094 .halt_check = BRANCH_HALT_VOTED, 1095 .hwcg_reg = 0x770cc, 1096 .hwcg_bit = 1, 1097 .clkr = { 1098 .enable_reg = 0x770cc, 1099 .enable_mask = BIT(0), 1100 .hw.init = &(struct clk_init_data){ 1101 .name = "gcc_aggre_ufs_phy_axi_clk", 1102 .parent_data = &(const struct clk_parent_data){ 1103 .hw = &gcc_ufs_phy_axi_clk_src.clkr.hw, 1104 }, 1105 .num_parents = 1, 1106 .flags = CLK_SET_RATE_PARENT, 1107 .ops = &clk_branch2_ops, 1108 }, 1109 }, 1110}; 1111 1112static struct clk_branch gcc_aggre_usb3_prim_axi_clk = { 1113 .halt_reg = 0xf080, 1114 .halt_check = BRANCH_HALT_VOTED, 1115 .clkr = { 1116 .enable_reg = 0xf080, 1117 .enable_mask = BIT(0), 1118 .hw.init = &(struct clk_init_data){ 1119 .name = "gcc_aggre_usb3_prim_axi_clk", 1120 .parent_data = &(const struct clk_parent_data){ 1121 .hw = &gcc_usb30_prim_master_clk_src.clkr.hw, 1122 }, 1123 .num_parents = 1, 1124 .flags = CLK_SET_RATE_PARENT, 1125 .ops = &clk_branch2_ops, 1126 }, 1127 }, 1128}; 1129 1130static struct clk_branch gcc_aggre_usb3_sec_axi_clk = { 1131 .halt_reg = 0x10080, 1132 .halt_check = BRANCH_HALT_VOTED, 1133 .clkr = { 1134 .enable_reg = 0x10080, 1135 .enable_mask = BIT(0), 1136 .hw.init = &(struct clk_init_data){ 1137 .name = "gcc_aggre_usb3_sec_axi_clk", 1138 .parent_data = &(const struct clk_parent_data){ 1139 .hw = &gcc_usb30_sec_master_clk_src.clkr.hw, 1140 }, 1141 .num_parents = 1, 1142 .flags = CLK_SET_RATE_PARENT, 1143 .ops = &clk_branch2_ops, 1144 }, 1145 }, 1146}; 1147 1148static struct clk_branch gcc_boot_rom_ahb_clk = { 1149 .halt_reg = 0x38004, 1150 .halt_check = BRANCH_HALT_VOTED, 1151 .hwcg_reg = 0x38004, 1152 .hwcg_bit = 1, 1153 .clkr = { 1154 .enable_reg = 0x52000, 1155 .enable_mask = BIT(10), 1156 .hw.init = &(struct clk_init_data){ 1157 .name = "gcc_boot_rom_ahb_clk", 1158 .ops = &clk_branch2_ops, 1159 }, 1160 }, 1161}; 1162 1163static struct clk_branch gcc_camera_hf_axi_clk = { 1164 .halt_reg = 0xb02c, 1165 .halt_check = BRANCH_HALT_VOTED, 1166 .clkr = { 1167 .enable_reg = 0xb02c, 1168 .enable_mask = BIT(0), 1169 .hw.init = &(struct clk_init_data){ 1170 .name = "gcc_camera_hf_axi_clk", 1171 .ops = &clk_branch2_ops, 1172 }, 1173 }, 1174}; 1175 1176static struct clk_branch gcc_camera_sf_axi_clk = { 1177 .halt_reg = 0xb030, 1178 .halt_check = BRANCH_HALT_VOTED, 1179 .clkr = { 1180 .enable_reg = 0xb030, 1181 .enable_mask = BIT(0), 1182 .hw.init = &(struct clk_init_data){ 1183 .name = "gcc_camera_sf_axi_clk", 1184 .ops = &clk_branch2_ops, 1185 }, 1186 }, 1187}; 1188 1189static struct clk_branch gcc_camera_xo_clk = { 1190 .halt_reg = 0xb040, 1191 .halt_check = BRANCH_HALT, 1192 .clkr = { 1193 .enable_reg = 0xb040, 1194 .enable_mask = BIT(0), 1195 .hw.init = &(struct clk_init_data){ 1196 .name = "gcc_camera_xo_clk", 1197 .ops = &clk_branch2_ops, 1198 }, 1199 }, 1200}; 1201 1202static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { 1203 .halt_reg = 0xf07c, 1204 .halt_check = BRANCH_HALT_VOTED, 1205 .clkr = { 1206 .enable_reg = 0xf07c, 1207 .enable_mask = BIT(0), 1208 .hw.init = &(struct clk_init_data){ 1209 .name = "gcc_cfg_noc_usb3_prim_axi_clk", 1210 .parent_data = &(const struct clk_parent_data){ 1211 .hw = &gcc_usb30_prim_master_clk_src.clkr.hw, 1212 }, 1213 .num_parents = 1, 1214 .flags = CLK_SET_RATE_PARENT, 1215 .ops = &clk_branch2_ops, 1216 }, 1217 }, 1218}; 1219 1220static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = { 1221 .halt_reg = 0x1007c, 1222 .halt_check = BRANCH_HALT_VOTED, 1223 .clkr = { 1224 .enable_reg = 0x1007c, 1225 .enable_mask = BIT(0), 1226 .hw.init = &(struct clk_init_data){ 1227 .name = "gcc_cfg_noc_usb3_sec_axi_clk", 1228 .parent_data = &(const struct clk_parent_data){ 1229 .hw = &gcc_usb30_sec_master_clk_src.clkr.hw, 1230 }, 1231 .num_parents = 1, 1232 .flags = CLK_SET_RATE_PARENT, 1233 .ops = &clk_branch2_ops, 1234 }, 1235 }, 1236}; 1237 1238static struct clk_branch gcc_cpuss_ahb_clk = { 1239 .halt_reg = 0x48000, 1240 .halt_check = BRANCH_HALT_VOTED, 1241 .clkr = { 1242 .enable_reg = 0x52000, 1243 .enable_mask = BIT(21), 1244 .hw.init = &(struct clk_init_data){ 1245 .name = "gcc_cpuss_ahb_clk", 1246 .parent_data = &(const struct clk_parent_data){ 1247 .hw = &gcc_cpuss_ahb_postdiv_clk_src.clkr.hw, 1248 }, 1249 .num_parents = 1, 1250 .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 1251 .ops = &clk_branch2_ops, 1252 }, 1253 }, 1254}; 1255 1256static struct clk_branch gcc_cpuss_rbcpr_clk = { 1257 .halt_reg = 0x48004, 1258 .halt_check = BRANCH_HALT, 1259 .clkr = { 1260 .enable_reg = 0x48004, 1261 .enable_mask = BIT(0), 1262 .hw.init = &(struct clk_init_data){ 1263 .name = "gcc_cpuss_rbcpr_clk", 1264 .ops = &clk_branch2_ops, 1265 }, 1266 }, 1267}; 1268 1269static struct clk_branch gcc_ddrss_gpu_axi_clk = { 1270 .halt_reg = 0x71154, 1271 .halt_check = BRANCH_HALT_VOTED, 1272 .clkr = { 1273 .enable_reg = 0x71154, 1274 .enable_mask = BIT(0), 1275 .hw.init = &(struct clk_init_data){ 1276 .name = "gcc_ddrss_gpu_axi_clk", 1277 .ops = &clk_branch2_ops, 1278 }, 1279 }, 1280}; 1281 1282static struct clk_branch gcc_ddrss_pcie_sf_tbu_clk = { 1283 .halt_reg = 0x8d058, 1284 .halt_check = BRANCH_HALT_VOTED, 1285 .clkr = { 1286 .enable_reg = 0x8d058, 1287 .enable_mask = BIT(0), 1288 .hw.init = &(struct clk_init_data){ 1289 .name = "gcc_ddrss_pcie_sf_tbu_clk", 1290 .ops = &clk_branch2_ops, 1291 }, 1292 }, 1293}; 1294 1295static struct clk_branch gcc_disp_hf_axi_clk = { 1296 .halt_reg = 0xb034, 1297 .halt_check = BRANCH_HALT_VOTED, 1298 .clkr = { 1299 .enable_reg = 0xb034, 1300 .enable_mask = BIT(0), 1301 .hw.init = &(struct clk_init_data){ 1302 .name = "gcc_disp_hf_axi_clk", 1303 .ops = &clk_branch2_ops, 1304 }, 1305 }, 1306}; 1307 1308static struct clk_branch gcc_disp_sf_axi_clk = { 1309 .halt_reg = 0xb038, 1310 .halt_check = BRANCH_HALT_VOTED, 1311 .clkr = { 1312 .enable_reg = 0xb038, 1313 .enable_mask = BIT(0), 1314 .hw.init = &(struct clk_init_data){ 1315 .name = "gcc_disp_sf_axi_clk", 1316 .ops = &clk_branch2_ops, 1317 }, 1318 }, 1319}; 1320 1321static struct clk_branch gcc_disp_xo_clk = { 1322 .halt_reg = 0xb044, 1323 .halt_check = BRANCH_HALT, 1324 .clkr = { 1325 .enable_reg = 0xb044, 1326 .enable_mask = BIT(0), 1327 .hw.init = &(struct clk_init_data){ 1328 .name = "gcc_disp_xo_clk", 1329 .ops = &clk_branch2_ops, 1330 }, 1331 }, 1332}; 1333 1334static struct clk_branch gcc_gp1_clk = { 1335 .halt_reg = 0x64000, 1336 .halt_check = BRANCH_HALT, 1337 .clkr = { 1338 .enable_reg = 0x64000, 1339 .enable_mask = BIT(0), 1340 .hw.init = &(struct clk_init_data){ 1341 .name = "gcc_gp1_clk", 1342 .parent_data = &(const struct clk_parent_data){ 1343 .hw = &gcc_gp1_clk_src.clkr.hw, 1344 }, 1345 .num_parents = 1, 1346 .flags = CLK_SET_RATE_PARENT, 1347 .ops = &clk_branch2_ops, 1348 }, 1349 }, 1350}; 1351 1352static struct clk_branch gcc_gp2_clk = { 1353 .halt_reg = 0x65000, 1354 .halt_check = BRANCH_HALT, 1355 .clkr = { 1356 .enable_reg = 0x65000, 1357 .enable_mask = BIT(0), 1358 .hw.init = &(struct clk_init_data){ 1359 .name = "gcc_gp2_clk", 1360 .parent_data = &(const struct clk_parent_data){ 1361 .hw = &gcc_gp2_clk_src.clkr.hw, 1362 }, 1363 .num_parents = 1, 1364 .flags = CLK_SET_RATE_PARENT, 1365 .ops = &clk_branch2_ops, 1366 }, 1367 }, 1368}; 1369 1370static struct clk_branch gcc_gp3_clk = { 1371 .halt_reg = 0x66000, 1372 .halt_check = BRANCH_HALT, 1373 .clkr = { 1374 .enable_reg = 0x66000, 1375 .enable_mask = BIT(0), 1376 .hw.init = &(struct clk_init_data){ 1377 .name = "gcc_gp3_clk", 1378 .parent_data = &(const struct clk_parent_data){ 1379 .hw = &gcc_gp3_clk_src.clkr.hw, 1380 }, 1381 .num_parents = 1, 1382 .flags = CLK_SET_RATE_PARENT, 1383 .ops = &clk_branch2_ops, 1384 }, 1385 }, 1386}; 1387 1388static struct clk_branch gcc_gpu_gpll0_clk_src = { 1389 .halt_check = BRANCH_HALT_DELAY, 1390 .clkr = { 1391 .enable_reg = 0x52000, 1392 .enable_mask = BIT(15), 1393 .hw.init = &(struct clk_init_data){ 1394 .name = "gcc_gpu_gpll0_clk_src", 1395 .parent_data = &(const struct clk_parent_data){ 1396 .hw = &gpll0.clkr.hw, 1397 }, 1398 .num_parents = 1, 1399 .flags = CLK_SET_RATE_PARENT, 1400 .ops = &clk_branch2_ops, 1401 }, 1402 }, 1403}; 1404 1405static struct clk_branch gcc_gpu_gpll0_div_clk_src = { 1406 .halt_check = BRANCH_HALT_DELAY, 1407 .clkr = { 1408 .enable_reg = 0x52000, 1409 .enable_mask = BIT(16), 1410 .hw.init = &(struct clk_init_data){ 1411 .name = "gcc_gpu_gpll0_div_clk_src", 1412 .parent_data = &(const struct clk_parent_data){ 1413 .hw = &gpll0_out_even.clkr.hw, 1414 }, 1415 .num_parents = 1, 1416 .flags = CLK_SET_RATE_PARENT, 1417 .ops = &clk_branch2_ops, 1418 }, 1419 }, 1420}; 1421 1422static struct clk_branch gcc_gpu_iref_en = { 1423 .halt_reg = 0x8c014, 1424 .halt_check = BRANCH_HALT, 1425 .clkr = { 1426 .enable_reg = 0x8c014, 1427 .enable_mask = BIT(0), 1428 .hw.init = &(struct clk_init_data){ 1429 .name = "gcc_gpu_iref_en", 1430 .ops = &clk_branch2_ops, 1431 }, 1432 }, 1433}; 1434 1435static struct clk_branch gcc_gpu_memnoc_gfx_clk = { 1436 .halt_reg = 0x7100c, 1437 .halt_check = BRANCH_HALT_VOTED, 1438 .clkr = { 1439 .enable_reg = 0x7100c, 1440 .enable_mask = BIT(0), 1441 .hw.init = &(struct clk_init_data){ 1442 .name = "gcc_gpu_memnoc_gfx_clk", 1443 .ops = &clk_branch2_ops, 1444 }, 1445 }, 1446}; 1447 1448static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = { 1449 .halt_reg = 0x71018, 1450 .halt_check = BRANCH_HALT, 1451 .clkr = { 1452 .enable_reg = 0x71018, 1453 .enable_mask = BIT(0), 1454 .hw.init = &(struct clk_init_data){ 1455 .name = "gcc_gpu_snoc_dvm_gfx_clk", 1456 .ops = &clk_branch2_ops, 1457 }, 1458 }, 1459}; 1460 1461static struct clk_branch gcc_npu_axi_clk = { 1462 .halt_reg = 0x4d008, 1463 .halt_check = BRANCH_HALT_VOTED, 1464 .clkr = { 1465 .enable_reg = 0x4d008, 1466 .enable_mask = BIT(0), 1467 .hw.init = &(struct clk_init_data){ 1468 .name = "gcc_npu_axi_clk", 1469 .ops = &clk_branch2_ops, 1470 }, 1471 }, 1472}; 1473 1474static struct clk_branch gcc_npu_bwmon_axi_clk = { 1475 .halt_reg = 0x73008, 1476 .halt_check = BRANCH_HALT_VOTED, 1477 .clkr = { 1478 .enable_reg = 0x73008, 1479 .enable_mask = BIT(0), 1480 .hw.init = &(struct clk_init_data){ 1481 .name = "gcc_npu_bwmon_axi_clk", 1482 .ops = &clk_branch2_ops, 1483 }, 1484 }, 1485}; 1486 1487static struct clk_branch gcc_npu_bwmon_cfg_ahb_clk = { 1488 .halt_reg = 0x73004, 1489 .halt_check = BRANCH_HALT, 1490 .clkr = { 1491 .enable_reg = 0x73004, 1492 .enable_mask = BIT(0), 1493 .hw.init = &(struct clk_init_data){ 1494 .name = "gcc_npu_bwmon_cfg_ahb_clk", 1495 .ops = &clk_branch2_ops, 1496 }, 1497 }, 1498}; 1499 1500static struct clk_branch gcc_npu_cfg_ahb_clk = { 1501 .halt_reg = 0x4d004, 1502 .halt_check = BRANCH_HALT, 1503 .hwcg_reg = 0x4d004, 1504 .hwcg_bit = 1, 1505 .clkr = { 1506 .enable_reg = 0x4d004, 1507 .enable_mask = BIT(0), 1508 .hw.init = &(struct clk_init_data){ 1509 .name = "gcc_npu_cfg_ahb_clk", 1510 .ops = &clk_branch2_ops, 1511 }, 1512 }, 1513}; 1514 1515static struct clk_branch gcc_npu_dma_clk = { 1516 .halt_reg = 0x4d00c, 1517 .halt_check = BRANCH_HALT_VOTED, 1518 .clkr = { 1519 .enable_reg = 0x4d00c, 1520 .enable_mask = BIT(0), 1521 .hw.init = &(struct clk_init_data){ 1522 .name = "gcc_npu_dma_clk", 1523 .ops = &clk_branch2_ops, 1524 }, 1525 }, 1526}; 1527 1528static struct clk_branch gcc_npu_gpll0_clk_src = { 1529 .halt_check = BRANCH_HALT_DELAY, 1530 .clkr = { 1531 .enable_reg = 0x52000, 1532 .enable_mask = BIT(18), 1533 .hw.init = &(struct clk_init_data){ 1534 .name = "gcc_npu_gpll0_clk_src", 1535 .parent_data = &(const struct clk_parent_data){ 1536 .hw = &gpll0.clkr.hw, 1537 }, 1538 .num_parents = 1, 1539 .flags = CLK_SET_RATE_PARENT, 1540 .ops = &clk_branch2_ops, 1541 }, 1542 }, 1543}; 1544 1545static struct clk_branch gcc_npu_gpll0_div_clk_src = { 1546 .halt_check = BRANCH_HALT_DELAY, 1547 .clkr = { 1548 .enable_reg = 0x52000, 1549 .enable_mask = BIT(19), 1550 .hw.init = &(struct clk_init_data){ 1551 .name = "gcc_npu_gpll0_div_clk_src", 1552 .parent_data = &(const struct clk_parent_data){ 1553 .hw = &gpll0_out_even.clkr.hw, 1554 }, 1555 .num_parents = 1, 1556 .flags = CLK_SET_RATE_PARENT, 1557 .ops = &clk_branch2_ops, 1558 }, 1559 }, 1560}; 1561 1562static struct clk_branch gcc_pcie0_phy_refgen_clk = { 1563 .halt_reg = 0x6f02c, 1564 .halt_check = BRANCH_HALT, 1565 .clkr = { 1566 .enable_reg = 0x6f02c, 1567 .enable_mask = BIT(0), 1568 .hw.init = &(struct clk_init_data){ 1569 .name = "gcc_pcie0_phy_refgen_clk", 1570 .parent_data = &(const struct clk_parent_data){ 1571 .hw = &gcc_pcie_phy_refgen_clk_src.clkr.hw, 1572 }, 1573 .num_parents = 1, 1574 .flags = CLK_SET_RATE_PARENT, 1575 .ops = &clk_branch2_ops, 1576 }, 1577 }, 1578}; 1579 1580static struct clk_branch gcc_pcie1_phy_refgen_clk = { 1581 .halt_reg = 0x6f030, 1582 .halt_check = BRANCH_HALT, 1583 .clkr = { 1584 .enable_reg = 0x6f030, 1585 .enable_mask = BIT(0), 1586 .hw.init = &(struct clk_init_data){ 1587 .name = "gcc_pcie1_phy_refgen_clk", 1588 .parent_data = &(const struct clk_parent_data){ 1589 .hw = &gcc_pcie_phy_refgen_clk_src.clkr.hw, 1590 }, 1591 .num_parents = 1, 1592 .flags = CLK_SET_RATE_PARENT, 1593 .ops = &clk_branch2_ops, 1594 }, 1595 }, 1596}; 1597 1598static struct clk_branch gcc_pcie2_phy_refgen_clk = { 1599 .halt_reg = 0x6f034, 1600 .halt_check = BRANCH_HALT, 1601 .clkr = { 1602 .enable_reg = 0x6f034, 1603 .enable_mask = BIT(0), 1604 .hw.init = &(struct clk_init_data){ 1605 .name = "gcc_pcie2_phy_refgen_clk", 1606 .parent_data = &(const struct clk_parent_data){ 1607 .hw = &gcc_pcie_phy_refgen_clk_src.clkr.hw, 1608 }, 1609 .num_parents = 1, 1610 .flags = CLK_SET_RATE_PARENT, 1611 .ops = &clk_branch2_ops, 1612 }, 1613 }, 1614}; 1615 1616static struct clk_branch gcc_pcie_0_aux_clk = { 1617 .halt_reg = 0x6b028, 1618 .halt_check = BRANCH_HALT_VOTED, 1619 .clkr = { 1620 .enable_reg = 0x52008, 1621 .enable_mask = BIT(3), 1622 .hw.init = &(struct clk_init_data){ 1623 .name = "gcc_pcie_0_aux_clk", 1624 .parent_data = &(const struct clk_parent_data){ 1625 .hw = &gcc_pcie_0_aux_clk_src.clkr.hw, 1626 }, 1627 .num_parents = 1, 1628 .flags = CLK_SET_RATE_PARENT, 1629 .ops = &clk_branch2_ops, 1630 }, 1631 }, 1632}; 1633 1634static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { 1635 .halt_reg = 0x6b024, 1636 .halt_check = BRANCH_HALT_VOTED, 1637 .hwcg_reg = 0x6b024, 1638 .hwcg_bit = 1, 1639 .clkr = { 1640 .enable_reg = 0x52008, 1641 .enable_mask = BIT(2), 1642 .hw.init = &(struct clk_init_data){ 1643 .name = "gcc_pcie_0_cfg_ahb_clk", 1644 .ops = &clk_branch2_ops, 1645 }, 1646 }, 1647}; 1648 1649static struct clk_branch gcc_pcie_0_mstr_axi_clk = { 1650 .halt_reg = 0x6b01c, 1651 .halt_check = BRANCH_HALT_VOTED, 1652 .clkr = { 1653 .enable_reg = 0x52008, 1654 .enable_mask = BIT(1), 1655 .hw.init = &(struct clk_init_data){ 1656 .name = "gcc_pcie_0_mstr_axi_clk", 1657 .ops = &clk_branch2_ops, 1658 }, 1659 }, 1660}; 1661 1662static struct clk_branch gcc_pcie_0_pipe_clk = { 1663 .halt_reg = 0x6b02c, 1664 .halt_check = BRANCH_HALT_SKIP, 1665 .clkr = { 1666 .enable_reg = 0x52008, 1667 .enable_mask = BIT(4), 1668 .hw.init = &(struct clk_init_data){ 1669 .name = "gcc_pcie_0_pipe_clk", 1670 .ops = &clk_branch2_ops, 1671 }, 1672 }, 1673}; 1674 1675static struct clk_branch gcc_pcie_0_slv_axi_clk = { 1676 .halt_reg = 0x6b014, 1677 .halt_check = BRANCH_HALT_VOTED, 1678 .hwcg_reg = 0x6b014, 1679 .hwcg_bit = 1, 1680 .clkr = { 1681 .enable_reg = 0x52008, 1682 .enable_mask = BIT(0), 1683 .hw.init = &(struct clk_init_data){ 1684 .name = "gcc_pcie_0_slv_axi_clk", 1685 .ops = &clk_branch2_ops, 1686 }, 1687 }, 1688}; 1689 1690static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = { 1691 .halt_reg = 0x6b010, 1692 .halt_check = BRANCH_HALT_VOTED, 1693 .clkr = { 1694 .enable_reg = 0x52008, 1695 .enable_mask = BIT(5), 1696 .hw.init = &(struct clk_init_data){ 1697 .name = "gcc_pcie_0_slv_q2a_axi_clk", 1698 .ops = &clk_branch2_ops, 1699 }, 1700 }, 1701}; 1702 1703static struct clk_branch gcc_pcie_1_aux_clk = { 1704 .halt_reg = 0x8d028, 1705 .halt_check = BRANCH_HALT_VOTED, 1706 .clkr = { 1707 .enable_reg = 0x52000, 1708 .enable_mask = BIT(29), 1709 .hw.init = &(struct clk_init_data){ 1710 .name = "gcc_pcie_1_aux_clk", 1711 .parent_data = &(const struct clk_parent_data){ 1712 .hw = &gcc_pcie_1_aux_clk_src.clkr.hw, 1713 }, 1714 .num_parents = 1, 1715 .flags = CLK_SET_RATE_PARENT, 1716 .ops = &clk_branch2_ops, 1717 }, 1718 }, 1719}; 1720 1721static struct clk_branch gcc_pcie_1_cfg_ahb_clk = { 1722 .halt_reg = 0x8d024, 1723 .halt_check = BRANCH_HALT_VOTED, 1724 .hwcg_reg = 0x8d024, 1725 .hwcg_bit = 1, 1726 .clkr = { 1727 .enable_reg = 0x52000, 1728 .enable_mask = BIT(28), 1729 .hw.init = &(struct clk_init_data){ 1730 .name = "gcc_pcie_1_cfg_ahb_clk", 1731 .ops = &clk_branch2_ops, 1732 }, 1733 }, 1734}; 1735 1736static struct clk_branch gcc_pcie_1_mstr_axi_clk = { 1737 .halt_reg = 0x8d01c, 1738 .halt_check = BRANCH_HALT_VOTED, 1739 .clkr = { 1740 .enable_reg = 0x52000, 1741 .enable_mask = BIT(27), 1742 .hw.init = &(struct clk_init_data){ 1743 .name = "gcc_pcie_1_mstr_axi_clk", 1744 .ops = &clk_branch2_ops, 1745 }, 1746 }, 1747}; 1748 1749static struct clk_branch gcc_pcie_1_pipe_clk = { 1750 .halt_reg = 0x8d02c, 1751 .halt_check = BRANCH_HALT_SKIP, 1752 .clkr = { 1753 .enable_reg = 0x52000, 1754 .enable_mask = BIT(30), 1755 .hw.init = &(struct clk_init_data){ 1756 .name = "gcc_pcie_1_pipe_clk", 1757 .ops = &clk_branch2_ops, 1758 }, 1759 }, 1760}; 1761 1762static struct clk_branch gcc_pcie_1_slv_axi_clk = { 1763 .halt_reg = 0x8d014, 1764 .halt_check = BRANCH_HALT_VOTED, 1765 .hwcg_reg = 0x8d014, 1766 .hwcg_bit = 1, 1767 .clkr = { 1768 .enable_reg = 0x52000, 1769 .enable_mask = BIT(26), 1770 .hw.init = &(struct clk_init_data){ 1771 .name = "gcc_pcie_1_slv_axi_clk", 1772 .ops = &clk_branch2_ops, 1773 }, 1774 }, 1775}; 1776 1777static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = { 1778 .halt_reg = 0x8d010, 1779 .halt_check = BRANCH_HALT_VOTED, 1780 .clkr = { 1781 .enable_reg = 0x52000, 1782 .enable_mask = BIT(25), 1783 .hw.init = &(struct clk_init_data){ 1784 .name = "gcc_pcie_1_slv_q2a_axi_clk", 1785 .ops = &clk_branch2_ops, 1786 }, 1787 }, 1788}; 1789 1790static struct clk_branch gcc_pcie_2_aux_clk = { 1791 .halt_reg = 0x6028, 1792 .halt_check = BRANCH_HALT_VOTED, 1793 .clkr = { 1794 .enable_reg = 0x52010, 1795 .enable_mask = BIT(14), 1796 .hw.init = &(struct clk_init_data){ 1797 .name = "gcc_pcie_2_aux_clk", 1798 .parent_data = &(const struct clk_parent_data){ 1799 .hw = &gcc_pcie_2_aux_clk_src.clkr.hw, 1800 }, 1801 .num_parents = 1, 1802 .flags = CLK_SET_RATE_PARENT, 1803 .ops = &clk_branch2_ops, 1804 }, 1805 }, 1806}; 1807 1808static struct clk_branch gcc_pcie_2_cfg_ahb_clk = { 1809 .halt_reg = 0x6024, 1810 .halt_check = BRANCH_HALT_VOTED, 1811 .hwcg_reg = 0x6024, 1812 .hwcg_bit = 1, 1813 .clkr = { 1814 .enable_reg = 0x52010, 1815 .enable_mask = BIT(13), 1816 .hw.init = &(struct clk_init_data){ 1817 .name = "gcc_pcie_2_cfg_ahb_clk", 1818 .ops = &clk_branch2_ops, 1819 }, 1820 }, 1821}; 1822 1823static struct clk_branch gcc_pcie_2_mstr_axi_clk = { 1824 .halt_reg = 0x601c, 1825 .halt_check = BRANCH_HALT_VOTED, 1826 .clkr = { 1827 .enable_reg = 0x52010, 1828 .enable_mask = BIT(12), 1829 .hw.init = &(struct clk_init_data){ 1830 .name = "gcc_pcie_2_mstr_axi_clk", 1831 .ops = &clk_branch2_ops, 1832 }, 1833 }, 1834}; 1835 1836static struct clk_branch gcc_pcie_2_pipe_clk = { 1837 .halt_reg = 0x602c, 1838 .halt_check = BRANCH_HALT_SKIP, 1839 .clkr = { 1840 .enable_reg = 0x52010, 1841 .enable_mask = BIT(15), 1842 .hw.init = &(struct clk_init_data){ 1843 .name = "gcc_pcie_2_pipe_clk", 1844 .ops = &clk_branch2_ops, 1845 }, 1846 }, 1847}; 1848 1849static struct clk_branch gcc_pcie_2_slv_axi_clk = { 1850 .halt_reg = 0x6014, 1851 .halt_check = BRANCH_HALT_VOTED, 1852 .hwcg_reg = 0x6014, 1853 .hwcg_bit = 1, 1854 .clkr = { 1855 .enable_reg = 0x52010, 1856 .enable_mask = BIT(11), 1857 .hw.init = &(struct clk_init_data){ 1858 .name = "gcc_pcie_2_slv_axi_clk", 1859 .ops = &clk_branch2_ops, 1860 }, 1861 }, 1862}; 1863 1864static struct clk_branch gcc_pcie_2_slv_q2a_axi_clk = { 1865 .halt_reg = 0x6010, 1866 .halt_check = BRANCH_HALT_VOTED, 1867 .clkr = { 1868 .enable_reg = 0x52010, 1869 .enable_mask = BIT(10), 1870 .hw.init = &(struct clk_init_data){ 1871 .name = "gcc_pcie_2_slv_q2a_axi_clk", 1872 .ops = &clk_branch2_ops, 1873 }, 1874 }, 1875}; 1876 1877static struct clk_branch gcc_pcie_mdm_clkref_en = { 1878 .halt_reg = 0x8c00c, 1879 .halt_check = BRANCH_HALT, 1880 .clkr = { 1881 .enable_reg = 0x8c00c, 1882 .enable_mask = BIT(0), 1883 .hw.init = &(struct clk_init_data){ 1884 .name = "gcc_pcie_mdm_clkref_en", 1885 .ops = &clk_branch2_ops, 1886 }, 1887 }, 1888}; 1889 1890static struct clk_branch gcc_pcie_phy_aux_clk = { 1891 .halt_reg = 0x6f004, 1892 .halt_check = BRANCH_HALT, 1893 .clkr = { 1894 .enable_reg = 0x6f004, 1895 .enable_mask = BIT(0), 1896 .hw.init = &(struct clk_init_data){ 1897 .name = "gcc_pcie_phy_aux_clk", 1898 .parent_data = &(const struct clk_parent_data){ 1899 .hw = &gcc_pcie_0_aux_clk_src.clkr.hw, 1900 }, 1901 .num_parents = 1, 1902 .flags = CLK_SET_RATE_PARENT, 1903 .ops = &clk_branch2_ops, 1904 }, 1905 }, 1906}; 1907 1908static struct clk_branch gcc_pcie_wifi_clkref_en = { 1909 .halt_reg = 0x8c004, 1910 .halt_check = BRANCH_HALT, 1911 .clkr = { 1912 .enable_reg = 0x8c004, 1913 .enable_mask = BIT(0), 1914 .hw.init = &(struct clk_init_data){ 1915 .name = "gcc_pcie_wifi_clkref_en", 1916 .ops = &clk_branch2_ops, 1917 }, 1918 }, 1919}; 1920 1921static struct clk_branch gcc_pcie_wigig_clkref_en = { 1922 .halt_reg = 0x8c008, 1923 .halt_check = BRANCH_HALT, 1924 .clkr = { 1925 .enable_reg = 0x8c008, 1926 .enable_mask = BIT(0), 1927 .hw.init = &(struct clk_init_data){ 1928 .name = "gcc_pcie_wigig_clkref_en", 1929 .ops = &clk_branch2_ops, 1930 }, 1931 }, 1932}; 1933 1934static struct clk_branch gcc_pdm2_clk = { 1935 .halt_reg = 0x3300c, 1936 .halt_check = BRANCH_HALT, 1937 .clkr = { 1938 .enable_reg = 0x3300c, 1939 .enable_mask = BIT(0), 1940 .hw.init = &(struct clk_init_data){ 1941 .name = "gcc_pdm2_clk", 1942 .parent_data = &(const struct clk_parent_data){ 1943 .hw = &gcc_pdm2_clk_src.clkr.hw, 1944 }, 1945 .num_parents = 1, 1946 .flags = CLK_SET_RATE_PARENT, 1947 .ops = &clk_branch2_ops, 1948 }, 1949 }, 1950}; 1951 1952static struct clk_branch gcc_pdm_ahb_clk = { 1953 .halt_reg = 0x33004, 1954 .halt_check = BRANCH_HALT, 1955 .hwcg_reg = 0x33004, 1956 .hwcg_bit = 1, 1957 .clkr = { 1958 .enable_reg = 0x33004, 1959 .enable_mask = BIT(0), 1960 .hw.init = &(struct clk_init_data){ 1961 .name = "gcc_pdm_ahb_clk", 1962 .ops = &clk_branch2_ops, 1963 }, 1964 }, 1965}; 1966 1967static struct clk_branch gcc_pdm_xo4_clk = { 1968 .halt_reg = 0x33008, 1969 .halt_check = BRANCH_HALT, 1970 .clkr = { 1971 .enable_reg = 0x33008, 1972 .enable_mask = BIT(0), 1973 .hw.init = &(struct clk_init_data){ 1974 .name = "gcc_pdm_xo4_clk", 1975 .ops = &clk_branch2_ops, 1976 }, 1977 }, 1978}; 1979 1980static struct clk_branch gcc_prng_ahb_clk = { 1981 .halt_reg = 0x34004, 1982 .halt_check = BRANCH_HALT_VOTED, 1983 .clkr = { 1984 .enable_reg = 0x52000, 1985 .enable_mask = BIT(13), 1986 .hw.init = &(struct clk_init_data){ 1987 .name = "gcc_prng_ahb_clk", 1988 .ops = &clk_branch2_ops, 1989 }, 1990 }, 1991}; 1992 1993static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = { 1994 .halt_reg = 0xb018, 1995 .halt_check = BRANCH_HALT_VOTED, 1996 .hwcg_reg = 0xb018, 1997 .hwcg_bit = 1, 1998 .clkr = { 1999 .enable_reg = 0xb018, 2000 .enable_mask = BIT(0), 2001 .hw.init = &(struct clk_init_data){ 2002 .name = "gcc_qmip_camera_nrt_ahb_clk", 2003 .ops = &clk_branch2_ops, 2004 }, 2005 }, 2006}; 2007 2008static struct clk_branch gcc_qmip_camera_rt_ahb_clk = { 2009 .halt_reg = 0xb01c, 2010 .halt_check = BRANCH_HALT_VOTED, 2011 .hwcg_reg = 0xb01c, 2012 .hwcg_bit = 1, 2013 .clkr = { 2014 .enable_reg = 0xb01c, 2015 .enable_mask = BIT(0), 2016 .hw.init = &(struct clk_init_data){ 2017 .name = "gcc_qmip_camera_rt_ahb_clk", 2018 .ops = &clk_branch2_ops, 2019 }, 2020 }, 2021}; 2022 2023static struct clk_branch gcc_qmip_disp_ahb_clk = { 2024 .halt_reg = 0xb020, 2025 .halt_check = BRANCH_HALT_VOTED, 2026 .hwcg_reg = 0xb020, 2027 .hwcg_bit = 1, 2028 .clkr = { 2029 .enable_reg = 0xb020, 2030 .enable_mask = BIT(0), 2031 .hw.init = &(struct clk_init_data){ 2032 .name = "gcc_qmip_disp_ahb_clk", 2033 .ops = &clk_branch2_ops, 2034 }, 2035 }, 2036}; 2037 2038static struct clk_branch gcc_qmip_video_cvp_ahb_clk = { 2039 .halt_reg = 0xb010, 2040 .halt_check = BRANCH_HALT_VOTED, 2041 .hwcg_reg = 0xb010, 2042 .hwcg_bit = 1, 2043 .clkr = { 2044 .enable_reg = 0xb010, 2045 .enable_mask = BIT(0), 2046 .hw.init = &(struct clk_init_data){ 2047 .name = "gcc_qmip_video_cvp_ahb_clk", 2048 .ops = &clk_branch2_ops, 2049 }, 2050 }, 2051}; 2052 2053static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = { 2054 .halt_reg = 0xb014, 2055 .halt_check = BRANCH_HALT_VOTED, 2056 .hwcg_reg = 0xb014, 2057 .hwcg_bit = 1, 2058 .clkr = { 2059 .enable_reg = 0xb014, 2060 .enable_mask = BIT(0), 2061 .hw.init = &(struct clk_init_data){ 2062 .name = "gcc_qmip_video_vcodec_ahb_clk", 2063 .ops = &clk_branch2_ops, 2064 }, 2065 }, 2066}; 2067 2068static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = { 2069 .halt_reg = 0x23008, 2070 .halt_check = BRANCH_HALT_VOTED, 2071 .clkr = { 2072 .enable_reg = 0x52008, 2073 .enable_mask = BIT(9), 2074 .hw.init = &(struct clk_init_data){ 2075 .name = "gcc_qupv3_wrap0_core_2x_clk", 2076 .ops = &clk_branch2_ops, 2077 }, 2078 }, 2079}; 2080 2081static struct clk_branch gcc_qupv3_wrap0_core_clk = { 2082 .halt_reg = 0x23000, 2083 .halt_check = BRANCH_HALT_VOTED, 2084 .clkr = { 2085 .enable_reg = 0x52008, 2086 .enable_mask = BIT(8), 2087 .hw.init = &(struct clk_init_data){ 2088 .name = "gcc_qupv3_wrap0_core_clk", 2089 .ops = &clk_branch2_ops, 2090 }, 2091 }, 2092}; 2093 2094static struct clk_branch gcc_qupv3_wrap0_s0_clk = { 2095 .halt_reg = 0x1700c, 2096 .halt_check = BRANCH_HALT_VOTED, 2097 .clkr = { 2098 .enable_reg = 0x52008, 2099 .enable_mask = BIT(10), 2100 .hw.init = &(struct clk_init_data){ 2101 .name = "gcc_qupv3_wrap0_s0_clk", 2102 .parent_data = &(const struct clk_parent_data){ 2103 .hw = &gcc_qupv3_wrap0_s0_clk_src.clkr.hw, 2104 }, 2105 .num_parents = 1, 2106 .flags = CLK_SET_RATE_PARENT, 2107 .ops = &clk_branch2_ops, 2108 }, 2109 }, 2110}; 2111 2112static struct clk_branch gcc_qupv3_wrap0_s1_clk = { 2113 .halt_reg = 0x1713c, 2114 .halt_check = BRANCH_HALT_VOTED, 2115 .clkr = { 2116 .enable_reg = 0x52008, 2117 .enable_mask = BIT(11), 2118 .hw.init = &(struct clk_init_data){ 2119 .name = "gcc_qupv3_wrap0_s1_clk", 2120 .parent_data = &(const struct clk_parent_data){ 2121 .hw = &gcc_qupv3_wrap0_s1_clk_src.clkr.hw, 2122 }, 2123 .num_parents = 1, 2124 .flags = CLK_SET_RATE_PARENT, 2125 .ops = &clk_branch2_ops, 2126 }, 2127 }, 2128}; 2129 2130static struct clk_branch gcc_qupv3_wrap0_s2_clk = { 2131 .halt_reg = 0x1726c, 2132 .halt_check = BRANCH_HALT_VOTED, 2133 .clkr = { 2134 .enable_reg = 0x52008, 2135 .enable_mask = BIT(12), 2136 .hw.init = &(struct clk_init_data){ 2137 .name = "gcc_qupv3_wrap0_s2_clk", 2138 .parent_data = &(const struct clk_parent_data){ 2139 .hw = &gcc_qupv3_wrap0_s2_clk_src.clkr.hw, 2140 }, 2141 .num_parents = 1, 2142 .flags = CLK_SET_RATE_PARENT, 2143 .ops = &clk_branch2_ops, 2144 }, 2145 }, 2146}; 2147 2148static struct clk_branch gcc_qupv3_wrap0_s3_clk = { 2149 .halt_reg = 0x1739c, 2150 .halt_check = BRANCH_HALT_VOTED, 2151 .clkr = { 2152 .enable_reg = 0x52008, 2153 .enable_mask = BIT(13), 2154 .hw.init = &(struct clk_init_data){ 2155 .name = "gcc_qupv3_wrap0_s3_clk", 2156 .parent_data = &(const struct clk_parent_data){ 2157 .hw = &gcc_qupv3_wrap0_s3_clk_src.clkr.hw, 2158 }, 2159 .num_parents = 1, 2160 .flags = CLK_SET_RATE_PARENT, 2161 .ops = &clk_branch2_ops, 2162 }, 2163 }, 2164}; 2165 2166static struct clk_branch gcc_qupv3_wrap0_s4_clk = { 2167 .halt_reg = 0x174cc, 2168 .halt_check = BRANCH_HALT_VOTED, 2169 .clkr = { 2170 .enable_reg = 0x52008, 2171 .enable_mask = BIT(14), 2172 .hw.init = &(struct clk_init_data){ 2173 .name = "gcc_qupv3_wrap0_s4_clk", 2174 .parent_data = &(const struct clk_parent_data){ 2175 .hw = &gcc_qupv3_wrap0_s4_clk_src.clkr.hw, 2176 }, 2177 .num_parents = 1, 2178 .flags = CLK_SET_RATE_PARENT, 2179 .ops = &clk_branch2_ops, 2180 }, 2181 }, 2182}; 2183 2184static struct clk_branch gcc_qupv3_wrap0_s5_clk = { 2185 .halt_reg = 0x175fc, 2186 .halt_check = BRANCH_HALT_VOTED, 2187 .clkr = { 2188 .enable_reg = 0x52008, 2189 .enable_mask = BIT(15), 2190 .hw.init = &(struct clk_init_data){ 2191 .name = "gcc_qupv3_wrap0_s5_clk", 2192 .parent_data = &(const struct clk_parent_data){ 2193 .hw = &gcc_qupv3_wrap0_s5_clk_src.clkr.hw, 2194 }, 2195 .num_parents = 1, 2196 .flags = CLK_SET_RATE_PARENT, 2197 .ops = &clk_branch2_ops, 2198 }, 2199 }, 2200}; 2201 2202static struct clk_branch gcc_qupv3_wrap0_s6_clk = { 2203 .halt_reg = 0x1772c, 2204 .halt_check = BRANCH_HALT_VOTED, 2205 .clkr = { 2206 .enable_reg = 0x52008, 2207 .enable_mask = BIT(16), 2208 .hw.init = &(struct clk_init_data){ 2209 .name = "gcc_qupv3_wrap0_s6_clk", 2210 .parent_data = &(const struct clk_parent_data){ 2211 .hw = &gcc_qupv3_wrap0_s6_clk_src.clkr.hw, 2212 }, 2213 .num_parents = 1, 2214 .flags = CLK_SET_RATE_PARENT, 2215 .ops = &clk_branch2_ops, 2216 }, 2217 }, 2218}; 2219 2220static struct clk_branch gcc_qupv3_wrap0_s7_clk = { 2221 .halt_reg = 0x1785c, 2222 .halt_check = BRANCH_HALT_VOTED, 2223 .clkr = { 2224 .enable_reg = 0x52008, 2225 .enable_mask = BIT(17), 2226 .hw.init = &(struct clk_init_data){ 2227 .name = "gcc_qupv3_wrap0_s7_clk", 2228 .parent_data = &(const struct clk_parent_data){ 2229 .hw = &gcc_qupv3_wrap0_s7_clk_src.clkr.hw, 2230 }, 2231 .num_parents = 1, 2232 .flags = CLK_SET_RATE_PARENT, 2233 .ops = &clk_branch2_ops, 2234 }, 2235 }, 2236}; 2237 2238static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = { 2239 .halt_reg = 0x23140, 2240 .halt_check = BRANCH_HALT_VOTED, 2241 .clkr = { 2242 .enable_reg = 0x52008, 2243 .enable_mask = BIT(18), 2244 .hw.init = &(struct clk_init_data){ 2245 .name = "gcc_qupv3_wrap1_core_2x_clk", 2246 .ops = &clk_branch2_ops, 2247 }, 2248 }, 2249}; 2250 2251static struct clk_branch gcc_qupv3_wrap1_core_clk = { 2252 .halt_reg = 0x23138, 2253 .halt_check = BRANCH_HALT_VOTED, 2254 .clkr = { 2255 .enable_reg = 0x52008, 2256 .enable_mask = BIT(19), 2257 .hw.init = &(struct clk_init_data){ 2258 .name = "gcc_qupv3_wrap1_core_clk", 2259 .ops = &clk_branch2_ops, 2260 }, 2261 }, 2262}; 2263 2264static struct clk_branch gcc_qupv3_wrap1_s0_clk = { 2265 .halt_reg = 0x1800c, 2266 .halt_check = BRANCH_HALT_VOTED, 2267 .clkr = { 2268 .enable_reg = 0x52008, 2269 .enable_mask = BIT(22), 2270 .hw.init = &(struct clk_init_data){ 2271 .name = "gcc_qupv3_wrap1_s0_clk", 2272 .parent_data = &(const struct clk_parent_data){ 2273 .hw = &gcc_qupv3_wrap1_s0_clk_src.clkr.hw, 2274 }, 2275 .num_parents = 1, 2276 .flags = CLK_SET_RATE_PARENT, 2277 .ops = &clk_branch2_ops, 2278 }, 2279 }, 2280}; 2281 2282static struct clk_branch gcc_qupv3_wrap1_s1_clk = { 2283 .halt_reg = 0x1813c, 2284 .halt_check = BRANCH_HALT_VOTED, 2285 .clkr = { 2286 .enable_reg = 0x52008, 2287 .enable_mask = BIT(23), 2288 .hw.init = &(struct clk_init_data){ 2289 .name = "gcc_qupv3_wrap1_s1_clk", 2290 .parent_data = &(const struct clk_parent_data){ 2291 .hw = &gcc_qupv3_wrap1_s1_clk_src.clkr.hw, 2292 }, 2293 .num_parents = 1, 2294 .flags = CLK_SET_RATE_PARENT, 2295 .ops = &clk_branch2_ops, 2296 }, 2297 }, 2298}; 2299 2300static struct clk_branch gcc_qupv3_wrap1_s2_clk = { 2301 .halt_reg = 0x1826c, 2302 .halt_check = BRANCH_HALT_VOTED, 2303 .clkr = { 2304 .enable_reg = 0x52008, 2305 .enable_mask = BIT(24), 2306 .hw.init = &(struct clk_init_data){ 2307 .name = "gcc_qupv3_wrap1_s2_clk", 2308 .parent_data = &(const struct clk_parent_data){ 2309 .hw = &gcc_qupv3_wrap1_s2_clk_src.clkr.hw, 2310 }, 2311 .num_parents = 1, 2312 .flags = CLK_SET_RATE_PARENT, 2313 .ops = &clk_branch2_ops, 2314 }, 2315 }, 2316}; 2317 2318static struct clk_branch gcc_qupv3_wrap1_s3_clk = { 2319 .halt_reg = 0x1839c, 2320 .halt_check = BRANCH_HALT_VOTED, 2321 .clkr = { 2322 .enable_reg = 0x52008, 2323 .enable_mask = BIT(25), 2324 .hw.init = &(struct clk_init_data){ 2325 .name = "gcc_qupv3_wrap1_s3_clk", 2326 .parent_data = &(const struct clk_parent_data){ 2327 .hw = &gcc_qupv3_wrap1_s3_clk_src.clkr.hw, 2328 }, 2329 .num_parents = 1, 2330 .flags = CLK_SET_RATE_PARENT, 2331 .ops = &clk_branch2_ops, 2332 }, 2333 }, 2334}; 2335 2336static struct clk_branch gcc_qupv3_wrap1_s4_clk = { 2337 .halt_reg = 0x184cc, 2338 .halt_check = BRANCH_HALT_VOTED, 2339 .clkr = { 2340 .enable_reg = 0x52008, 2341 .enable_mask = BIT(26), 2342 .hw.init = &(struct clk_init_data){ 2343 .name = "gcc_qupv3_wrap1_s4_clk", 2344 .parent_data = &(const struct clk_parent_data){ 2345 .hw = &gcc_qupv3_wrap1_s4_clk_src.clkr.hw, 2346 }, 2347 .num_parents = 1, 2348 .flags = CLK_SET_RATE_PARENT, 2349 .ops = &clk_branch2_ops, 2350 }, 2351 }, 2352}; 2353 2354static struct clk_branch gcc_qupv3_wrap1_s5_clk = { 2355 .halt_reg = 0x185fc, 2356 .halt_check = BRANCH_HALT_VOTED, 2357 .clkr = { 2358 .enable_reg = 0x52008, 2359 .enable_mask = BIT(27), 2360 .hw.init = &(struct clk_init_data){ 2361 .name = "gcc_qupv3_wrap1_s5_clk", 2362 .parent_data = &(const struct clk_parent_data){ 2363 .hw = &gcc_qupv3_wrap1_s5_clk_src.clkr.hw, 2364 }, 2365 .num_parents = 1, 2366 .flags = CLK_SET_RATE_PARENT, 2367 .ops = &clk_branch2_ops, 2368 }, 2369 }, 2370}; 2371 2372static struct clk_branch gcc_qupv3_wrap2_core_2x_clk = { 2373 .halt_reg = 0x23278, 2374 .halt_check = BRANCH_HALT_VOTED, 2375 .clkr = { 2376 .enable_reg = 0x52010, 2377 .enable_mask = BIT(3), 2378 .hw.init = &(struct clk_init_data){ 2379 .name = "gcc_qupv3_wrap2_core_2x_clk", 2380 .ops = &clk_branch2_ops, 2381 }, 2382 }, 2383}; 2384 2385static struct clk_branch gcc_qupv3_wrap2_core_clk = { 2386 .halt_reg = 0x23270, 2387 .halt_check = BRANCH_HALT_VOTED, 2388 .clkr = { 2389 .enable_reg = 0x52010, 2390 .enable_mask = BIT(0), 2391 .hw.init = &(struct clk_init_data){ 2392 .name = "gcc_qupv3_wrap2_core_clk", 2393 .ops = &clk_branch2_ops, 2394 }, 2395 }, 2396}; 2397 2398static struct clk_branch gcc_qupv3_wrap2_s0_clk = { 2399 .halt_reg = 0x1e00c, 2400 .halt_check = BRANCH_HALT_VOTED, 2401 .clkr = { 2402 .enable_reg = 0x52010, 2403 .enable_mask = BIT(4), 2404 .hw.init = &(struct clk_init_data){ 2405 .name = "gcc_qupv3_wrap2_s0_clk", 2406 .parent_data = &(const struct clk_parent_data){ 2407 .hw = &gcc_qupv3_wrap2_s0_clk_src.clkr.hw, 2408 }, 2409 .num_parents = 1, 2410 .flags = CLK_SET_RATE_PARENT, 2411 .ops = &clk_branch2_ops, 2412 }, 2413 }, 2414}; 2415 2416static struct clk_branch gcc_qupv3_wrap2_s1_clk = { 2417 .halt_reg = 0x1e13c, 2418 .halt_check = BRANCH_HALT_VOTED, 2419 .clkr = { 2420 .enable_reg = 0x52010, 2421 .enable_mask = BIT(5), 2422 .hw.init = &(struct clk_init_data){ 2423 .name = "gcc_qupv3_wrap2_s1_clk", 2424 .parent_data = &(const struct clk_parent_data){ 2425 .hw = &gcc_qupv3_wrap2_s1_clk_src.clkr.hw, 2426 }, 2427 .num_parents = 1, 2428 .flags = CLK_SET_RATE_PARENT, 2429 .ops = &clk_branch2_ops, 2430 }, 2431 }, 2432}; 2433 2434static struct clk_branch gcc_qupv3_wrap2_s2_clk = { 2435 .halt_reg = 0x1e26c, 2436 .halt_check = BRANCH_HALT_VOTED, 2437 .clkr = { 2438 .enable_reg = 0x52010, 2439 .enable_mask = BIT(6), 2440 .hw.init = &(struct clk_init_data){ 2441 .name = "gcc_qupv3_wrap2_s2_clk", 2442 .parent_data = &(const struct clk_parent_data){ 2443 .hw = &gcc_qupv3_wrap2_s2_clk_src.clkr.hw, 2444 }, 2445 .num_parents = 1, 2446 .flags = CLK_SET_RATE_PARENT, 2447 .ops = &clk_branch2_ops, 2448 }, 2449 }, 2450}; 2451 2452static struct clk_branch gcc_qupv3_wrap2_s3_clk = { 2453 .halt_reg = 0x1e39c, 2454 .halt_check = BRANCH_HALT_VOTED, 2455 .clkr = { 2456 .enable_reg = 0x52010, 2457 .enable_mask = BIT(7), 2458 .hw.init = &(struct clk_init_data){ 2459 .name = "gcc_qupv3_wrap2_s3_clk", 2460 .parent_data = &(const struct clk_parent_data){ 2461 .hw = &gcc_qupv3_wrap2_s3_clk_src.clkr.hw, 2462 }, 2463 .num_parents = 1, 2464 .flags = CLK_SET_RATE_PARENT, 2465 .ops = &clk_branch2_ops, 2466 }, 2467 }, 2468}; 2469 2470static struct clk_branch gcc_qupv3_wrap2_s4_clk = { 2471 .halt_reg = 0x1e4cc, 2472 .halt_check = BRANCH_HALT_VOTED, 2473 .clkr = { 2474 .enable_reg = 0x52010, 2475 .enable_mask = BIT(8), 2476 .hw.init = &(struct clk_init_data){ 2477 .name = "gcc_qupv3_wrap2_s4_clk", 2478 .parent_data = &(const struct clk_parent_data){ 2479 .hw = &gcc_qupv3_wrap2_s4_clk_src.clkr.hw, 2480 }, 2481 .num_parents = 1, 2482 .flags = CLK_SET_RATE_PARENT, 2483 .ops = &clk_branch2_ops, 2484 }, 2485 }, 2486}; 2487 2488static struct clk_branch gcc_qupv3_wrap2_s5_clk = { 2489 .halt_reg = 0x1e5fc, 2490 .halt_check = BRANCH_HALT_VOTED, 2491 .clkr = { 2492 .enable_reg = 0x52010, 2493 .enable_mask = BIT(9), 2494 .hw.init = &(struct clk_init_data){ 2495 .name = "gcc_qupv3_wrap2_s5_clk", 2496 .parent_data = &(const struct clk_parent_data){ 2497 .hw = &gcc_qupv3_wrap2_s5_clk_src.clkr.hw, 2498 }, 2499 .num_parents = 1, 2500 .flags = CLK_SET_RATE_PARENT, 2501 .ops = &clk_branch2_ops, 2502 }, 2503 }, 2504}; 2505 2506static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = { 2507 .halt_reg = 0x17004, 2508 .halt_check = BRANCH_HALT_VOTED, 2509 .clkr = { 2510 .enable_reg = 0x52008, 2511 .enable_mask = BIT(6), 2512 .hw.init = &(struct clk_init_data){ 2513 .name = "gcc_qupv3_wrap_0_m_ahb_clk", 2514 .ops = &clk_branch2_ops, 2515 }, 2516 }, 2517}; 2518 2519static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = { 2520 .halt_reg = 0x17008, 2521 .halt_check = BRANCH_HALT_VOTED, 2522 .hwcg_reg = 0x17008, 2523 .hwcg_bit = 1, 2524 .clkr = { 2525 .enable_reg = 0x52008, 2526 .enable_mask = BIT(7), 2527 .hw.init = &(struct clk_init_data){ 2528 .name = "gcc_qupv3_wrap_0_s_ahb_clk", 2529 .ops = &clk_branch2_ops, 2530 }, 2531 }, 2532}; 2533 2534static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = { 2535 .halt_reg = 0x18004, 2536 .halt_check = BRANCH_HALT_VOTED, 2537 .clkr = { 2538 .enable_reg = 0x52008, 2539 .enable_mask = BIT(20), 2540 .hw.init = &(struct clk_init_data){ 2541 .name = "gcc_qupv3_wrap_1_m_ahb_clk", 2542 .ops = &clk_branch2_ops, 2543 }, 2544 }, 2545}; 2546 2547static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = { 2548 .halt_reg = 0x18008, 2549 .halt_check = BRANCH_HALT_VOTED, 2550 .hwcg_reg = 0x18008, 2551 .hwcg_bit = 1, 2552 .clkr = { 2553 .enable_reg = 0x52008, 2554 .enable_mask = BIT(21), 2555 .hw.init = &(struct clk_init_data){ 2556 .name = "gcc_qupv3_wrap_1_s_ahb_clk", 2557 .ops = &clk_branch2_ops, 2558 }, 2559 }, 2560}; 2561 2562static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = { 2563 .halt_reg = 0x1e004, 2564 .halt_check = BRANCH_HALT_VOTED, 2565 .clkr = { 2566 .enable_reg = 0x52010, 2567 .enable_mask = BIT(2), 2568 .hw.init = &(struct clk_init_data){ 2569 .name = "gcc_qupv3_wrap_2_m_ahb_clk", 2570 .ops = &clk_branch2_ops, 2571 }, 2572 }, 2573}; 2574 2575static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = { 2576 .halt_reg = 0x1e008, 2577 .halt_check = BRANCH_HALT_VOTED, 2578 .hwcg_reg = 0x1e008, 2579 .hwcg_bit = 1, 2580 .clkr = { 2581 .enable_reg = 0x52010, 2582 .enable_mask = BIT(1), 2583 .hw.init = &(struct clk_init_data){ 2584 .name = "gcc_qupv3_wrap_2_s_ahb_clk", 2585 .ops = &clk_branch2_ops, 2586 }, 2587 }, 2588}; 2589 2590static struct clk_branch gcc_sdcc2_ahb_clk = { 2591 .halt_reg = 0x14008, 2592 .halt_check = BRANCH_HALT, 2593 .clkr = { 2594 .enable_reg = 0x14008, 2595 .enable_mask = BIT(0), 2596 .hw.init = &(struct clk_init_data){ 2597 .name = "gcc_sdcc2_ahb_clk", 2598 .ops = &clk_branch2_ops, 2599 }, 2600 }, 2601}; 2602 2603static struct clk_branch gcc_sdcc2_apps_clk = { 2604 .halt_reg = 0x14004, 2605 .halt_check = BRANCH_HALT, 2606 .clkr = { 2607 .enable_reg = 0x14004, 2608 .enable_mask = BIT(0), 2609 .hw.init = &(struct clk_init_data){ 2610 .name = "gcc_sdcc2_apps_clk", 2611 .parent_data = &(const struct clk_parent_data){ 2612 .hw = &gcc_sdcc2_apps_clk_src.clkr.hw, 2613 }, 2614 .num_parents = 1, 2615 .flags = CLK_SET_RATE_PARENT, 2616 .ops = &clk_branch2_ops, 2617 }, 2618 }, 2619}; 2620 2621static struct clk_branch gcc_sdcc4_ahb_clk = { 2622 .halt_reg = 0x16008, 2623 .halt_check = BRANCH_HALT, 2624 .clkr = { 2625 .enable_reg = 0x16008, 2626 .enable_mask = BIT(0), 2627 .hw.init = &(struct clk_init_data){ 2628 .name = "gcc_sdcc4_ahb_clk", 2629 .ops = &clk_branch2_ops, 2630 }, 2631 }, 2632}; 2633 2634static struct clk_branch gcc_sdcc4_apps_clk = { 2635 .halt_reg = 0x16004, 2636 .halt_check = BRANCH_HALT, 2637 .clkr = { 2638 .enable_reg = 0x16004, 2639 .enable_mask = BIT(0), 2640 .hw.init = &(struct clk_init_data){ 2641 .name = "gcc_sdcc4_apps_clk", 2642 .parent_data = &(const struct clk_parent_data){ 2643 .hw = &gcc_sdcc4_apps_clk_src.clkr.hw, 2644 }, 2645 .num_parents = 1, 2646 .flags = CLK_SET_RATE_PARENT, 2647 .ops = &clk_branch2_ops, 2648 }, 2649 }, 2650}; 2651 2652static struct clk_branch gcc_tsif_ahb_clk = { 2653 .halt_reg = 0x36004, 2654 .halt_check = BRANCH_HALT_VOTED, 2655 .clkr = { 2656 .enable_reg = 0x36004, 2657 .enable_mask = BIT(0), 2658 .hw.init = &(struct clk_init_data){ 2659 .name = "gcc_tsif_ahb_clk", 2660 .ops = &clk_branch2_ops, 2661 }, 2662 }, 2663}; 2664 2665static struct clk_branch gcc_tsif_inactivity_timers_clk = { 2666 .halt_reg = 0x3600c, 2667 .halt_check = BRANCH_HALT, 2668 .clkr = { 2669 .enable_reg = 0x3600c, 2670 .enable_mask = BIT(0), 2671 .hw.init = &(struct clk_init_data){ 2672 .name = "gcc_tsif_inactivity_timers_clk", 2673 .ops = &clk_branch2_ops, 2674 }, 2675 }, 2676}; 2677 2678static struct clk_branch gcc_tsif_ref_clk = { 2679 .halt_reg = 0x36008, 2680 .halt_check = BRANCH_HALT, 2681 .clkr = { 2682 .enable_reg = 0x36008, 2683 .enable_mask = BIT(0), 2684 .hw.init = &(struct clk_init_data){ 2685 .name = "gcc_tsif_ref_clk", 2686 .parent_data = &(const struct clk_parent_data){ 2687 .hw = &gcc_tsif_ref_clk_src.clkr.hw, 2688 }, 2689 .num_parents = 1, 2690 .flags = CLK_SET_RATE_PARENT, 2691 .ops = &clk_branch2_ops, 2692 }, 2693 }, 2694}; 2695 2696static struct clk_branch gcc_ufs_1x_clkref_en = { 2697 .halt_reg = 0x8c000, 2698 .halt_check = BRANCH_HALT, 2699 .clkr = { 2700 .enable_reg = 0x8c000, 2701 .enable_mask = BIT(0), 2702 .hw.init = &(struct clk_init_data){ 2703 .name = "gcc_ufs_1x_clkref_en", 2704 .ops = &clk_branch2_ops, 2705 }, 2706 }, 2707}; 2708 2709static struct clk_branch gcc_ufs_card_ahb_clk = { 2710 .halt_reg = 0x75018, 2711 .halt_check = BRANCH_HALT_VOTED, 2712 .hwcg_reg = 0x75018, 2713 .hwcg_bit = 1, 2714 .clkr = { 2715 .enable_reg = 0x75018, 2716 .enable_mask = BIT(0), 2717 .hw.init = &(struct clk_init_data){ 2718 .name = "gcc_ufs_card_ahb_clk", 2719 .ops = &clk_branch2_ops, 2720 }, 2721 }, 2722}; 2723 2724static struct clk_branch gcc_ufs_card_axi_clk = { 2725 .halt_reg = 0x75010, 2726 .halt_check = BRANCH_HALT, 2727 .hwcg_reg = 0x75010, 2728 .hwcg_bit = 1, 2729 .clkr = { 2730 .enable_reg = 0x75010, 2731 .enable_mask = BIT(0), 2732 .hw.init = &(struct clk_init_data){ 2733 .name = "gcc_ufs_card_axi_clk", 2734 .parent_data = &(const struct clk_parent_data){ 2735 .hw = &gcc_ufs_card_axi_clk_src.clkr.hw, 2736 }, 2737 .num_parents = 1, 2738 .flags = CLK_SET_RATE_PARENT, 2739 .ops = &clk_branch2_ops, 2740 }, 2741 }, 2742}; 2743 2744static struct clk_branch gcc_ufs_card_ice_core_clk = { 2745 .halt_reg = 0x75064, 2746 .halt_check = BRANCH_HALT_VOTED, 2747 .hwcg_reg = 0x75064, 2748 .hwcg_bit = 1, 2749 .clkr = { 2750 .enable_reg = 0x75064, 2751 .enable_mask = BIT(0), 2752 .hw.init = &(struct clk_init_data){ 2753 .name = "gcc_ufs_card_ice_core_clk", 2754 .parent_data = &(const struct clk_parent_data){ 2755 .hw = &gcc_ufs_card_ice_core_clk_src.clkr.hw, 2756 }, 2757 .num_parents = 1, 2758 .flags = CLK_SET_RATE_PARENT, 2759 .ops = &clk_branch2_ops, 2760 }, 2761 }, 2762}; 2763 2764static struct clk_branch gcc_ufs_card_phy_aux_clk = { 2765 .halt_reg = 0x7509c, 2766 .halt_check = BRANCH_HALT, 2767 .hwcg_reg = 0x7509c, 2768 .hwcg_bit = 1, 2769 .clkr = { 2770 .enable_reg = 0x7509c, 2771 .enable_mask = BIT(0), 2772 .hw.init = &(struct clk_init_data){ 2773 .name = "gcc_ufs_card_phy_aux_clk", 2774 .parent_data = &(const struct clk_parent_data){ 2775 .hw = &gcc_ufs_card_phy_aux_clk_src.clkr.hw, 2776 }, 2777 .num_parents = 1, 2778 .flags = CLK_SET_RATE_PARENT, 2779 .ops = &clk_branch2_ops, 2780 }, 2781 }, 2782}; 2783 2784static struct clk_branch gcc_ufs_card_rx_symbol_0_clk = { 2785 .halt_reg = 0x75020, 2786 .halt_check = BRANCH_HALT_DELAY, 2787 .clkr = { 2788 .enable_reg = 0x75020, 2789 .enable_mask = BIT(0), 2790 .hw.init = &(struct clk_init_data){ 2791 .name = "gcc_ufs_card_rx_symbol_0_clk", 2792 .ops = &clk_branch2_ops, 2793 }, 2794 }, 2795}; 2796 2797static struct clk_branch gcc_ufs_card_rx_symbol_1_clk = { 2798 .halt_reg = 0x750b8, 2799 .halt_check = BRANCH_HALT_DELAY, 2800 .clkr = { 2801 .enable_reg = 0x750b8, 2802 .enable_mask = BIT(0), 2803 .hw.init = &(struct clk_init_data){ 2804 .name = "gcc_ufs_card_rx_symbol_1_clk", 2805 .ops = &clk_branch2_ops, 2806 }, 2807 }, 2808}; 2809 2810static struct clk_branch gcc_ufs_card_tx_symbol_0_clk = { 2811 .halt_reg = 0x7501c, 2812 .halt_check = BRANCH_HALT_DELAY, 2813 .clkr = { 2814 .enable_reg = 0x7501c, 2815 .enable_mask = BIT(0), 2816 .hw.init = &(struct clk_init_data){ 2817 .name = "gcc_ufs_card_tx_symbol_0_clk", 2818 .ops = &clk_branch2_ops, 2819 }, 2820 }, 2821}; 2822 2823static struct clk_branch gcc_ufs_card_unipro_core_clk = { 2824 .halt_reg = 0x7505c, 2825 .halt_check = BRANCH_HALT, 2826 .hwcg_reg = 0x7505c, 2827 .hwcg_bit = 1, 2828 .clkr = { 2829 .enable_reg = 0x7505c, 2830 .enable_mask = BIT(0), 2831 .hw.init = &(struct clk_init_data){ 2832 .name = "gcc_ufs_card_unipro_core_clk", 2833 .parent_data = &(const struct clk_parent_data){ 2834 .hw = &gcc_ufs_card_unipro_core_clk_src.clkr.hw, 2835 }, 2836 .num_parents = 1, 2837 .flags = CLK_SET_RATE_PARENT, 2838 .ops = &clk_branch2_ops, 2839 }, 2840 }, 2841}; 2842 2843static struct clk_branch gcc_ufs_phy_ahb_clk = { 2844 .halt_reg = 0x77018, 2845 .halt_check = BRANCH_HALT_VOTED, 2846 .hwcg_reg = 0x77018, 2847 .hwcg_bit = 1, 2848 .clkr = { 2849 .enable_reg = 0x77018, 2850 .enable_mask = BIT(0), 2851 .hw.init = &(struct clk_init_data){ 2852 .name = "gcc_ufs_phy_ahb_clk", 2853 .ops = &clk_branch2_ops, 2854 }, 2855 }, 2856}; 2857 2858static struct clk_branch gcc_ufs_phy_axi_clk = { 2859 .halt_reg = 0x77010, 2860 .halt_check = BRANCH_HALT, 2861 .hwcg_reg = 0x77010, 2862 .hwcg_bit = 1, 2863 .clkr = { 2864 .enable_reg = 0x77010, 2865 .enable_mask = BIT(0), 2866 .hw.init = &(struct clk_init_data){ 2867 .name = "gcc_ufs_phy_axi_clk", 2868 .parent_data = &(const struct clk_parent_data){ 2869 .hw = &gcc_ufs_phy_axi_clk_src.clkr.hw, 2870 }, 2871 .num_parents = 1, 2872 .flags = CLK_SET_RATE_PARENT, 2873 .ops = &clk_branch2_ops, 2874 }, 2875 }, 2876}; 2877 2878static struct clk_branch gcc_ufs_phy_ice_core_clk = { 2879 .halt_reg = 0x77064, 2880 .halt_check = BRANCH_HALT_VOTED, 2881 .hwcg_reg = 0x77064, 2882 .hwcg_bit = 1, 2883 .clkr = { 2884 .enable_reg = 0x77064, 2885 .enable_mask = BIT(0), 2886 .hw.init = &(struct clk_init_data){ 2887 .name = "gcc_ufs_phy_ice_core_clk", 2888 .parent_data = &(const struct clk_parent_data){ 2889 .hw = &gcc_ufs_phy_ice_core_clk_src.clkr.hw, 2890 }, 2891 .num_parents = 1, 2892 .flags = CLK_SET_RATE_PARENT, 2893 .ops = &clk_branch2_ops, 2894 }, 2895 }, 2896}; 2897 2898static struct clk_branch gcc_ufs_phy_phy_aux_clk = { 2899 .halt_reg = 0x7709c, 2900 .halt_check = BRANCH_HALT, 2901 .hwcg_reg = 0x7709c, 2902 .hwcg_bit = 1, 2903 .clkr = { 2904 .enable_reg = 0x7709c, 2905 .enable_mask = BIT(0), 2906 .hw.init = &(struct clk_init_data){ 2907 .name = "gcc_ufs_phy_phy_aux_clk", 2908 .parent_data = &(const struct clk_parent_data){ 2909 .hw = &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, 2910 }, 2911 .num_parents = 1, 2912 .flags = CLK_SET_RATE_PARENT, 2913 .ops = &clk_branch2_ops, 2914 }, 2915 }, 2916}; 2917 2918static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = { 2919 .halt_reg = 0x77020, 2920 .halt_check = BRANCH_HALT_DELAY, 2921 .clkr = { 2922 .enable_reg = 0x77020, 2923 .enable_mask = BIT(0), 2924 .hw.init = &(struct clk_init_data){ 2925 .name = "gcc_ufs_phy_rx_symbol_0_clk", 2926 .ops = &clk_branch2_ops, 2927 }, 2928 }, 2929}; 2930 2931static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = { 2932 .halt_reg = 0x770b8, 2933 .halt_check = BRANCH_HALT_DELAY, 2934 .clkr = { 2935 .enable_reg = 0x770b8, 2936 .enable_mask = BIT(0), 2937 .hw.init = &(struct clk_init_data){ 2938 .name = "gcc_ufs_phy_rx_symbol_1_clk", 2939 .ops = &clk_branch2_ops, 2940 }, 2941 }, 2942}; 2943 2944static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = { 2945 .halt_reg = 0x7701c, 2946 .halt_check = BRANCH_HALT_DELAY, 2947 .clkr = { 2948 .enable_reg = 0x7701c, 2949 .enable_mask = BIT(0), 2950 .hw.init = &(struct clk_init_data){ 2951 .name = "gcc_ufs_phy_tx_symbol_0_clk", 2952 .ops = &clk_branch2_ops, 2953 }, 2954 }, 2955}; 2956 2957static struct clk_branch gcc_ufs_phy_unipro_core_clk = { 2958 .halt_reg = 0x7705c, 2959 .halt_check = BRANCH_HALT, 2960 .hwcg_reg = 0x7705c, 2961 .hwcg_bit = 1, 2962 .clkr = { 2963 .enable_reg = 0x7705c, 2964 .enable_mask = BIT(0), 2965 .hw.init = &(struct clk_init_data){ 2966 .name = "gcc_ufs_phy_unipro_core_clk", 2967 .parent_data = &(const struct clk_parent_data){ 2968 .hw = &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, 2969 }, 2970 .num_parents = 1, 2971 .flags = CLK_SET_RATE_PARENT, 2972 .ops = &clk_branch2_ops, 2973 }, 2974 }, 2975}; 2976 2977static struct clk_branch gcc_usb30_prim_master_clk = { 2978 .halt_reg = 0xf010, 2979 .halt_check = BRANCH_HALT_VOTED, 2980 .clkr = { 2981 .enable_reg = 0xf010, 2982 .enable_mask = BIT(0), 2983 .hw.init = &(struct clk_init_data){ 2984 .name = "gcc_usb30_prim_master_clk", 2985 .parent_data = &(const struct clk_parent_data){ 2986 .hw = &gcc_usb30_prim_master_clk_src.clkr.hw, 2987 }, 2988 .num_parents = 1, 2989 .flags = CLK_SET_RATE_PARENT, 2990 .ops = &clk_branch2_ops, 2991 }, 2992 }, 2993}; 2994 2995static struct clk_branch gcc_usb30_prim_mock_utmi_clk = { 2996 .halt_reg = 0xf01c, 2997 .halt_check = BRANCH_HALT, 2998 .clkr = { 2999 .enable_reg = 0xf01c, 3000 .enable_mask = BIT(0), 3001 .hw.init = &(struct clk_init_data){ 3002 .name = "gcc_usb30_prim_mock_utmi_clk", 3003 .parent_data = &(const struct clk_parent_data){ 3004 .hw = 3005 &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw, 3006 }, 3007 .num_parents = 1, 3008 .flags = CLK_SET_RATE_PARENT, 3009 .ops = &clk_branch2_ops, 3010 }, 3011 }, 3012}; 3013 3014static struct clk_branch gcc_usb30_prim_sleep_clk = { 3015 .halt_reg = 0xf018, 3016 .halt_check = BRANCH_HALT, 3017 .clkr = { 3018 .enable_reg = 0xf018, 3019 .enable_mask = BIT(0), 3020 .hw.init = &(struct clk_init_data){ 3021 .name = "gcc_usb30_prim_sleep_clk", 3022 .ops = &clk_branch2_ops, 3023 }, 3024 }, 3025}; 3026 3027static struct clk_branch gcc_usb30_sec_master_clk = { 3028 .halt_reg = 0x10010, 3029 .halt_check = BRANCH_HALT_VOTED, 3030 .clkr = { 3031 .enable_reg = 0x10010, 3032 .enable_mask = BIT(0), 3033 .hw.init = &(struct clk_init_data){ 3034 .name = "gcc_usb30_sec_master_clk", 3035 .parent_data = &(const struct clk_parent_data){ 3036 .hw = &gcc_usb30_sec_master_clk_src.clkr.hw, 3037 }, 3038 .num_parents = 1, 3039 .flags = CLK_SET_RATE_PARENT, 3040 .ops = &clk_branch2_ops, 3041 }, 3042 }, 3043}; 3044 3045static struct clk_branch gcc_usb30_sec_mock_utmi_clk = { 3046 .halt_reg = 0x1001c, 3047 .halt_check = BRANCH_HALT, 3048 .clkr = { 3049 .enable_reg = 0x1001c, 3050 .enable_mask = BIT(0), 3051 .hw.init = &(struct clk_init_data){ 3052 .name = "gcc_usb30_sec_mock_utmi_clk", 3053 .parent_data = &(const struct clk_parent_data){ 3054 .hw = 3055 &gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr.hw, 3056 }, 3057 .num_parents = 1, 3058 .flags = CLK_SET_RATE_PARENT, 3059 .ops = &clk_branch2_ops, 3060 }, 3061 }, 3062}; 3063 3064static struct clk_branch gcc_usb30_sec_sleep_clk = { 3065 .halt_reg = 0x10018, 3066 .halt_check = BRANCH_HALT, 3067 .clkr = { 3068 .enable_reg = 0x10018, 3069 .enable_mask = BIT(0), 3070 .hw.init = &(struct clk_init_data){ 3071 .name = "gcc_usb30_sec_sleep_clk", 3072 .ops = &clk_branch2_ops, 3073 }, 3074 }, 3075}; 3076 3077static struct clk_branch gcc_usb3_prim_phy_aux_clk = { 3078 .halt_reg = 0xf054, 3079 .halt_check = BRANCH_HALT, 3080 .clkr = { 3081 .enable_reg = 0xf054, 3082 .enable_mask = BIT(0), 3083 .hw.init = &(struct clk_init_data){ 3084 .name = "gcc_usb3_prim_phy_aux_clk", 3085 .parent_data = &(const struct clk_parent_data){ 3086 .hw = &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 3087 }, 3088 .num_parents = 1, 3089 .flags = CLK_SET_RATE_PARENT, 3090 .ops = &clk_branch2_ops, 3091 }, 3092 }, 3093}; 3094 3095static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { 3096 .halt_reg = 0xf058, 3097 .halt_check = BRANCH_HALT, 3098 .clkr = { 3099 .enable_reg = 0xf058, 3100 .enable_mask = BIT(0), 3101 .hw.init = &(struct clk_init_data){ 3102 .name = "gcc_usb3_prim_phy_com_aux_clk", 3103 .parent_data = &(const struct clk_parent_data){ 3104 .hw = &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 3105 }, 3106 .num_parents = 1, 3107 .flags = CLK_SET_RATE_PARENT, 3108 .ops = &clk_branch2_ops, 3109 }, 3110 }, 3111}; 3112 3113static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { 3114 .halt_reg = 0xf05c, 3115 .halt_check = BRANCH_HALT_DELAY, 3116 .clkr = { 3117 .enable_reg = 0xf05c, 3118 .enable_mask = BIT(0), 3119 .hw.init = &(struct clk_init_data){ 3120 .name = "gcc_usb3_prim_phy_pipe_clk", 3121 .ops = &clk_branch2_ops, 3122 }, 3123 }, 3124}; 3125 3126static struct clk_branch gcc_usb3_sec_clkref_en = { 3127 .halt_reg = 0x8c010, 3128 .halt_check = BRANCH_HALT, 3129 .clkr = { 3130 .enable_reg = 0x8c010, 3131 .enable_mask = BIT(0), 3132 .hw.init = &(struct clk_init_data){ 3133 .name = "gcc_usb3_sec_clkref_en", 3134 .ops = &clk_branch2_ops, 3135 }, 3136 }, 3137}; 3138 3139static struct clk_branch gcc_usb3_sec_phy_aux_clk = { 3140 .halt_reg = 0x10054, 3141 .halt_check = BRANCH_HALT, 3142 .clkr = { 3143 .enable_reg = 0x10054, 3144 .enable_mask = BIT(0), 3145 .hw.init = &(struct clk_init_data){ 3146 .name = "gcc_usb3_sec_phy_aux_clk", 3147 .parent_data = &(const struct clk_parent_data){ 3148 .hw = &gcc_usb3_sec_phy_aux_clk_src.clkr.hw, 3149 }, 3150 .num_parents = 1, 3151 .flags = CLK_SET_RATE_PARENT, 3152 .ops = &clk_branch2_ops, 3153 }, 3154 }, 3155}; 3156 3157static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = { 3158 .halt_reg = 0x10058, 3159 .halt_check = BRANCH_HALT, 3160 .clkr = { 3161 .enable_reg = 0x10058, 3162 .enable_mask = BIT(0), 3163 .hw.init = &(struct clk_init_data){ 3164 .name = "gcc_usb3_sec_phy_com_aux_clk", 3165 .parent_data = &(const struct clk_parent_data){ 3166 .hw = &gcc_usb3_sec_phy_aux_clk_src.clkr.hw, 3167 }, 3168 .num_parents = 1, 3169 .flags = CLK_SET_RATE_PARENT, 3170 .ops = &clk_branch2_ops, 3171 }, 3172 }, 3173}; 3174 3175static struct clk_branch gcc_usb3_sec_phy_pipe_clk = { 3176 .halt_reg = 0x1005c, 3177 .halt_check = BRANCH_HALT_DELAY, 3178 .clkr = { 3179 .enable_reg = 0x1005c, 3180 .enable_mask = BIT(0), 3181 .hw.init = &(struct clk_init_data){ 3182 .name = "gcc_usb3_sec_phy_pipe_clk", 3183 .ops = &clk_branch2_ops, 3184 }, 3185 }, 3186}; 3187 3188static struct clk_branch gcc_video_axi0_clk = { 3189 .halt_reg = 0xb024, 3190 .halt_check = BRANCH_HALT_VOTED, 3191 .clkr = { 3192 .enable_reg = 0xb024, 3193 .enable_mask = BIT(0), 3194 .hw.init = &(struct clk_init_data){ 3195 .name = "gcc_video_axi0_clk", 3196 .ops = &clk_branch2_ops, 3197 }, 3198 }, 3199}; 3200 3201static struct clk_branch gcc_video_axi1_clk = { 3202 .halt_reg = 0xb028, 3203 .halt_check = BRANCH_HALT_VOTED, 3204 .clkr = { 3205 .enable_reg = 0xb028, 3206 .enable_mask = BIT(0), 3207 .hw.init = &(struct clk_init_data){ 3208 .name = "gcc_video_axi1_clk", 3209 .ops = &clk_branch2_ops, 3210 }, 3211 }, 3212}; 3213 3214static struct clk_branch gcc_video_xo_clk = { 3215 .halt_reg = 0xb03c, 3216 .halt_check = BRANCH_HALT, 3217 .clkr = { 3218 .enable_reg = 0xb03c, 3219 .enable_mask = BIT(0), 3220 .hw.init = &(struct clk_init_data){ 3221 .name = "gcc_video_xo_clk", 3222 .ops = &clk_branch2_ops, 3223 }, 3224 }, 3225}; 3226 3227static struct gdsc pcie_0_gdsc = { 3228 .gdscr = 0x6b004, 3229 .pd = { 3230 .name = "pcie_0_gdsc", 3231 }, 3232 .pwrsts = PWRSTS_OFF_ON, 3233}; 3234 3235static struct gdsc pcie_1_gdsc = { 3236 .gdscr = 0x8d004, 3237 .pd = { 3238 .name = "pcie_1_gdsc", 3239 }, 3240 .pwrsts = PWRSTS_OFF_ON, 3241}; 3242 3243static struct gdsc pcie_2_gdsc = { 3244 .gdscr = 0x6004, 3245 .pd = { 3246 .name = "pcie_2_gdsc", 3247 }, 3248 .pwrsts = PWRSTS_OFF_ON, 3249}; 3250 3251static struct gdsc ufs_card_gdsc = { 3252 .gdscr = 0x75004, 3253 .pd = { 3254 .name = "ufs_card_gdsc", 3255 }, 3256 .pwrsts = PWRSTS_OFF_ON, 3257}; 3258 3259static struct gdsc ufs_phy_gdsc = { 3260 .gdscr = 0x77004, 3261 .pd = { 3262 .name = "ufs_phy_gdsc", 3263 }, 3264 .pwrsts = PWRSTS_OFF_ON, 3265}; 3266 3267static struct gdsc usb30_prim_gdsc = { 3268 .gdscr = 0xf004, 3269 .pd = { 3270 .name = "usb30_prim_gdsc", 3271 }, 3272 .pwrsts = PWRSTS_RET_ON, 3273}; 3274 3275static struct gdsc usb30_sec_gdsc = { 3276 .gdscr = 0x10004, 3277 .pd = { 3278 .name = "usb30_sec_gdsc", 3279 }, 3280 .pwrsts = PWRSTS_RET_ON, 3281}; 3282 3283static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc = { 3284 .gdscr = 0x7d050, 3285 .pd = { 3286 .name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc", 3287 }, 3288 .pwrsts = PWRSTS_OFF_ON, 3289 .flags = VOTABLE, 3290}; 3291 3292static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc = { 3293 .gdscr = 0x7d058, 3294 .pd = { 3295 .name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc", 3296 }, 3297 .pwrsts = PWRSTS_OFF_ON, 3298 .flags = VOTABLE, 3299}; 3300 3301static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc = { 3302 .gdscr = 0x7d054, 3303 .pd = { 3304 .name = "hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc", 3305 }, 3306 .pwrsts = PWRSTS_OFF_ON, 3307 .flags = VOTABLE, 3308}; 3309 3310static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc = { 3311 .gdscr = 0x7d06c, 3312 .pd = { 3313 .name = "hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc", 3314 }, 3315 .pwrsts = PWRSTS_OFF_ON, 3316 .flags = VOTABLE, 3317}; 3318 3319static struct clk_regmap *gcc_sm8250_clocks[] = { 3320 [GCC_AGGRE_NOC_PCIE_TBU_CLK] = &gcc_aggre_noc_pcie_tbu_clk.clkr, 3321 [GCC_AGGRE_UFS_CARD_AXI_CLK] = &gcc_aggre_ufs_card_axi_clk.clkr, 3322 [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr, 3323 [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr, 3324 [GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr, 3325 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 3326 [GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr, 3327 [GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr, 3328 [GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr, 3329 [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, 3330 [GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr, 3331 [GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr, 3332 [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr, 3333 [GCC_CPUSS_AHB_POSTDIV_CLK_SRC] = &gcc_cpuss_ahb_postdiv_clk_src.clkr, 3334 [GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr, 3335 [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr, 3336 [GCC_DDRSS_PCIE_SF_TBU_CLK] = &gcc_ddrss_pcie_sf_tbu_clk.clkr, 3337 [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr, 3338 [GCC_DISP_SF_AXI_CLK] = &gcc_disp_sf_axi_clk.clkr, 3339 [GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr, 3340 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 3341 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, 3342 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 3343 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, 3344 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 3345 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, 3346 [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr, 3347 [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr, 3348 [GCC_GPU_IREF_EN] = &gcc_gpu_iref_en.clkr, 3349 [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr, 3350 [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, 3351 [GCC_NPU_AXI_CLK] = &gcc_npu_axi_clk.clkr, 3352 [GCC_NPU_BWMON_AXI_CLK] = &gcc_npu_bwmon_axi_clk.clkr, 3353 [GCC_NPU_BWMON_CFG_AHB_CLK] = &gcc_npu_bwmon_cfg_ahb_clk.clkr, 3354 [GCC_NPU_CFG_AHB_CLK] = &gcc_npu_cfg_ahb_clk.clkr, 3355 [GCC_NPU_DMA_CLK] = &gcc_npu_dma_clk.clkr, 3356 [GCC_NPU_GPLL0_CLK_SRC] = &gcc_npu_gpll0_clk_src.clkr, 3357 [GCC_NPU_GPLL0_DIV_CLK_SRC] = &gcc_npu_gpll0_div_clk_src.clkr, 3358 [GCC_PCIE0_PHY_REFGEN_CLK] = &gcc_pcie0_phy_refgen_clk.clkr, 3359 [GCC_PCIE1_PHY_REFGEN_CLK] = &gcc_pcie1_phy_refgen_clk.clkr, 3360 [GCC_PCIE2_PHY_REFGEN_CLK] = &gcc_pcie2_phy_refgen_clk.clkr, 3361 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr, 3362 [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr, 3363 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr, 3364 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr, 3365 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr, 3366 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr, 3367 [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr, 3368 [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr, 3369 [GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr, 3370 [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr, 3371 [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr, 3372 [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr, 3373 [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr, 3374 [GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr, 3375 [GCC_PCIE_2_AUX_CLK] = &gcc_pcie_2_aux_clk.clkr, 3376 [GCC_PCIE_2_AUX_CLK_SRC] = &gcc_pcie_2_aux_clk_src.clkr, 3377 [GCC_PCIE_2_CFG_AHB_CLK] = &gcc_pcie_2_cfg_ahb_clk.clkr, 3378 [GCC_PCIE_2_MSTR_AXI_CLK] = &gcc_pcie_2_mstr_axi_clk.clkr, 3379 [GCC_PCIE_2_PIPE_CLK] = &gcc_pcie_2_pipe_clk.clkr, 3380 [GCC_PCIE_2_SLV_AXI_CLK] = &gcc_pcie_2_slv_axi_clk.clkr, 3381 [GCC_PCIE_2_SLV_Q2A_AXI_CLK] = &gcc_pcie_2_slv_q2a_axi_clk.clkr, 3382 [GCC_PCIE_MDM_CLKREF_EN] = &gcc_pcie_mdm_clkref_en.clkr, 3383 [GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr, 3384 [GCC_PCIE_PHY_REFGEN_CLK_SRC] = &gcc_pcie_phy_refgen_clk_src.clkr, 3385 [GCC_PCIE_WIFI_CLKREF_EN] = &gcc_pcie_wifi_clkref_en.clkr, 3386 [GCC_PCIE_WIGIG_CLKREF_EN] = &gcc_pcie_wigig_clkref_en.clkr, 3387 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 3388 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, 3389 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 3390 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, 3391 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, 3392 [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr, 3393 [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr, 3394 [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr, 3395 [GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr, 3396 [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr, 3397 [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr, 3398 [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr, 3399 [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr, 3400 [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr, 3401 [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr, 3402 [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr, 3403 [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr, 3404 [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr, 3405 [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr, 3406 [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr, 3407 [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr, 3408 [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr, 3409 [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr, 3410 [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr, 3411 [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr, 3412 [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr, 3413 [GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr, 3414 [GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr, 3415 [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr, 3416 [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr, 3417 [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr, 3418 [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr, 3419 [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr, 3420 [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr, 3421 [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr, 3422 [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr, 3423 [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr, 3424 [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr, 3425 [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr, 3426 [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr, 3427 [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr, 3428 [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr, 3429 [GCC_QUPV3_WRAP2_CORE_2X_CLK] = &gcc_qupv3_wrap2_core_2x_clk.clkr, 3430 [GCC_QUPV3_WRAP2_CORE_CLK] = &gcc_qupv3_wrap2_core_clk.clkr, 3431 [GCC_QUPV3_WRAP2_S0_CLK] = &gcc_qupv3_wrap2_s0_clk.clkr, 3432 [GCC_QUPV3_WRAP2_S0_CLK_SRC] = &gcc_qupv3_wrap2_s0_clk_src.clkr, 3433 [GCC_QUPV3_WRAP2_S1_CLK] = &gcc_qupv3_wrap2_s1_clk.clkr, 3434 [GCC_QUPV3_WRAP2_S1_CLK_SRC] = &gcc_qupv3_wrap2_s1_clk_src.clkr, 3435 [GCC_QUPV3_WRAP2_S2_CLK] = &gcc_qupv3_wrap2_s2_clk.clkr, 3436 [GCC_QUPV3_WRAP2_S2_CLK_SRC] = &gcc_qupv3_wrap2_s2_clk_src.clkr, 3437 [GCC_QUPV3_WRAP2_S3_CLK] = &gcc_qupv3_wrap2_s3_clk.clkr, 3438 [GCC_QUPV3_WRAP2_S3_CLK_SRC] = &gcc_qupv3_wrap2_s3_clk_src.clkr, 3439 [GCC_QUPV3_WRAP2_S4_CLK] = &gcc_qupv3_wrap2_s4_clk.clkr, 3440 [GCC_QUPV3_WRAP2_S4_CLK_SRC] = &gcc_qupv3_wrap2_s4_clk_src.clkr, 3441 [GCC_QUPV3_WRAP2_S5_CLK] = &gcc_qupv3_wrap2_s5_clk.clkr, 3442 [GCC_QUPV3_WRAP2_S5_CLK_SRC] = &gcc_qupv3_wrap2_s5_clk_src.clkr, 3443 [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr, 3444 [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr, 3445 [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr, 3446 [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr, 3447 [GCC_QUPV3_WRAP_2_M_AHB_CLK] = &gcc_qupv3_wrap_2_m_ahb_clk.clkr, 3448 [GCC_QUPV3_WRAP_2_S_AHB_CLK] = &gcc_qupv3_wrap_2_s_ahb_clk.clkr, 3449 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, 3450 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, 3451 [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr, 3452 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr, 3453 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr, 3454 [GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr, 3455 [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr, 3456 [GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr, 3457 [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr, 3458 [GCC_TSIF_REF_CLK_SRC] = &gcc_tsif_ref_clk_src.clkr, 3459 [GCC_UFS_1X_CLKREF_EN] = &gcc_ufs_1x_clkref_en.clkr, 3460 [GCC_UFS_CARD_AHB_CLK] = &gcc_ufs_card_ahb_clk.clkr, 3461 [GCC_UFS_CARD_AXI_CLK] = &gcc_ufs_card_axi_clk.clkr, 3462 [GCC_UFS_CARD_AXI_CLK_SRC] = &gcc_ufs_card_axi_clk_src.clkr, 3463 [GCC_UFS_CARD_ICE_CORE_CLK] = &gcc_ufs_card_ice_core_clk.clkr, 3464 [GCC_UFS_CARD_ICE_CORE_CLK_SRC] = &gcc_ufs_card_ice_core_clk_src.clkr, 3465 [GCC_UFS_CARD_PHY_AUX_CLK] = &gcc_ufs_card_phy_aux_clk.clkr, 3466 [GCC_UFS_CARD_PHY_AUX_CLK_SRC] = &gcc_ufs_card_phy_aux_clk_src.clkr, 3467 [GCC_UFS_CARD_RX_SYMBOL_0_CLK] = &gcc_ufs_card_rx_symbol_0_clk.clkr, 3468 [GCC_UFS_CARD_RX_SYMBOL_1_CLK] = &gcc_ufs_card_rx_symbol_1_clk.clkr, 3469 [GCC_UFS_CARD_TX_SYMBOL_0_CLK] = &gcc_ufs_card_tx_symbol_0_clk.clkr, 3470 [GCC_UFS_CARD_UNIPRO_CORE_CLK] = &gcc_ufs_card_unipro_core_clk.clkr, 3471 [GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC] = 3472 &gcc_ufs_card_unipro_core_clk_src.clkr, 3473 [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr, 3474 [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr, 3475 [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr, 3476 [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr, 3477 [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr, 3478 [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr, 3479 [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr, 3480 [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr, 3481 [GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr, 3482 [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr, 3483 [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr, 3484 [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = 3485 &gcc_ufs_phy_unipro_core_clk_src.clkr, 3486 [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr, 3487 [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr, 3488 [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr, 3489 [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = 3490 &gcc_usb30_prim_mock_utmi_clk_src.clkr, 3491 [GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = 3492 &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr, 3493 [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr, 3494 [GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr, 3495 [GCC_USB30_SEC_MASTER_CLK_SRC] = &gcc_usb30_sec_master_clk_src.clkr, 3496 [GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr, 3497 [GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] = 3498 &gcc_usb30_sec_mock_utmi_clk_src.clkr, 3499 [GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC] = 3500 &gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr, 3501 [GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr, 3502 [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr, 3503 [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr, 3504 [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr, 3505 [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr, 3506 [GCC_USB3_SEC_CLKREF_EN] = &gcc_usb3_sec_clkref_en.clkr, 3507 [GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr, 3508 [GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr, 3509 [GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr, 3510 [GCC_USB3_SEC_PHY_PIPE_CLK] = &gcc_usb3_sec_phy_pipe_clk.clkr, 3511 [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr, 3512 [GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr, 3513 [GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr, 3514 [GPLL0] = &gpll0.clkr, 3515 [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr, 3516 [GPLL4] = &gpll4.clkr, 3517 [GPLL9] = &gpll9.clkr, 3518}; 3519 3520static struct gdsc *gcc_sm8250_gdscs[] = { 3521 [PCIE_0_GDSC] = &pcie_0_gdsc, 3522 [PCIE_1_GDSC] = &pcie_1_gdsc, 3523 [PCIE_2_GDSC] = &pcie_2_gdsc, 3524 [UFS_CARD_GDSC] = &ufs_card_gdsc, 3525 [UFS_PHY_GDSC] = &ufs_phy_gdsc, 3526 [USB30_PRIM_GDSC] = &usb30_prim_gdsc, 3527 [USB30_SEC_GDSC] = &usb30_sec_gdsc, 3528 [HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] = 3529 &hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc, 3530 [HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] = 3531 &hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc, 3532 [HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC] = 3533 &hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc, 3534 [HLOS1_VOTE_MMNOC_MMU_TBU_SF1_GDSC] = 3535 &hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc, 3536}; 3537 3538static const struct qcom_reset_map gcc_sm8250_resets[] = { 3539 [GCC_GPU_BCR] = { 0x71000 }, 3540 [GCC_MMSS_BCR] = { 0xb000 }, 3541 [GCC_NPU_BWMON_BCR] = { 0x73000 }, 3542 [GCC_NPU_BCR] = { 0x4d000 }, 3543 [GCC_PCIE_0_BCR] = { 0x6b000 }, 3544 [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 }, 3545 [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 }, 3546 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c }, 3547 [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x6c028 }, 3548 [GCC_PCIE_1_BCR] = { 0x8d000 }, 3549 [GCC_PCIE_1_LINK_DOWN_BCR] = { 0x8e014 }, 3550 [GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0x8e020 }, 3551 [GCC_PCIE_1_PHY_BCR] = { 0x8e01c }, 3552 [GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0x8e000 }, 3553 [GCC_PCIE_2_BCR] = { 0x6000 }, 3554 [GCC_PCIE_2_LINK_DOWN_BCR] = { 0x1f014 }, 3555 [GCC_PCIE_2_NOCSR_COM_PHY_BCR] = { 0x1f020 }, 3556 [GCC_PCIE_2_PHY_BCR] = { 0x1f01c }, 3557 [GCC_PCIE_2_PHY_NOCSR_COM_PHY_BCR] = { 0x1f028 }, 3558 [GCC_PCIE_PHY_BCR] = { 0x6f000 }, 3559 [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x6f00c }, 3560 [GCC_PCIE_PHY_COM_BCR] = { 0x6f010 }, 3561 [GCC_PDM_BCR] = { 0x33000 }, 3562 [GCC_PRNG_BCR] = { 0x34000 }, 3563 [GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 }, 3564 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 }, 3565 [GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 }, 3566 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 }, 3567 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 }, 3568 [GCC_SDCC2_BCR] = { 0x14000 }, 3569 [GCC_SDCC4_BCR] = { 0x16000 }, 3570 [GCC_TSIF_BCR] = { 0x36000 }, 3571 [GCC_UFS_CARD_BCR] = { 0x75000 }, 3572 [GCC_UFS_PHY_BCR] = { 0x77000 }, 3573 [GCC_USB30_PRIM_BCR] = { 0xf000 }, 3574 [GCC_USB30_SEC_BCR] = { 0x10000 }, 3575 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 }, 3576 [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 }, 3577 [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 }, 3578 [GCC_USB3_PHY_SEC_BCR] = { 0x5000c }, 3579 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 }, 3580 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 }, 3581 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 }, 3582 [GCC_VIDEO_AXI0_CLK_ARES] = { 0xb024, 2 }, 3583 [GCC_VIDEO_AXI1_CLK_ARES] = { 0xb028, 2 }, 3584}; 3585 3586static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = { 3587 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src), 3588 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src), 3589 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src), 3590 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src), 3591 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src), 3592 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src), 3593 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src), 3594 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src), 3595 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src), 3596 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src), 3597 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src), 3598 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src), 3599 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src), 3600 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src), 3601 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s0_clk_src), 3602 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s1_clk_src), 3603 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s2_clk_src), 3604 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s3_clk_src), 3605 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s4_clk_src), 3606 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s5_clk_src), 3607}; 3608 3609static const struct regmap_config gcc_sm8250_regmap_config = { 3610 .reg_bits = 32, 3611 .reg_stride = 4, 3612 .val_bits = 32, 3613 .max_register = 0x9c100, 3614 .fast_io = true, 3615}; 3616 3617static const struct qcom_cc_desc gcc_sm8250_desc = { 3618 .config = &gcc_sm8250_regmap_config, 3619 .clks = gcc_sm8250_clocks, 3620 .num_clks = ARRAY_SIZE(gcc_sm8250_clocks), 3621 .resets = gcc_sm8250_resets, 3622 .num_resets = ARRAY_SIZE(gcc_sm8250_resets), 3623 .gdscs = gcc_sm8250_gdscs, 3624 .num_gdscs = ARRAY_SIZE(gcc_sm8250_gdscs), 3625}; 3626 3627static const struct of_device_id gcc_sm8250_match_table[] = { 3628 { .compatible = "qcom,gcc-sm8250" }, 3629 { } 3630}; 3631MODULE_DEVICE_TABLE(of, gcc_sm8250_match_table); 3632 3633static int gcc_sm8250_probe(struct platform_device *pdev) 3634{ 3635 struct regmap *regmap; 3636 int ret; 3637 3638 regmap = qcom_cc_map(pdev, &gcc_sm8250_desc); 3639 if (IS_ERR(regmap)) 3640 return PTR_ERR(regmap); 3641 3642 /* 3643 * Disable the GPLL0 active input to NPU and GPU 3644 * via MISC registers. 3645 */ 3646 regmap_update_bits(regmap, 0x4d110, 0x3, 0x3); 3647 regmap_update_bits(regmap, 0x71028, 0x3, 0x3); 3648 3649 /* 3650 * Keep the clocks always-ON 3651 * GCC_VIDEO_AHB_CLK, GCC_CAMERA_AHB_CLK, GCC_DISP_AHB_CLK, 3652 * GCC_CPUSS_DVM_BUS_CLK, GCC_GPU_CFG_AHB_CLK, 3653 * GCC_SYS_NOC_CPUSS_AHB_CLK 3654 */ 3655 regmap_update_bits(regmap, 0x0b004, BIT(0), BIT(0)); 3656 regmap_update_bits(regmap, 0x0b008, BIT(0), BIT(0)); 3657 regmap_update_bits(regmap, 0x0b00c, BIT(0), BIT(0)); 3658 regmap_update_bits(regmap, 0x4818c, BIT(0), BIT(0)); 3659 regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); 3660 regmap_update_bits(regmap, 0x52000, BIT(0), BIT(0)); 3661 3662 ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, 3663 ARRAY_SIZE(gcc_dfs_clocks)); 3664 if (ret) 3665 return ret; 3666 3667 return qcom_cc_really_probe(pdev, &gcc_sm8250_desc, regmap); 3668} 3669 3670static struct platform_driver gcc_sm8250_driver = { 3671 .probe = gcc_sm8250_probe, 3672 .driver = { 3673 .name = "gcc-sm8250", 3674 .of_match_table = gcc_sm8250_match_table, 3675 }, 3676}; 3677 3678static int __init gcc_sm8250_init(void) 3679{ 3680 return platform_driver_register(&gcc_sm8250_driver); 3681} 3682subsys_initcall(gcc_sm8250_init); 3683 3684static void __exit gcc_sm8250_exit(void) 3685{ 3686 platform_driver_unregister(&gcc_sm8250_driver); 3687} 3688module_exit(gcc_sm8250_exit); 3689 3690MODULE_DESCRIPTION("QTI GCC SM8250 Driver"); 3691MODULE_LICENSE("GPL v2"); 3692