1// SPDX-License-Identifier: GPL-2.0-only 2/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. 3 */ 4 5#include <linux/kernel.h> 6#include <linux/init.h> 7#include <linux/err.h> 8#include <linux/ctype.h> 9#include <linux/io.h> 10#include <linux/of.h> 11#include <linux/platform_device.h> 12#include <linux/module.h> 13#include <linux/regmap.h> 14 15#include <dt-bindings/clock/qcom,gcc-msm8994.h> 16 17#include "common.h" 18#include "clk-regmap.h" 19#include "clk-alpha-pll.h" 20#include "clk-rcg.h" 21#include "clk-branch.h" 22#include "reset.h" 23#include "gdsc.h" 24 25enum { 26 P_XO, 27 P_GPLL0, 28 P_GPLL4, 29}; 30 31static const struct parent_map gcc_xo_gpll0_map[] = { 32 { P_XO, 0 }, 33 { P_GPLL0, 1 }, 34}; 35 36static const char * const gcc_xo_gpll0[] = { 37 "xo", 38 "gpll0", 39}; 40 41static const struct parent_map gcc_xo_gpll0_gpll4_map[] = { 42 { P_XO, 0 }, 43 { P_GPLL0, 1 }, 44 { P_GPLL4, 5 }, 45}; 46 47static const char * const gcc_xo_gpll0_gpll4[] = { 48 "xo", 49 "gpll0", 50 "gpll4", 51}; 52 53static struct clk_fixed_factor xo = { 54 .mult = 1, 55 .div = 1, 56 .hw.init = &(struct clk_init_data) 57 { 58 .name = "xo", 59 .parent_names = (const char *[]) { "xo_board" }, 60 .num_parents = 1, 61 .ops = &clk_fixed_factor_ops, 62 }, 63}; 64 65static struct clk_alpha_pll gpll0_early = { 66 .offset = 0x00000, 67 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 68 .clkr = { 69 .enable_reg = 0x1480, 70 .enable_mask = BIT(0), 71 .hw.init = &(struct clk_init_data) 72 { 73 .name = "gpll0_early", 74 .parent_names = (const char *[]) { "xo" }, 75 .num_parents = 1, 76 .ops = &clk_alpha_pll_ops, 77 }, 78 }, 79}; 80 81static struct clk_alpha_pll_postdiv gpll0 = { 82 .offset = 0x00000, 83 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 84 .clkr.hw.init = &(struct clk_init_data) 85 { 86 .name = "gpll0", 87 .parent_names = (const char *[]) { "gpll0_early" }, 88 .num_parents = 1, 89 .ops = &clk_alpha_pll_postdiv_ops, 90 }, 91}; 92 93static struct clk_alpha_pll gpll4_early = { 94 .offset = 0x1dc0, 95 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 96 .clkr = { 97 .enable_reg = 0x1480, 98 .enable_mask = BIT(4), 99 .hw.init = &(struct clk_init_data) 100 { 101 .name = "gpll4_early", 102 .parent_names = (const char *[]) { "xo" }, 103 .num_parents = 1, 104 .ops = &clk_alpha_pll_ops, 105 }, 106 }, 107}; 108 109static struct clk_alpha_pll_postdiv gpll4 = { 110 .offset = 0x1dc0, 111 .width = 4, 112 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 113 .clkr.hw.init = &(struct clk_init_data) 114 { 115 .name = "gpll4", 116 .parent_names = (const char *[]) { "gpll4_early" }, 117 .num_parents = 1, 118 .ops = &clk_alpha_pll_postdiv_ops, 119 }, 120}; 121 122static struct freq_tbl ftbl_ufs_axi_clk_src[] = { 123 F(50000000, P_GPLL0, 12, 0, 0), 124 F(100000000, P_GPLL0, 6, 0, 0), 125 F(150000000, P_GPLL0, 4, 0, 0), 126 F(171430000, P_GPLL0, 3.5, 0, 0), 127 F(200000000, P_GPLL0, 3, 0, 0), 128 F(240000000, P_GPLL0, 2.5, 0, 0), 129 { } 130}; 131 132static struct clk_rcg2 ufs_axi_clk_src = { 133 .cmd_rcgr = 0x1d68, 134 .mnd_width = 8, 135 .hid_width = 5, 136 .parent_map = gcc_xo_gpll0_map, 137 .freq_tbl = ftbl_ufs_axi_clk_src, 138 .clkr.hw.init = &(struct clk_init_data) 139 { 140 .name = "ufs_axi_clk_src", 141 .parent_names = gcc_xo_gpll0, 142 .num_parents = 2, 143 .ops = &clk_rcg2_ops, 144 }, 145}; 146 147static struct freq_tbl ftbl_usb30_master_clk_src[] = { 148 F(19200000, P_XO, 1, 0, 0), 149 F(125000000, P_GPLL0, 1, 5, 24), 150 { } 151}; 152 153static struct clk_rcg2 usb30_master_clk_src = { 154 .cmd_rcgr = 0x03d4, 155 .mnd_width = 8, 156 .hid_width = 5, 157 .parent_map = gcc_xo_gpll0_map, 158 .freq_tbl = ftbl_usb30_master_clk_src, 159 .clkr.hw.init = &(struct clk_init_data) 160 { 161 .name = "usb30_master_clk_src", 162 .parent_names = gcc_xo_gpll0, 163 .num_parents = 2, 164 .ops = &clk_rcg2_ops, 165 }, 166}; 167 168static struct freq_tbl ftbl_blsp_i2c_apps_clk_src[] = { 169 F(19200000, P_XO, 1, 0, 0), 170 F(50000000, P_GPLL0, 12, 0, 0), 171 { } 172}; 173 174static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = { 175 .cmd_rcgr = 0x0660, 176 .hid_width = 5, 177 .parent_map = gcc_xo_gpll0_map, 178 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 179 .clkr.hw.init = &(struct clk_init_data) 180 { 181 .name = "blsp1_qup1_i2c_apps_clk_src", 182 .parent_names = gcc_xo_gpll0, 183 .num_parents = 2, 184 .ops = &clk_rcg2_ops, 185 }, 186}; 187 188static struct freq_tbl ftbl_blspqup_spi_apps_clk_src[] = { 189 F(960000, P_XO, 10, 1, 2), 190 F(4800000, P_XO, 4, 0, 0), 191 F(9600000, P_XO, 2, 0, 0), 192 F(15000000, P_GPLL0, 10, 1, 4), 193 F(19200000, P_XO, 1, 0, 0), 194 F(24000000, P_GPLL0, 12.5, 1, 2), 195 F(25000000, P_GPLL0, 12, 1, 2), 196 F(48000000, P_GPLL0, 12.5, 0, 0), 197 F(50000000, P_GPLL0, 12, 0, 0), 198 { } 199}; 200 201static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = { 202 .cmd_rcgr = 0x064c, 203 .mnd_width = 8, 204 .hid_width = 5, 205 .parent_map = gcc_xo_gpll0_map, 206 .freq_tbl = ftbl_blspqup_spi_apps_clk_src, 207 .clkr.hw.init = &(struct clk_init_data) 208 { 209 .name = "blsp1_qup1_spi_apps_clk_src", 210 .parent_names = gcc_xo_gpll0, 211 .num_parents = 2, 212 .ops = &clk_rcg2_ops, 213 }, 214}; 215 216static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = { 217 .cmd_rcgr = 0x06e0, 218 .hid_width = 5, 219 .parent_map = gcc_xo_gpll0_map, 220 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 221 .clkr.hw.init = &(struct clk_init_data) 222 { 223 .name = "blsp1_qup2_i2c_apps_clk_src", 224 .parent_names = gcc_xo_gpll0, 225 .num_parents = 2, 226 .ops = &clk_rcg2_ops, 227 }, 228}; 229 230static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = { 231 .cmd_rcgr = 0x06cc, 232 .mnd_width = 8, 233 .hid_width = 5, 234 .parent_map = gcc_xo_gpll0_map, 235 .freq_tbl = ftbl_blspqup_spi_apps_clk_src, 236 .clkr.hw.init = &(struct clk_init_data) 237 { 238 .name = "blsp1_qup2_spi_apps_clk_src", 239 .parent_names = gcc_xo_gpll0, 240 .num_parents = 2, 241 .ops = &clk_rcg2_ops, 242 }, 243}; 244 245static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = { 246 .cmd_rcgr = 0x0760, 247 .hid_width = 5, 248 .parent_map = gcc_xo_gpll0_map, 249 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 250 .clkr.hw.init = &(struct clk_init_data) 251 { 252 .name = "blsp1_qup3_i2c_apps_clk_src", 253 .parent_names = gcc_xo_gpll0, 254 .num_parents = 2, 255 .ops = &clk_rcg2_ops, 256 }, 257}; 258 259static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = { 260 .cmd_rcgr = 0x074c, 261 .mnd_width = 8, 262 .hid_width = 5, 263 .parent_map = gcc_xo_gpll0_map, 264 .freq_tbl = ftbl_blspqup_spi_apps_clk_src, 265 .clkr.hw.init = &(struct clk_init_data) 266 { 267 .name = "blsp1_qup3_spi_apps_clk_src", 268 .parent_names = gcc_xo_gpll0, 269 .num_parents = 2, 270 .ops = &clk_rcg2_ops, 271 }, 272}; 273 274static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = { 275 .cmd_rcgr = 0x07e0, 276 .hid_width = 5, 277 .parent_map = gcc_xo_gpll0_map, 278 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 279 .clkr.hw.init = &(struct clk_init_data) 280 { 281 .name = "blsp1_qup4_i2c_apps_clk_src", 282 .parent_names = gcc_xo_gpll0, 283 .num_parents = 2, 284 .ops = &clk_rcg2_ops, 285 }, 286}; 287 288static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = { 289 .cmd_rcgr = 0x07cc, 290 .mnd_width = 8, 291 .hid_width = 5, 292 .parent_map = gcc_xo_gpll0_map, 293 .freq_tbl = ftbl_blspqup_spi_apps_clk_src, 294 .clkr.hw.init = &(struct clk_init_data) 295 { 296 .name = "blsp1_qup4_spi_apps_clk_src", 297 .parent_names = gcc_xo_gpll0, 298 .num_parents = 2, 299 .ops = &clk_rcg2_ops, 300 }, 301}; 302 303static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = { 304 .cmd_rcgr = 0x0860, 305 .hid_width = 5, 306 .parent_map = gcc_xo_gpll0_map, 307 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 308 .clkr.hw.init = &(struct clk_init_data) 309 { 310 .name = "blsp1_qup5_i2c_apps_clk_src", 311 .parent_names = gcc_xo_gpll0, 312 .num_parents = 2, 313 .ops = &clk_rcg2_ops, 314 }, 315}; 316 317static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = { 318 .cmd_rcgr = 0x084c, 319 .mnd_width = 8, 320 .hid_width = 5, 321 .parent_map = gcc_xo_gpll0_map, 322 .freq_tbl = ftbl_blspqup_spi_apps_clk_src, 323 .clkr.hw.init = &(struct clk_init_data) 324 { 325 .name = "blsp1_qup5_spi_apps_clk_src", 326 .parent_names = gcc_xo_gpll0, 327 .num_parents = 2, 328 .ops = &clk_rcg2_ops, 329 }, 330}; 331 332static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = { 333 .cmd_rcgr = 0x08e0, 334 .hid_width = 5, 335 .parent_map = gcc_xo_gpll0_map, 336 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 337 .clkr.hw.init = &(struct clk_init_data) 338 { 339 .name = "blsp1_qup6_i2c_apps_clk_src", 340 .parent_names = gcc_xo_gpll0, 341 .num_parents = 2, 342 .ops = &clk_rcg2_ops, 343 }, 344}; 345 346static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = { 347 .cmd_rcgr = 0x08cc, 348 .mnd_width = 8, 349 .hid_width = 5, 350 .parent_map = gcc_xo_gpll0_map, 351 .freq_tbl = ftbl_blspqup_spi_apps_clk_src, 352 .clkr.hw.init = &(struct clk_init_data) 353 { 354 .name = "blsp1_qup6_spi_apps_clk_src", 355 .parent_names = gcc_xo_gpll0, 356 .num_parents = 2, 357 .ops = &clk_rcg2_ops, 358 }, 359}; 360 361static struct freq_tbl ftbl_blsp_uart_apps_clk_src[] = { 362 F(3686400, P_GPLL0, 1, 96, 15625), 363 F(7372800, P_GPLL0, 1, 192, 15625), 364 F(14745600, P_GPLL0, 1, 384, 15625), 365 F(16000000, P_GPLL0, 5, 2, 15), 366 F(19200000, P_XO, 1, 0, 0), 367 F(24000000, P_GPLL0, 5, 1, 5), 368 F(32000000, P_GPLL0, 1, 4, 75), 369 F(40000000, P_GPLL0, 15, 0, 0), 370 F(46400000, P_GPLL0, 1, 29, 375), 371 F(48000000, P_GPLL0, 12.5, 0, 0), 372 F(51200000, P_GPLL0, 1, 32, 375), 373 F(56000000, P_GPLL0, 1, 7, 75), 374 F(58982400, P_GPLL0, 1, 1536, 15625), 375 F(60000000, P_GPLL0, 10, 0, 0), 376 F(63160000, P_GPLL0, 9.5, 0, 0), 377 { } 378}; 379 380static struct clk_rcg2 blsp1_uart1_apps_clk_src = { 381 .cmd_rcgr = 0x068c, 382 .mnd_width = 16, 383 .hid_width = 5, 384 .parent_map = gcc_xo_gpll0_map, 385 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 386 .clkr.hw.init = &(struct clk_init_data) 387 { 388 .name = "blsp1_uart1_apps_clk_src", 389 .parent_names = gcc_xo_gpll0, 390 .num_parents = 2, 391 .ops = &clk_rcg2_ops, 392 }, 393}; 394 395static struct clk_rcg2 blsp1_uart2_apps_clk_src = { 396 .cmd_rcgr = 0x070c, 397 .mnd_width = 16, 398 .hid_width = 5, 399 .parent_map = gcc_xo_gpll0_map, 400 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 401 .clkr.hw.init = &(struct clk_init_data) 402 { 403 .name = "blsp1_uart2_apps_clk_src", 404 .parent_names = gcc_xo_gpll0, 405 .num_parents = 2, 406 .ops = &clk_rcg2_ops, 407 }, 408}; 409 410static struct clk_rcg2 blsp1_uart3_apps_clk_src = { 411 .cmd_rcgr = 0x078c, 412 .mnd_width = 16, 413 .hid_width = 5, 414 .parent_map = gcc_xo_gpll0_map, 415 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 416 .clkr.hw.init = &(struct clk_init_data) 417 { 418 .name = "blsp1_uart3_apps_clk_src", 419 .parent_names = gcc_xo_gpll0, 420 .num_parents = 2, 421 .ops = &clk_rcg2_ops, 422 }, 423}; 424 425static struct clk_rcg2 blsp1_uart4_apps_clk_src = { 426 .cmd_rcgr = 0x080c, 427 .mnd_width = 16, 428 .hid_width = 5, 429 .parent_map = gcc_xo_gpll0_map, 430 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 431 .clkr.hw.init = &(struct clk_init_data) 432 { 433 .name = "blsp1_uart4_apps_clk_src", 434 .parent_names = gcc_xo_gpll0, 435 .num_parents = 2, 436 .ops = &clk_rcg2_ops, 437 }, 438}; 439 440static struct clk_rcg2 blsp1_uart5_apps_clk_src = { 441 .cmd_rcgr = 0x088c, 442 .mnd_width = 16, 443 .hid_width = 5, 444 .parent_map = gcc_xo_gpll0_map, 445 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 446 .clkr.hw.init = &(struct clk_init_data) 447 { 448 .name = "blsp1_uart5_apps_clk_src", 449 .parent_names = gcc_xo_gpll0, 450 .num_parents = 2, 451 .ops = &clk_rcg2_ops, 452 }, 453}; 454 455static struct clk_rcg2 blsp1_uart6_apps_clk_src = { 456 .cmd_rcgr = 0x090c, 457 .mnd_width = 16, 458 .hid_width = 5, 459 .parent_map = gcc_xo_gpll0_map, 460 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 461 .clkr.hw.init = &(struct clk_init_data) 462 { 463 .name = "blsp1_uart6_apps_clk_src", 464 .parent_names = gcc_xo_gpll0, 465 .num_parents = 2, 466 .ops = &clk_rcg2_ops, 467 }, 468}; 469 470static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = { 471 .cmd_rcgr = 0x09a0, 472 .hid_width = 5, 473 .parent_map = gcc_xo_gpll0_map, 474 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 475 .clkr.hw.init = &(struct clk_init_data) 476 { 477 .name = "blsp2_qup1_i2c_apps_clk_src", 478 .parent_names = gcc_xo_gpll0, 479 .num_parents = 2, 480 .ops = &clk_rcg2_ops, 481 }, 482}; 483 484static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = { 485 .cmd_rcgr = 0x098c, 486 .mnd_width = 8, 487 .hid_width = 5, 488 .parent_map = gcc_xo_gpll0_map, 489 .freq_tbl = ftbl_blspqup_spi_apps_clk_src, 490 .clkr.hw.init = &(struct clk_init_data) 491 { 492 .name = "blsp2_qup1_spi_apps_clk_src", 493 .parent_names = gcc_xo_gpll0, 494 .num_parents = 2, 495 .ops = &clk_rcg2_ops, 496 }, 497}; 498 499static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = { 500 .cmd_rcgr = 0x0a20, 501 .hid_width = 5, 502 .parent_map = gcc_xo_gpll0_map, 503 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 504 .clkr.hw.init = &(struct clk_init_data) 505 { 506 .name = "blsp2_qup2_i2c_apps_clk_src", 507 .parent_names = gcc_xo_gpll0, 508 .num_parents = 2, 509 .ops = &clk_rcg2_ops, 510 }, 511}; 512 513static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = { 514 .cmd_rcgr = 0x0a0c, 515 .mnd_width = 8, 516 .hid_width = 5, 517 .parent_map = gcc_xo_gpll0_map, 518 .freq_tbl = ftbl_blspqup_spi_apps_clk_src, 519 .clkr.hw.init = &(struct clk_init_data) 520 { 521 .name = "blsp2_qup2_spi_apps_clk_src", 522 .parent_names = gcc_xo_gpll0, 523 .num_parents = 2, 524 .ops = &clk_rcg2_ops, 525 }, 526}; 527 528static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = { 529 .cmd_rcgr = 0x0aa0, 530 .hid_width = 5, 531 .parent_map = gcc_xo_gpll0_map, 532 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 533 .clkr.hw.init = &(struct clk_init_data) 534 { 535 .name = "blsp2_qup3_i2c_apps_clk_src", 536 .parent_names = gcc_xo_gpll0, 537 .num_parents = 2, 538 .ops = &clk_rcg2_ops, 539 }, 540}; 541 542static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = { 543 .cmd_rcgr = 0x0a8c, 544 .mnd_width = 8, 545 .hid_width = 5, 546 .parent_map = gcc_xo_gpll0_map, 547 .freq_tbl = ftbl_blspqup_spi_apps_clk_src, 548 .clkr.hw.init = &(struct clk_init_data) 549 { 550 .name = "blsp2_qup3_spi_apps_clk_src", 551 .parent_names = gcc_xo_gpll0, 552 .num_parents = 2, 553 .ops = &clk_rcg2_ops, 554 }, 555}; 556 557static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = { 558 .cmd_rcgr = 0x0b20, 559 .hid_width = 5, 560 .parent_map = gcc_xo_gpll0_map, 561 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 562 .clkr.hw.init = &(struct clk_init_data) 563 { 564 .name = "blsp2_qup4_i2c_apps_clk_src", 565 .parent_names = gcc_xo_gpll0, 566 .num_parents = 2, 567 .ops = &clk_rcg2_ops, 568 }, 569}; 570 571static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = { 572 .cmd_rcgr = 0x0b0c, 573 .mnd_width = 8, 574 .hid_width = 5, 575 .parent_map = gcc_xo_gpll0_map, 576 .freq_tbl = ftbl_blspqup_spi_apps_clk_src, 577 .clkr.hw.init = &(struct clk_init_data) 578 { 579 .name = "blsp2_qup4_spi_apps_clk_src", 580 .parent_names = gcc_xo_gpll0, 581 .num_parents = 2, 582 .ops = &clk_rcg2_ops, 583 }, 584}; 585 586static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = { 587 .cmd_rcgr = 0x0ba0, 588 .hid_width = 5, 589 .parent_map = gcc_xo_gpll0_map, 590 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 591 .clkr.hw.init = &(struct clk_init_data) 592 { 593 .name = "blsp2_qup5_i2c_apps_clk_src", 594 .parent_names = gcc_xo_gpll0, 595 .num_parents = 2, 596 .ops = &clk_rcg2_ops, 597 }, 598}; 599 600static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = { 601 .cmd_rcgr = 0x0b8c, 602 .mnd_width = 8, 603 .hid_width = 5, 604 .parent_map = gcc_xo_gpll0_map, 605 .freq_tbl = ftbl_blspqup_spi_apps_clk_src, 606 .clkr.hw.init = &(struct clk_init_data) 607 { 608 .name = "blsp2_qup5_spi_apps_clk_src", 609 .parent_names = gcc_xo_gpll0, 610 .num_parents = 2, 611 .ops = &clk_rcg2_ops, 612 }, 613}; 614 615static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = { 616 .cmd_rcgr = 0x0c20, 617 .hid_width = 5, 618 .parent_map = gcc_xo_gpll0_map, 619 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 620 .clkr.hw.init = &(struct clk_init_data) 621 { 622 .name = "blsp2_qup6_i2c_apps_clk_src", 623 .parent_names = gcc_xo_gpll0, 624 .num_parents = 2, 625 .ops = &clk_rcg2_ops, 626 }, 627}; 628 629static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = { 630 .cmd_rcgr = 0x0c0c, 631 .mnd_width = 8, 632 .hid_width = 5, 633 .parent_map = gcc_xo_gpll0_map, 634 .freq_tbl = ftbl_blspqup_spi_apps_clk_src, 635 .clkr.hw.init = &(struct clk_init_data) 636 { 637 .name = "blsp2_qup6_spi_apps_clk_src", 638 .parent_names = gcc_xo_gpll0, 639 .num_parents = 2, 640 .ops = &clk_rcg2_ops, 641 }, 642}; 643 644static struct clk_rcg2 blsp2_uart1_apps_clk_src = { 645 .cmd_rcgr = 0x09cc, 646 .mnd_width = 16, 647 .hid_width = 5, 648 .parent_map = gcc_xo_gpll0_map, 649 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 650 .clkr.hw.init = &(struct clk_init_data) 651 { 652 .name = "blsp2_uart1_apps_clk_src", 653 .parent_names = gcc_xo_gpll0, 654 .num_parents = 2, 655 .ops = &clk_rcg2_ops, 656 }, 657}; 658 659static struct clk_rcg2 blsp2_uart2_apps_clk_src = { 660 .cmd_rcgr = 0x0a4c, 661 .mnd_width = 16, 662 .hid_width = 5, 663 .parent_map = gcc_xo_gpll0_map, 664 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 665 .clkr.hw.init = &(struct clk_init_data) 666 { 667 .name = "blsp2_uart2_apps_clk_src", 668 .parent_names = gcc_xo_gpll0, 669 .num_parents = 2, 670 .ops = &clk_rcg2_ops, 671 }, 672}; 673 674static struct clk_rcg2 blsp2_uart3_apps_clk_src = { 675 .cmd_rcgr = 0x0acc, 676 .mnd_width = 16, 677 .hid_width = 5, 678 .parent_map = gcc_xo_gpll0_map, 679 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 680 .clkr.hw.init = &(struct clk_init_data) 681 { 682 .name = "blsp2_uart3_apps_clk_src", 683 .parent_names = gcc_xo_gpll0, 684 .num_parents = 2, 685 .ops = &clk_rcg2_ops, 686 }, 687}; 688 689static struct clk_rcg2 blsp2_uart4_apps_clk_src = { 690 .cmd_rcgr = 0x0b4c, 691 .mnd_width = 16, 692 .hid_width = 5, 693 .parent_map = gcc_xo_gpll0_map, 694 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 695 .clkr.hw.init = &(struct clk_init_data) 696 { 697 .name = "blsp2_uart4_apps_clk_src", 698 .parent_names = gcc_xo_gpll0, 699 .num_parents = 2, 700 .ops = &clk_rcg2_ops, 701 }, 702}; 703 704static struct clk_rcg2 blsp2_uart5_apps_clk_src = { 705 .cmd_rcgr = 0x0bcc, 706 .mnd_width = 16, 707 .hid_width = 5, 708 .parent_map = gcc_xo_gpll0_map, 709 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 710 .clkr.hw.init = &(struct clk_init_data) 711 { 712 .name = "blsp2_uart5_apps_clk_src", 713 .parent_names = gcc_xo_gpll0, 714 .num_parents = 2, 715 .ops = &clk_rcg2_ops, 716 }, 717}; 718 719static struct clk_rcg2 blsp2_uart6_apps_clk_src = { 720 .cmd_rcgr = 0x0c4c, 721 .mnd_width = 16, 722 .hid_width = 5, 723 .parent_map = gcc_xo_gpll0_map, 724 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 725 .clkr.hw.init = &(struct clk_init_data) 726 { 727 .name = "blsp2_uart6_apps_clk_src", 728 .parent_names = gcc_xo_gpll0, 729 .num_parents = 2, 730 .ops = &clk_rcg2_ops, 731 }, 732}; 733 734static struct freq_tbl ftbl_gp1_clk_src[] = { 735 F(19200000, P_XO, 1, 0, 0), 736 F(100000000, P_GPLL0, 6, 0, 0), 737 F(200000000, P_GPLL0, 3, 0, 0), 738 { } 739}; 740 741static struct clk_rcg2 gp1_clk_src = { 742 .cmd_rcgr = 0x1904, 743 .mnd_width = 8, 744 .hid_width = 5, 745 .parent_map = gcc_xo_gpll0_map, 746 .freq_tbl = ftbl_gp1_clk_src, 747 .clkr.hw.init = &(struct clk_init_data) 748 { 749 .name = "gp1_clk_src", 750 .parent_names = gcc_xo_gpll0, 751 .num_parents = 2, 752 .ops = &clk_rcg2_ops, 753 }, 754}; 755 756static struct freq_tbl ftbl_gp2_clk_src[] = { 757 F(19200000, P_XO, 1, 0, 0), 758 F(100000000, P_GPLL0, 6, 0, 0), 759 F(200000000, P_GPLL0, 3, 0, 0), 760 { } 761}; 762 763static struct clk_rcg2 gp2_clk_src = { 764 .cmd_rcgr = 0x1944, 765 .mnd_width = 8, 766 .hid_width = 5, 767 .parent_map = gcc_xo_gpll0_map, 768 .freq_tbl = ftbl_gp2_clk_src, 769 .clkr.hw.init = &(struct clk_init_data) 770 { 771 .name = "gp2_clk_src", 772 .parent_names = gcc_xo_gpll0, 773 .num_parents = 2, 774 .ops = &clk_rcg2_ops, 775 }, 776}; 777 778static struct freq_tbl ftbl_gp3_clk_src[] = { 779 F(19200000, P_XO, 1, 0, 0), 780 F(100000000, P_GPLL0, 6, 0, 0), 781 F(200000000, P_GPLL0, 3, 0, 0), 782 { } 783}; 784 785static struct clk_rcg2 gp3_clk_src = { 786 .cmd_rcgr = 0x1984, 787 .mnd_width = 8, 788 .hid_width = 5, 789 .parent_map = gcc_xo_gpll0_map, 790 .freq_tbl = ftbl_gp3_clk_src, 791 .clkr.hw.init = &(struct clk_init_data) 792 { 793 .name = "gp3_clk_src", 794 .parent_names = gcc_xo_gpll0, 795 .num_parents = 2, 796 .ops = &clk_rcg2_ops, 797 }, 798}; 799 800static struct freq_tbl ftbl_pcie_0_aux_clk_src[] = { 801 F(1011000, P_XO, 1, 1, 19), 802 { } 803}; 804 805static struct clk_rcg2 pcie_0_aux_clk_src = { 806 .cmd_rcgr = 0x1b00, 807 .mnd_width = 8, 808 .hid_width = 5, 809 .freq_tbl = ftbl_pcie_0_aux_clk_src, 810 .clkr.hw.init = &(struct clk_init_data) 811 { 812 .name = "pcie_0_aux_clk_src", 813 .parent_names = (const char *[]) { "xo" }, 814 .num_parents = 1, 815 .ops = &clk_rcg2_ops, 816 }, 817}; 818 819static struct freq_tbl ftbl_pcie_pipe_clk_src[] = { 820 F(125000000, P_XO, 1, 0, 0), 821 { } 822}; 823 824static struct clk_rcg2 pcie_0_pipe_clk_src = { 825 .cmd_rcgr = 0x1adc, 826 .hid_width = 5, 827 .freq_tbl = ftbl_pcie_pipe_clk_src, 828 .clkr.hw.init = &(struct clk_init_data) 829 { 830 .name = "pcie_0_pipe_clk_src", 831 .parent_names = (const char *[]) { "xo" }, 832 .num_parents = 1, 833 .ops = &clk_rcg2_ops, 834 }, 835}; 836 837static struct freq_tbl ftbl_pcie_1_aux_clk_src[] = { 838 F(1011000, P_XO, 1, 1, 19), 839 { } 840}; 841 842static struct clk_rcg2 pcie_1_aux_clk_src = { 843 .cmd_rcgr = 0x1b80, 844 .mnd_width = 8, 845 .hid_width = 5, 846 .freq_tbl = ftbl_pcie_1_aux_clk_src, 847 .clkr.hw.init = &(struct clk_init_data) 848 { 849 .name = "pcie_1_aux_clk_src", 850 .parent_names = (const char *[]) { "xo" }, 851 .num_parents = 1, 852 .ops = &clk_rcg2_ops, 853 }, 854}; 855 856static struct clk_rcg2 pcie_1_pipe_clk_src = { 857 .cmd_rcgr = 0x1b5c, 858 .hid_width = 5, 859 .freq_tbl = ftbl_pcie_pipe_clk_src, 860 .clkr.hw.init = &(struct clk_init_data) 861 { 862 .name = "pcie_1_pipe_clk_src", 863 .parent_names = (const char *[]) { "xo" }, 864 .num_parents = 1, 865 .ops = &clk_rcg2_ops, 866 }, 867}; 868 869static struct freq_tbl ftbl_pdm2_clk_src[] = { 870 F(60000000, P_GPLL0, 10, 0, 0), 871 { } 872}; 873 874static struct clk_rcg2 pdm2_clk_src = { 875 .cmd_rcgr = 0x0cd0, 876 .hid_width = 5, 877 .parent_map = gcc_xo_gpll0_map, 878 .freq_tbl = ftbl_pdm2_clk_src, 879 .clkr.hw.init = &(struct clk_init_data) 880 { 881 .name = "pdm2_clk_src", 882 .parent_names = gcc_xo_gpll0, 883 .num_parents = 2, 884 .ops = &clk_rcg2_ops, 885 }, 886}; 887 888static struct freq_tbl ftbl_sdcc1_apps_clk_src[] = { 889 F(144000, P_XO, 16, 3, 25), 890 F(400000, P_XO, 12, 1, 4), 891 F(20000000, P_GPLL0, 15, 1, 2), 892 F(25000000, P_GPLL0, 12, 1, 2), 893 F(50000000, P_GPLL0, 12, 0, 0), 894 F(100000000, P_GPLL0, 6, 0, 0), 895 F(192000000, P_GPLL4, 2, 0, 0), 896 F(384000000, P_GPLL4, 1, 0, 0), 897 { } 898}; 899 900static struct clk_rcg2 sdcc1_apps_clk_src = { 901 .cmd_rcgr = 0x04d0, 902 .mnd_width = 8, 903 .hid_width = 5, 904 .parent_map = gcc_xo_gpll0_gpll4_map, 905 .freq_tbl = ftbl_sdcc1_apps_clk_src, 906 .clkr.hw.init = &(struct clk_init_data) 907 { 908 .name = "sdcc1_apps_clk_src", 909 .parent_names = gcc_xo_gpll0_gpll4, 910 .num_parents = 3, 911 .ops = &clk_rcg2_floor_ops, 912 }, 913}; 914 915static struct freq_tbl ftbl_sdcc2_4_apps_clk_src[] = { 916 F(144000, P_XO, 16, 3, 25), 917 F(400000, P_XO, 12, 1, 4), 918 F(20000000, P_GPLL0, 15, 1, 2), 919 F(25000000, P_GPLL0, 12, 1, 2), 920 F(50000000, P_GPLL0, 12, 0, 0), 921 F(100000000, P_GPLL0, 6, 0, 0), 922 F(200000000, P_GPLL0, 3, 0, 0), 923 { } 924}; 925 926static struct clk_rcg2 sdcc2_apps_clk_src = { 927 .cmd_rcgr = 0x0510, 928 .mnd_width = 8, 929 .hid_width = 5, 930 .parent_map = gcc_xo_gpll0_map, 931 .freq_tbl = ftbl_sdcc2_4_apps_clk_src, 932 .clkr.hw.init = &(struct clk_init_data) 933 { 934 .name = "sdcc2_apps_clk_src", 935 .parent_names = gcc_xo_gpll0, 936 .num_parents = 2, 937 .ops = &clk_rcg2_floor_ops, 938 }, 939}; 940 941static struct clk_rcg2 sdcc3_apps_clk_src = { 942 .cmd_rcgr = 0x0550, 943 .mnd_width = 8, 944 .hid_width = 5, 945 .parent_map = gcc_xo_gpll0_map, 946 .freq_tbl = ftbl_sdcc2_4_apps_clk_src, 947 .clkr.hw.init = &(struct clk_init_data) 948 { 949 .name = "sdcc3_apps_clk_src", 950 .parent_names = gcc_xo_gpll0, 951 .num_parents = 2, 952 .ops = &clk_rcg2_floor_ops, 953 }, 954}; 955 956static struct clk_rcg2 sdcc4_apps_clk_src = { 957 .cmd_rcgr = 0x0590, 958 .mnd_width = 8, 959 .hid_width = 5, 960 .parent_map = gcc_xo_gpll0_map, 961 .freq_tbl = ftbl_sdcc2_4_apps_clk_src, 962 .clkr.hw.init = &(struct clk_init_data) 963 { 964 .name = "sdcc4_apps_clk_src", 965 .parent_names = gcc_xo_gpll0, 966 .num_parents = 2, 967 .ops = &clk_rcg2_floor_ops, 968 }, 969}; 970 971static struct freq_tbl ftbl_tsif_ref_clk_src[] = { 972 F(105500, P_XO, 1, 1, 182), 973 { } 974}; 975 976static struct clk_rcg2 tsif_ref_clk_src = { 977 .cmd_rcgr = 0x0d90, 978 .mnd_width = 8, 979 .hid_width = 5, 980 .freq_tbl = ftbl_tsif_ref_clk_src, 981 .clkr.hw.init = &(struct clk_init_data) 982 { 983 .name = "tsif_ref_clk_src", 984 .parent_names = (const char *[]) { "xo" }, 985 .num_parents = 1, 986 .ops = &clk_rcg2_ops, 987 }, 988}; 989 990static struct freq_tbl ftbl_usb30_mock_utmi_clk_src[] = { 991 F(19200000, P_XO, 1, 0, 0), 992 F(60000000, P_GPLL0, 10, 0, 0), 993 { } 994}; 995 996static struct clk_rcg2 usb30_mock_utmi_clk_src = { 997 .cmd_rcgr = 0x03e8, 998 .hid_width = 5, 999 .parent_map = gcc_xo_gpll0_map, 1000 .freq_tbl = ftbl_usb30_mock_utmi_clk_src, 1001 .clkr.hw.init = &(struct clk_init_data) 1002 { 1003 .name = "usb30_mock_utmi_clk_src", 1004 .parent_names = gcc_xo_gpll0, 1005 .num_parents = 2, 1006 .ops = &clk_rcg2_ops, 1007 }, 1008}; 1009 1010static struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = { 1011 F(1200000, P_XO, 16, 0, 0), 1012 { } 1013}; 1014 1015static struct clk_rcg2 usb3_phy_aux_clk_src = { 1016 .cmd_rcgr = 0x1414, 1017 .hid_width = 5, 1018 .freq_tbl = ftbl_usb3_phy_aux_clk_src, 1019 .clkr.hw.init = &(struct clk_init_data) 1020 { 1021 .name = "usb3_phy_aux_clk_src", 1022 .parent_names = (const char *[]) { "xo" }, 1023 .num_parents = 1, 1024 .ops = &clk_rcg2_ops, 1025 }, 1026}; 1027 1028static struct freq_tbl ftbl_usb_hs_system_clk_src[] = { 1029 F(75000000, P_GPLL0, 8, 0, 0), 1030 { } 1031}; 1032 1033static struct clk_rcg2 usb_hs_system_clk_src = { 1034 .cmd_rcgr = 0x0490, 1035 .hid_width = 5, 1036 .parent_map = gcc_xo_gpll0_map, 1037 .freq_tbl = ftbl_usb_hs_system_clk_src, 1038 .clkr.hw.init = &(struct clk_init_data) 1039 { 1040 .name = "usb_hs_system_clk_src", 1041 .parent_names = gcc_xo_gpll0, 1042 .num_parents = 2, 1043 .ops = &clk_rcg2_ops, 1044 }, 1045}; 1046 1047static struct clk_branch gcc_blsp1_ahb_clk = { 1048 .halt_reg = 0x05c4, 1049 .halt_check = BRANCH_HALT_VOTED, 1050 .clkr = { 1051 .enable_reg = 0x1484, 1052 .enable_mask = BIT(17), 1053 .hw.init = &(struct clk_init_data) 1054 { 1055 .name = "gcc_blsp1_ahb_clk", 1056 .ops = &clk_branch2_ops, 1057 }, 1058 }, 1059}; 1060 1061static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = { 1062 .halt_reg = 0x0648, 1063 .clkr = { 1064 .enable_reg = 0x0648, 1065 .enable_mask = BIT(0), 1066 .hw.init = &(struct clk_init_data) 1067 { 1068 .name = "gcc_blsp1_qup1_i2c_apps_clk", 1069 .parent_names = (const char *[]) { 1070 "blsp1_qup1_i2c_apps_clk_src", 1071 }, 1072 .num_parents = 1, 1073 .flags = CLK_SET_RATE_PARENT, 1074 .ops = &clk_branch2_ops, 1075 }, 1076 }, 1077}; 1078 1079static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = { 1080 .halt_reg = 0x0644, 1081 .clkr = { 1082 .enable_reg = 0x0644, 1083 .enable_mask = BIT(0), 1084 .hw.init = &(struct clk_init_data) 1085 { 1086 .name = "gcc_blsp1_qup1_spi_apps_clk", 1087 .parent_names = (const char *[]) { 1088 "blsp1_qup1_spi_apps_clk_src", 1089 }, 1090 .num_parents = 1, 1091 .flags = CLK_SET_RATE_PARENT, 1092 .ops = &clk_branch2_ops, 1093 }, 1094 }, 1095}; 1096 1097static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = { 1098 .halt_reg = 0x06c8, 1099 .clkr = { 1100 .enable_reg = 0x06c8, 1101 .enable_mask = BIT(0), 1102 .hw.init = &(struct clk_init_data) 1103 { 1104 .name = "gcc_blsp1_qup2_i2c_apps_clk", 1105 .parent_names = (const char *[]) { 1106 "blsp1_qup2_i2c_apps_clk_src", 1107 }, 1108 .num_parents = 1, 1109 .flags = CLK_SET_RATE_PARENT, 1110 .ops = &clk_branch2_ops, 1111 }, 1112 }, 1113}; 1114 1115static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = { 1116 .halt_reg = 0x06c4, 1117 .clkr = { 1118 .enable_reg = 0x06c4, 1119 .enable_mask = BIT(0), 1120 .hw.init = &(struct clk_init_data) 1121 { 1122 .name = "gcc_blsp1_qup2_spi_apps_clk", 1123 .parent_names = (const char *[]) { 1124 "blsp1_qup2_spi_apps_clk_src", 1125 }, 1126 .num_parents = 1, 1127 .flags = CLK_SET_RATE_PARENT, 1128 .ops = &clk_branch2_ops, 1129 }, 1130 }, 1131}; 1132 1133static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = { 1134 .halt_reg = 0x0748, 1135 .clkr = { 1136 .enable_reg = 0x0748, 1137 .enable_mask = BIT(0), 1138 .hw.init = &(struct clk_init_data) 1139 { 1140 .name = "gcc_blsp1_qup3_i2c_apps_clk", 1141 .parent_names = (const char *[]) { 1142 "blsp1_qup3_i2c_apps_clk_src", 1143 }, 1144 .num_parents = 1, 1145 .flags = CLK_SET_RATE_PARENT, 1146 .ops = &clk_branch2_ops, 1147 }, 1148 }, 1149}; 1150 1151static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = { 1152 .halt_reg = 0x0744, 1153 .clkr = { 1154 .enable_reg = 0x0744, 1155 .enable_mask = BIT(0), 1156 .hw.init = &(struct clk_init_data) 1157 { 1158 .name = "gcc_blsp1_qup3_spi_apps_clk", 1159 .parent_names = (const char *[]) { 1160 "blsp1_qup3_spi_apps_clk_src", 1161 }, 1162 .num_parents = 1, 1163 .flags = CLK_SET_RATE_PARENT, 1164 .ops = &clk_branch2_ops, 1165 }, 1166 }, 1167}; 1168 1169static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = { 1170 .halt_reg = 0x07c8, 1171 .clkr = { 1172 .enable_reg = 0x07c8, 1173 .enable_mask = BIT(0), 1174 .hw.init = &(struct clk_init_data) 1175 { 1176 .name = "gcc_blsp1_qup4_i2c_apps_clk", 1177 .parent_names = (const char *[]) { 1178 "blsp1_qup4_i2c_apps_clk_src", 1179 }, 1180 .num_parents = 1, 1181 .flags = CLK_SET_RATE_PARENT, 1182 .ops = &clk_branch2_ops, 1183 }, 1184 }, 1185}; 1186 1187static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = { 1188 .halt_reg = 0x07c4, 1189 .clkr = { 1190 .enable_reg = 0x07c4, 1191 .enable_mask = BIT(0), 1192 .hw.init = &(struct clk_init_data) 1193 { 1194 .name = "gcc_blsp1_qup4_spi_apps_clk", 1195 .parent_names = (const char *[]) { 1196 "blsp1_qup4_spi_apps_clk_src", 1197 }, 1198 .num_parents = 1, 1199 .flags = CLK_SET_RATE_PARENT, 1200 .ops = &clk_branch2_ops, 1201 }, 1202 }, 1203}; 1204 1205static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = { 1206 .halt_reg = 0x0848, 1207 .clkr = { 1208 .enable_reg = 0x0848, 1209 .enable_mask = BIT(0), 1210 .hw.init = &(struct clk_init_data) 1211 { 1212 .name = "gcc_blsp1_qup5_i2c_apps_clk", 1213 .parent_names = (const char *[]) { 1214 "blsp1_qup5_i2c_apps_clk_src", 1215 }, 1216 .num_parents = 1, 1217 .flags = CLK_SET_RATE_PARENT, 1218 .ops = &clk_branch2_ops, 1219 }, 1220 }, 1221}; 1222 1223static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = { 1224 .halt_reg = 0x0844, 1225 .clkr = { 1226 .enable_reg = 0x0844, 1227 .enable_mask = BIT(0), 1228 .hw.init = &(struct clk_init_data) 1229 { 1230 .name = "gcc_blsp1_qup5_spi_apps_clk", 1231 .parent_names = (const char *[]) { 1232 "blsp1_qup5_spi_apps_clk_src", 1233 }, 1234 .num_parents = 1, 1235 .flags = CLK_SET_RATE_PARENT, 1236 .ops = &clk_branch2_ops, 1237 }, 1238 }, 1239}; 1240 1241static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = { 1242 .halt_reg = 0x08c8, 1243 .clkr = { 1244 .enable_reg = 0x08c8, 1245 .enable_mask = BIT(0), 1246 .hw.init = &(struct clk_init_data) 1247 { 1248 .name = "gcc_blsp1_qup6_i2c_apps_clk", 1249 .parent_names = (const char *[]) { 1250 "blsp1_qup6_i2c_apps_clk_src", 1251 }, 1252 .num_parents = 1, 1253 .flags = CLK_SET_RATE_PARENT, 1254 .ops = &clk_branch2_ops, 1255 }, 1256 }, 1257}; 1258 1259static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = { 1260 .halt_reg = 0x08c4, 1261 .clkr = { 1262 .enable_reg = 0x08c4, 1263 .enable_mask = BIT(0), 1264 .hw.init = &(struct clk_init_data) 1265 { 1266 .name = "gcc_blsp1_qup6_spi_apps_clk", 1267 .parent_names = (const char *[]) { 1268 "blsp1_qup6_spi_apps_clk_src", 1269 }, 1270 .num_parents = 1, 1271 .flags = CLK_SET_RATE_PARENT, 1272 .ops = &clk_branch2_ops, 1273 }, 1274 }, 1275}; 1276 1277static struct clk_branch gcc_blsp1_uart1_apps_clk = { 1278 .halt_reg = 0x0684, 1279 .clkr = { 1280 .enable_reg = 0x0684, 1281 .enable_mask = BIT(0), 1282 .hw.init = &(struct clk_init_data) 1283 { 1284 .name = "gcc_blsp1_uart1_apps_clk", 1285 .parent_names = (const char *[]) { 1286 "blsp1_uart1_apps_clk_src", 1287 }, 1288 .num_parents = 1, 1289 .flags = CLK_SET_RATE_PARENT, 1290 .ops = &clk_branch2_ops, 1291 }, 1292 }, 1293}; 1294 1295static struct clk_branch gcc_blsp1_uart2_apps_clk = { 1296 .halt_reg = 0x0704, 1297 .clkr = { 1298 .enable_reg = 0x0704, 1299 .enable_mask = BIT(0), 1300 .hw.init = &(struct clk_init_data) 1301 { 1302 .name = "gcc_blsp1_uart2_apps_clk", 1303 .parent_names = (const char *[]) { 1304 "blsp1_uart2_apps_clk_src", 1305 }, 1306 .num_parents = 1, 1307 .flags = CLK_SET_RATE_PARENT, 1308 .ops = &clk_branch2_ops, 1309 }, 1310 }, 1311}; 1312 1313static struct clk_branch gcc_blsp1_uart3_apps_clk = { 1314 .halt_reg = 0x0784, 1315 .clkr = { 1316 .enable_reg = 0x0784, 1317 .enable_mask = BIT(0), 1318 .hw.init = &(struct clk_init_data) 1319 { 1320 .name = "gcc_blsp1_uart3_apps_clk", 1321 .parent_names = (const char *[]) { 1322 "blsp1_uart3_apps_clk_src", 1323 }, 1324 .num_parents = 1, 1325 .flags = CLK_SET_RATE_PARENT, 1326 .ops = &clk_branch2_ops, 1327 }, 1328 }, 1329}; 1330 1331static struct clk_branch gcc_blsp1_uart4_apps_clk = { 1332 .halt_reg = 0x0804, 1333 .clkr = { 1334 .enable_reg = 0x0804, 1335 .enable_mask = BIT(0), 1336 .hw.init = &(struct clk_init_data) 1337 { 1338 .name = "gcc_blsp1_uart4_apps_clk", 1339 .parent_names = (const char *[]) { 1340 "blsp1_uart4_apps_clk_src", 1341 }, 1342 .num_parents = 1, 1343 .flags = CLK_SET_RATE_PARENT, 1344 .ops = &clk_branch2_ops, 1345 }, 1346 }, 1347}; 1348 1349static struct clk_branch gcc_blsp1_uart5_apps_clk = { 1350 .halt_reg = 0x0884, 1351 .clkr = { 1352 .enable_reg = 0x0884, 1353 .enable_mask = BIT(0), 1354 .hw.init = &(struct clk_init_data) 1355 { 1356 .name = "gcc_blsp1_uart5_apps_clk", 1357 .parent_names = (const char *[]) { 1358 "blsp1_uart5_apps_clk_src", 1359 }, 1360 .num_parents = 1, 1361 .flags = CLK_SET_RATE_PARENT, 1362 .ops = &clk_branch2_ops, 1363 }, 1364 }, 1365}; 1366 1367static struct clk_branch gcc_blsp1_uart6_apps_clk = { 1368 .halt_reg = 0x0904, 1369 .clkr = { 1370 .enable_reg = 0x0904, 1371 .enable_mask = BIT(0), 1372 .hw.init = &(struct clk_init_data) 1373 { 1374 .name = "gcc_blsp1_uart6_apps_clk", 1375 .parent_names = (const char *[]) { 1376 "blsp1_uart6_apps_clk_src", 1377 }, 1378 .num_parents = 1, 1379 .flags = CLK_SET_RATE_PARENT, 1380 .ops = &clk_branch2_ops, 1381 }, 1382 }, 1383}; 1384 1385static struct clk_branch gcc_blsp2_ahb_clk = { 1386 .halt_reg = 0x0944, 1387 .halt_check = BRANCH_HALT_VOTED, 1388 .clkr = { 1389 .enable_reg = 0x1484, 1390 .enable_mask = BIT(15), 1391 .hw.init = &(struct clk_init_data) 1392 { 1393 .name = "gcc_blsp2_ahb_clk", 1394 .ops = &clk_branch2_ops, 1395 }, 1396 }, 1397}; 1398 1399static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = { 1400 .halt_reg = 0x0988, 1401 .clkr = { 1402 .enable_reg = 0x0988, 1403 .enable_mask = BIT(0), 1404 .hw.init = &(struct clk_init_data) 1405 { 1406 .name = "gcc_blsp2_qup1_i2c_apps_clk", 1407 .parent_names = (const char *[]) { 1408 "blsp2_qup1_i2c_apps_clk_src", 1409 }, 1410 .num_parents = 1, 1411 .flags = CLK_SET_RATE_PARENT, 1412 .ops = &clk_branch2_ops, 1413 }, 1414 }, 1415}; 1416 1417static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = { 1418 .halt_reg = 0x0984, 1419 .clkr = { 1420 .enable_reg = 0x0984, 1421 .enable_mask = BIT(0), 1422 .hw.init = &(struct clk_init_data) 1423 { 1424 .name = "gcc_blsp2_qup1_spi_apps_clk", 1425 .parent_names = (const char *[]) { 1426 "blsp2_qup1_spi_apps_clk_src", 1427 }, 1428 .num_parents = 1, 1429 .flags = CLK_SET_RATE_PARENT, 1430 .ops = &clk_branch2_ops, 1431 }, 1432 }, 1433}; 1434 1435static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = { 1436 .halt_reg = 0x0a08, 1437 .clkr = { 1438 .enable_reg = 0x0a08, 1439 .enable_mask = BIT(0), 1440 .hw.init = &(struct clk_init_data) 1441 { 1442 .name = "gcc_blsp2_qup2_i2c_apps_clk", 1443 .parent_names = (const char *[]) { 1444 "blsp2_qup2_i2c_apps_clk_src", 1445 }, 1446 .num_parents = 1, 1447 .flags = CLK_SET_RATE_PARENT, 1448 .ops = &clk_branch2_ops, 1449 }, 1450 }, 1451}; 1452 1453static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = { 1454 .halt_reg = 0x0a04, 1455 .clkr = { 1456 .enable_reg = 0x0a04, 1457 .enable_mask = BIT(0), 1458 .hw.init = &(struct clk_init_data) 1459 { 1460 .name = "gcc_blsp2_qup2_spi_apps_clk", 1461 .parent_names = (const char *[]) { 1462 "blsp2_qup2_spi_apps_clk_src", 1463 }, 1464 .num_parents = 1, 1465 .flags = CLK_SET_RATE_PARENT, 1466 .ops = &clk_branch2_ops, 1467 }, 1468 }, 1469}; 1470 1471static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = { 1472 .halt_reg = 0x0a88, 1473 .clkr = { 1474 .enable_reg = 0x0a88, 1475 .enable_mask = BIT(0), 1476 .hw.init = &(struct clk_init_data) 1477 { 1478 .name = "gcc_blsp2_qup3_i2c_apps_clk", 1479 .parent_names = (const char *[]) { 1480 "blsp2_qup3_i2c_apps_clk_src", 1481 }, 1482 .num_parents = 1, 1483 .flags = CLK_SET_RATE_PARENT, 1484 .ops = &clk_branch2_ops, 1485 }, 1486 }, 1487}; 1488 1489static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = { 1490 .halt_reg = 0x0a84, 1491 .clkr = { 1492 .enable_reg = 0x0a84, 1493 .enable_mask = BIT(0), 1494 .hw.init = &(struct clk_init_data) 1495 { 1496 .name = "gcc_blsp2_qup3_spi_apps_clk", 1497 .parent_names = (const char *[]) { 1498 "blsp2_qup3_spi_apps_clk_src", 1499 }, 1500 .num_parents = 1, 1501 .flags = CLK_SET_RATE_PARENT, 1502 .ops = &clk_branch2_ops, 1503 }, 1504 }, 1505}; 1506 1507static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = { 1508 .halt_reg = 0x0b08, 1509 .clkr = { 1510 .enable_reg = 0x0b08, 1511 .enable_mask = BIT(0), 1512 .hw.init = &(struct clk_init_data) 1513 { 1514 .name = "gcc_blsp2_qup4_i2c_apps_clk", 1515 .parent_names = (const char *[]) { 1516 "blsp2_qup4_i2c_apps_clk_src", 1517 }, 1518 .num_parents = 1, 1519 .flags = CLK_SET_RATE_PARENT, 1520 .ops = &clk_branch2_ops, 1521 }, 1522 }, 1523}; 1524 1525static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = { 1526 .halt_reg = 0x0b04, 1527 .clkr = { 1528 .enable_reg = 0x0b04, 1529 .enable_mask = BIT(0), 1530 .hw.init = &(struct clk_init_data) 1531 { 1532 .name = "gcc_blsp2_qup4_spi_apps_clk", 1533 .parent_names = (const char *[]) { 1534 "blsp2_qup4_spi_apps_clk_src", 1535 }, 1536 .num_parents = 1, 1537 .flags = CLK_SET_RATE_PARENT, 1538 .ops = &clk_branch2_ops, 1539 }, 1540 }, 1541}; 1542 1543static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = { 1544 .halt_reg = 0x0b88, 1545 .clkr = { 1546 .enable_reg = 0x0b88, 1547 .enable_mask = BIT(0), 1548 .hw.init = &(struct clk_init_data) 1549 { 1550 .name = "gcc_blsp2_qup5_i2c_apps_clk", 1551 .parent_names = (const char *[]) { 1552 "blsp2_qup5_i2c_apps_clk_src", 1553 }, 1554 .num_parents = 1, 1555 .flags = CLK_SET_RATE_PARENT, 1556 .ops = &clk_branch2_ops, 1557 }, 1558 }, 1559}; 1560 1561static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = { 1562 .halt_reg = 0x0b84, 1563 .clkr = { 1564 .enable_reg = 0x0b84, 1565 .enable_mask = BIT(0), 1566 .hw.init = &(struct clk_init_data) 1567 { 1568 .name = "gcc_blsp2_qup5_spi_apps_clk", 1569 .parent_names = (const char *[]) { 1570 "blsp2_qup5_spi_apps_clk_src", 1571 }, 1572 .num_parents = 1, 1573 .flags = CLK_SET_RATE_PARENT, 1574 .ops = &clk_branch2_ops, 1575 }, 1576 }, 1577}; 1578 1579static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = { 1580 .halt_reg = 0x0c08, 1581 .clkr = { 1582 .enable_reg = 0x0c08, 1583 .enable_mask = BIT(0), 1584 .hw.init = &(struct clk_init_data) 1585 { 1586 .name = "gcc_blsp2_qup6_i2c_apps_clk", 1587 .parent_names = (const char *[]) { 1588 "blsp2_qup6_i2c_apps_clk_src", 1589 }, 1590 .num_parents = 1, 1591 .flags = CLK_SET_RATE_PARENT, 1592 .ops = &clk_branch2_ops, 1593 }, 1594 }, 1595}; 1596 1597static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = { 1598 .halt_reg = 0x0c04, 1599 .clkr = { 1600 .enable_reg = 0x0c04, 1601 .enable_mask = BIT(0), 1602 .hw.init = &(struct clk_init_data) 1603 { 1604 .name = "gcc_blsp2_qup6_spi_apps_clk", 1605 .parent_names = (const char *[]) { 1606 "blsp2_qup6_spi_apps_clk_src", 1607 }, 1608 .num_parents = 1, 1609 .flags = CLK_SET_RATE_PARENT, 1610 .ops = &clk_branch2_ops, 1611 }, 1612 }, 1613}; 1614 1615static struct clk_branch gcc_blsp2_uart1_apps_clk = { 1616 .halt_reg = 0x09c4, 1617 .clkr = { 1618 .enable_reg = 0x09c4, 1619 .enable_mask = BIT(0), 1620 .hw.init = &(struct clk_init_data) 1621 { 1622 .name = "gcc_blsp2_uart1_apps_clk", 1623 .parent_names = (const char *[]) { 1624 "blsp2_uart1_apps_clk_src", 1625 }, 1626 .num_parents = 1, 1627 .flags = CLK_SET_RATE_PARENT, 1628 .ops = &clk_branch2_ops, 1629 }, 1630 }, 1631}; 1632 1633static struct clk_branch gcc_blsp2_uart2_apps_clk = { 1634 .halt_reg = 0x0a44, 1635 .clkr = { 1636 .enable_reg = 0x0a44, 1637 .enable_mask = BIT(0), 1638 .hw.init = &(struct clk_init_data) 1639 { 1640 .name = "gcc_blsp2_uart2_apps_clk", 1641 .parent_names = (const char *[]) { 1642 "blsp2_uart2_apps_clk_src", 1643 }, 1644 .num_parents = 1, 1645 .flags = CLK_SET_RATE_PARENT, 1646 .ops = &clk_branch2_ops, 1647 }, 1648 }, 1649}; 1650 1651static struct clk_branch gcc_blsp2_uart3_apps_clk = { 1652 .halt_reg = 0x0ac4, 1653 .clkr = { 1654 .enable_reg = 0x0ac4, 1655 .enable_mask = BIT(0), 1656 .hw.init = &(struct clk_init_data) 1657 { 1658 .name = "gcc_blsp2_uart3_apps_clk", 1659 .parent_names = (const char *[]) { 1660 "blsp2_uart3_apps_clk_src", 1661 }, 1662 .num_parents = 1, 1663 .flags = CLK_SET_RATE_PARENT, 1664 .ops = &clk_branch2_ops, 1665 }, 1666 }, 1667}; 1668 1669static struct clk_branch gcc_blsp2_uart4_apps_clk = { 1670 .halt_reg = 0x0b44, 1671 .clkr = { 1672 .enable_reg = 0x0b44, 1673 .enable_mask = BIT(0), 1674 .hw.init = &(struct clk_init_data) 1675 { 1676 .name = "gcc_blsp2_uart4_apps_clk", 1677 .parent_names = (const char *[]) { 1678 "blsp2_uart4_apps_clk_src", 1679 }, 1680 .num_parents = 1, 1681 .flags = CLK_SET_RATE_PARENT, 1682 .ops = &clk_branch2_ops, 1683 }, 1684 }, 1685}; 1686 1687static struct clk_branch gcc_blsp2_uart5_apps_clk = { 1688 .halt_reg = 0x0bc4, 1689 .clkr = { 1690 .enable_reg = 0x0bc4, 1691 .enable_mask = BIT(0), 1692 .hw.init = &(struct clk_init_data) 1693 { 1694 .name = "gcc_blsp2_uart5_apps_clk", 1695 .parent_names = (const char *[]) { 1696 "blsp2_uart5_apps_clk_src", 1697 }, 1698 .num_parents = 1, 1699 .flags = CLK_SET_RATE_PARENT, 1700 .ops = &clk_branch2_ops, 1701 }, 1702 }, 1703}; 1704 1705static struct clk_branch gcc_blsp2_uart6_apps_clk = { 1706 .halt_reg = 0x0c44, 1707 .clkr = { 1708 .enable_reg = 0x0c44, 1709 .enable_mask = BIT(0), 1710 .hw.init = &(struct clk_init_data) 1711 { 1712 .name = "gcc_blsp2_uart6_apps_clk", 1713 .parent_names = (const char *[]) { 1714 "blsp2_uart6_apps_clk_src", 1715 }, 1716 .num_parents = 1, 1717 .flags = CLK_SET_RATE_PARENT, 1718 .ops = &clk_branch2_ops, 1719 }, 1720 }, 1721}; 1722 1723static struct clk_branch gcc_gp1_clk = { 1724 .halt_reg = 0x1900, 1725 .clkr = { 1726 .enable_reg = 0x1900, 1727 .enable_mask = BIT(0), 1728 .hw.init = &(struct clk_init_data) 1729 { 1730 .name = "gcc_gp1_clk", 1731 .parent_names = (const char *[]) { 1732 "gp1_clk_src", 1733 }, 1734 .num_parents = 1, 1735 .flags = CLK_SET_RATE_PARENT, 1736 .ops = &clk_branch2_ops, 1737 }, 1738 }, 1739}; 1740 1741static struct clk_branch gcc_gp2_clk = { 1742 .halt_reg = 0x1940, 1743 .clkr = { 1744 .enable_reg = 0x1940, 1745 .enable_mask = BIT(0), 1746 .hw.init = &(struct clk_init_data) 1747 { 1748 .name = "gcc_gp2_clk", 1749 .parent_names = (const char *[]) { 1750 "gp2_clk_src", 1751 }, 1752 .num_parents = 1, 1753 .flags = CLK_SET_RATE_PARENT, 1754 .ops = &clk_branch2_ops, 1755 }, 1756 }, 1757}; 1758 1759static struct clk_branch gcc_gp3_clk = { 1760 .halt_reg = 0x1980, 1761 .clkr = { 1762 .enable_reg = 0x1980, 1763 .enable_mask = BIT(0), 1764 .hw.init = &(struct clk_init_data) 1765 { 1766 .name = "gcc_gp3_clk", 1767 .parent_names = (const char *[]) { 1768 "gp3_clk_src", 1769 }, 1770 .num_parents = 1, 1771 .flags = CLK_SET_RATE_PARENT, 1772 .ops = &clk_branch2_ops, 1773 }, 1774 }, 1775}; 1776 1777static struct clk_branch gcc_lpass_q6_axi_clk = { 1778 .halt_reg = 0x0280, 1779 .clkr = { 1780 .enable_reg = 0x0280, 1781 .enable_mask = BIT(0), 1782 .hw.init = &(struct clk_init_data) 1783 { 1784 .name = "gcc_lpass_q6_axi_clk", 1785 .ops = &clk_branch2_ops, 1786 }, 1787 }, 1788}; 1789 1790static struct clk_branch gcc_mss_q6_bimc_axi_clk = { 1791 .halt_reg = 0x0284, 1792 .clkr = { 1793 .enable_reg = 0x0284, 1794 .enable_mask = BIT(0), 1795 .hw.init = &(struct clk_init_data) 1796 { 1797 .name = "gcc_mss_q6_bimc_axi_clk", 1798 .ops = &clk_branch2_ops, 1799 }, 1800 }, 1801}; 1802 1803static struct clk_branch gcc_pcie_0_aux_clk = { 1804 .halt_reg = 0x1ad4, 1805 .clkr = { 1806 .enable_reg = 0x1ad4, 1807 .enable_mask = BIT(0), 1808 .hw.init = &(struct clk_init_data) 1809 { 1810 .name = "gcc_pcie_0_aux_clk", 1811 .parent_names = (const char *[]) { 1812 "pcie_0_aux_clk_src", 1813 }, 1814 .num_parents = 1, 1815 .flags = CLK_SET_RATE_PARENT, 1816 .ops = &clk_branch2_ops, 1817 }, 1818 }, 1819}; 1820 1821static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { 1822 .halt_reg = 0x1ad0, 1823 .clkr = { 1824 .enable_reg = 0x1ad0, 1825 .enable_mask = BIT(0), 1826 .hw.init = &(struct clk_init_data) 1827 { 1828 .name = "gcc_pcie_0_cfg_ahb_clk", 1829 .ops = &clk_branch2_ops, 1830 }, 1831 }, 1832}; 1833 1834static struct clk_branch gcc_pcie_0_mstr_axi_clk = { 1835 .halt_reg = 0x1acc, 1836 .clkr = { 1837 .enable_reg = 0x1acc, 1838 .enable_mask = BIT(0), 1839 .hw.init = &(struct clk_init_data) 1840 { 1841 .name = "gcc_pcie_0_mstr_axi_clk", 1842 .ops = &clk_branch2_ops, 1843 }, 1844 }, 1845}; 1846 1847static struct clk_branch gcc_pcie_0_pipe_clk = { 1848 .halt_reg = 0x1ad8, 1849 .halt_check = BRANCH_HALT_DELAY, 1850 .clkr = { 1851 .enable_reg = 0x1ad8, 1852 .enable_mask = BIT(0), 1853 .hw.init = &(struct clk_init_data) 1854 { 1855 .name = "gcc_pcie_0_pipe_clk", 1856 .parent_names = (const char *[]) { 1857 "pcie_0_pipe_clk_src", 1858 }, 1859 .num_parents = 1, 1860 .flags = CLK_SET_RATE_PARENT, 1861 .ops = &clk_branch2_ops, 1862 }, 1863 }, 1864}; 1865 1866static struct clk_branch gcc_pcie_0_slv_axi_clk = { 1867 .halt_reg = 0x1ac8, 1868 .halt_check = BRANCH_HALT_DELAY, 1869 .clkr = { 1870 .enable_reg = 0x1ac8, 1871 .enable_mask = BIT(0), 1872 .hw.init = &(struct clk_init_data) 1873 { 1874 .name = "gcc_pcie_0_slv_axi_clk", 1875 .ops = &clk_branch2_ops, 1876 }, 1877 }, 1878}; 1879 1880static struct clk_branch gcc_pcie_1_aux_clk = { 1881 .halt_reg = 0x1b54, 1882 .clkr = { 1883 .enable_reg = 0x1b54, 1884 .enable_mask = BIT(0), 1885 .hw.init = &(struct clk_init_data) 1886 { 1887 .name = "gcc_pcie_1_aux_clk", 1888 .parent_names = (const char *[]) { 1889 "pcie_1_aux_clk_src", 1890 }, 1891 .num_parents = 1, 1892 .flags = CLK_SET_RATE_PARENT, 1893 .ops = &clk_branch2_ops, 1894 }, 1895 }, 1896}; 1897 1898static struct clk_branch gcc_pcie_1_cfg_ahb_clk = { 1899 .halt_reg = 0x1b54, 1900 .clkr = { 1901 .enable_reg = 0x1b54, 1902 .enable_mask = BIT(0), 1903 .hw.init = &(struct clk_init_data) 1904 { 1905 .name = "gcc_pcie_1_cfg_ahb_clk", 1906 .ops = &clk_branch2_ops, 1907 }, 1908 }, 1909}; 1910 1911static struct clk_branch gcc_pcie_1_mstr_axi_clk = { 1912 .halt_reg = 0x1b50, 1913 .clkr = { 1914 .enable_reg = 0x1b50, 1915 .enable_mask = BIT(0), 1916 .hw.init = &(struct clk_init_data) 1917 { 1918 .name = "gcc_pcie_1_mstr_axi_clk", 1919 .ops = &clk_branch2_ops, 1920 }, 1921 }, 1922}; 1923 1924static struct clk_branch gcc_pcie_1_pipe_clk = { 1925 .halt_reg = 0x1b58, 1926 .halt_check = BRANCH_HALT_DELAY, 1927 .clkr = { 1928 .enable_reg = 0x1b58, 1929 .enable_mask = BIT(0), 1930 .hw.init = &(struct clk_init_data) 1931 { 1932 .name = "gcc_pcie_1_pipe_clk", 1933 .parent_names = (const char *[]) { 1934 "pcie_1_pipe_clk_src", 1935 }, 1936 .num_parents = 1, 1937 .flags = CLK_SET_RATE_PARENT, 1938 .ops = &clk_branch2_ops, 1939 }, 1940 }, 1941}; 1942 1943static struct clk_branch gcc_pcie_1_slv_axi_clk = { 1944 .halt_reg = 0x1b48, 1945 .clkr = { 1946 .enable_reg = 0x1b48, 1947 .enable_mask = BIT(0), 1948 .hw.init = &(struct clk_init_data) 1949 { 1950 .name = "gcc_pcie_1_slv_axi_clk", 1951 .ops = &clk_branch2_ops, 1952 }, 1953 }, 1954}; 1955 1956static struct clk_branch gcc_pdm2_clk = { 1957 .halt_reg = 0x0ccc, 1958 .clkr = { 1959 .enable_reg = 0x0ccc, 1960 .enable_mask = BIT(0), 1961 .hw.init = &(struct clk_init_data) 1962 { 1963 .name = "gcc_pdm2_clk", 1964 .parent_names = (const char *[]) { 1965 "pdm2_clk_src", 1966 }, 1967 .num_parents = 1, 1968 .flags = CLK_SET_RATE_PARENT, 1969 .ops = &clk_branch2_ops, 1970 }, 1971 }, 1972}; 1973 1974static struct clk_branch gcc_pdm_ahb_clk = { 1975 .halt_reg = 0x0cc4, 1976 .clkr = { 1977 .enable_reg = 0x0cc4, 1978 .enable_mask = BIT(0), 1979 .hw.init = &(struct clk_init_data) 1980 { 1981 .name = "gcc_pdm_ahb_clk", 1982 .ops = &clk_branch2_ops, 1983 }, 1984 }, 1985}; 1986 1987static struct clk_branch gcc_sdcc1_apps_clk = { 1988 .halt_reg = 0x04c4, 1989 .clkr = { 1990 .enable_reg = 0x04c4, 1991 .enable_mask = BIT(0), 1992 .hw.init = &(struct clk_init_data) 1993 { 1994 .name = "gcc_sdcc1_apps_clk", 1995 .parent_names = (const char *[]) { 1996 "sdcc1_apps_clk_src", 1997 }, 1998 .num_parents = 1, 1999 .flags = CLK_SET_RATE_PARENT, 2000 .ops = &clk_branch2_ops, 2001 }, 2002 }, 2003}; 2004 2005static struct clk_branch gcc_sdcc1_ahb_clk = { 2006 .halt_reg = 0x04c8, 2007 .clkr = { 2008 .enable_reg = 0x04c8, 2009 .enable_mask = BIT(0), 2010 .hw.init = &(struct clk_init_data) 2011 { 2012 .name = "gcc_sdcc1_ahb_clk", 2013 .parent_names = (const char *[]){ 2014 "periph_noc_clk_src", 2015 }, 2016 .num_parents = 1, 2017 .ops = &clk_branch2_ops, 2018 }, 2019 }, 2020}; 2021 2022static struct clk_branch gcc_sdcc2_ahb_clk = { 2023 .halt_reg = 0x0508, 2024 .clkr = { 2025 .enable_reg = 0x0508, 2026 .enable_mask = BIT(0), 2027 .hw.init = &(struct clk_init_data) 2028 { 2029 .name = "gcc_sdcc2_ahb_clk", 2030 .parent_names = (const char *[]){ 2031 "periph_noc_clk_src", 2032 }, 2033 .num_parents = 1, 2034 .ops = &clk_branch2_ops, 2035 }, 2036 }, 2037}; 2038 2039static struct clk_branch gcc_sdcc2_apps_clk = { 2040 .halt_reg = 0x0504, 2041 .clkr = { 2042 .enable_reg = 0x0504, 2043 .enable_mask = BIT(0), 2044 .hw.init = &(struct clk_init_data) 2045 { 2046 .name = "gcc_sdcc2_apps_clk", 2047 .parent_names = (const char *[]) { 2048 "sdcc2_apps_clk_src", 2049 }, 2050 .num_parents = 1, 2051 .flags = CLK_SET_RATE_PARENT, 2052 .ops = &clk_branch2_ops, 2053 }, 2054 }, 2055}; 2056 2057static struct clk_branch gcc_sdcc3_ahb_clk = { 2058 .halt_reg = 0x0548, 2059 .clkr = { 2060 .enable_reg = 0x0548, 2061 .enable_mask = BIT(0), 2062 .hw.init = &(struct clk_init_data) 2063 { 2064 .name = "gcc_sdcc3_ahb_clk", 2065 .parent_names = (const char *[]){ 2066 "periph_noc_clk_src", 2067 }, 2068 .num_parents = 1, 2069 .ops = &clk_branch2_ops, 2070 }, 2071 }, 2072}; 2073 2074static struct clk_branch gcc_sdcc3_apps_clk = { 2075 .halt_reg = 0x0544, 2076 .clkr = { 2077 .enable_reg = 0x0544, 2078 .enable_mask = BIT(0), 2079 .hw.init = &(struct clk_init_data) 2080 { 2081 .name = "gcc_sdcc3_apps_clk", 2082 .parent_names = (const char *[]) { 2083 "sdcc3_apps_clk_src", 2084 }, 2085 .num_parents = 1, 2086 .flags = CLK_SET_RATE_PARENT, 2087 .ops = &clk_branch2_ops, 2088 }, 2089 }, 2090}; 2091 2092static struct clk_branch gcc_sdcc4_ahb_clk = { 2093 .halt_reg = 0x0588, 2094 .clkr = { 2095 .enable_reg = 0x0588, 2096 .enable_mask = BIT(0), 2097 .hw.init = &(struct clk_init_data) 2098 { 2099 .name = "gcc_sdcc4_ahb_clk", 2100 .parent_names = (const char *[]){ 2101 "periph_noc_clk_src", 2102 }, 2103 .num_parents = 1, 2104 .ops = &clk_branch2_ops, 2105 }, 2106 }, 2107}; 2108 2109static struct clk_branch gcc_sdcc4_apps_clk = { 2110 .halt_reg = 0x0584, 2111 .clkr = { 2112 .enable_reg = 0x0584, 2113 .enable_mask = BIT(0), 2114 .hw.init = &(struct clk_init_data) 2115 { 2116 .name = "gcc_sdcc4_apps_clk", 2117 .parent_names = (const char *[]) { 2118 "sdcc4_apps_clk_src", 2119 }, 2120 .num_parents = 1, 2121 .flags = CLK_SET_RATE_PARENT, 2122 .ops = &clk_branch2_ops, 2123 }, 2124 }, 2125}; 2126 2127static struct clk_branch gcc_sys_noc_ufs_axi_clk = { 2128 .halt_reg = 0x1d7c, 2129 .clkr = { 2130 .enable_reg = 0x1d7c, 2131 .enable_mask = BIT(0), 2132 .hw.init = &(struct clk_init_data) 2133 { 2134 .name = "gcc_sys_noc_ufs_axi_clk", 2135 .parent_names = (const char *[]) { 2136 "ufs_axi_clk_src", 2137 }, 2138 .num_parents = 1, 2139 .flags = CLK_SET_RATE_PARENT, 2140 .ops = &clk_branch2_ops, 2141 }, 2142 }, 2143}; 2144 2145static struct clk_branch gcc_sys_noc_usb3_axi_clk = { 2146 .halt_reg = 0x03fc, 2147 .clkr = { 2148 .enable_reg = 0x03fc, 2149 .enable_mask = BIT(0), 2150 .hw.init = &(struct clk_init_data) 2151 { 2152 .name = "gcc_sys_noc_usb3_axi_clk", 2153 .parent_names = (const char *[]) { 2154 "usb30_master_clk_src", 2155 }, 2156 .num_parents = 1, 2157 .flags = CLK_SET_RATE_PARENT, 2158 .ops = &clk_branch2_ops, 2159 }, 2160 }, 2161}; 2162 2163static struct clk_branch gcc_tsif_ahb_clk = { 2164 .halt_reg = 0x0d84, 2165 .clkr = { 2166 .enable_reg = 0x0d84, 2167 .enable_mask = BIT(0), 2168 .hw.init = &(struct clk_init_data) 2169 { 2170 .name = "gcc_tsif_ahb_clk", 2171 .ops = &clk_branch2_ops, 2172 }, 2173 }, 2174}; 2175 2176static struct clk_branch gcc_tsif_ref_clk = { 2177 .halt_reg = 0x0d88, 2178 .clkr = { 2179 .enable_reg = 0x0d88, 2180 .enable_mask = BIT(0), 2181 .hw.init = &(struct clk_init_data) 2182 { 2183 .name = "gcc_tsif_ref_clk", 2184 .parent_names = (const char *[]) { 2185 "tsif_ref_clk_src", 2186 }, 2187 .num_parents = 1, 2188 .flags = CLK_SET_RATE_PARENT, 2189 .ops = &clk_branch2_ops, 2190 }, 2191 }, 2192}; 2193 2194static struct clk_branch gcc_ufs_ahb_clk = { 2195 .halt_reg = 0x1d4c, 2196 .clkr = { 2197 .enable_reg = 0x1d4c, 2198 .enable_mask = BIT(0), 2199 .hw.init = &(struct clk_init_data) 2200 { 2201 .name = "gcc_ufs_ahb_clk", 2202 .ops = &clk_branch2_ops, 2203 }, 2204 }, 2205}; 2206 2207static struct clk_branch gcc_ufs_axi_clk = { 2208 .halt_reg = 0x1d48, 2209 .clkr = { 2210 .enable_reg = 0x1d48, 2211 .enable_mask = BIT(0), 2212 .hw.init = &(struct clk_init_data) 2213 { 2214 .name = "gcc_ufs_axi_clk", 2215 .parent_names = (const char *[]) { 2216 "ufs_axi_clk_src", 2217 }, 2218 .num_parents = 1, 2219 .flags = CLK_SET_RATE_PARENT, 2220 .ops = &clk_branch2_ops, 2221 }, 2222 }, 2223}; 2224 2225static struct clk_branch gcc_ufs_rx_cfg_clk = { 2226 .halt_reg = 0x1d54, 2227 .clkr = { 2228 .enable_reg = 0x1d54, 2229 .enable_mask = BIT(0), 2230 .hw.init = &(struct clk_init_data) 2231 { 2232 .name = "gcc_ufs_rx_cfg_clk", 2233 .parent_names = (const char *[]) { 2234 "ufs_axi_clk_src", 2235 }, 2236 .num_parents = 1, 2237 .flags = CLK_SET_RATE_PARENT, 2238 .ops = &clk_branch2_ops, 2239 }, 2240 }, 2241}; 2242 2243static struct clk_branch gcc_ufs_rx_symbol_0_clk = { 2244 .halt_reg = 0x1d60, 2245 .halt_check = BRANCH_HALT_DELAY, 2246 .clkr = { 2247 .enable_reg = 0x1d60, 2248 .enable_mask = BIT(0), 2249 .hw.init = &(struct clk_init_data) 2250 { 2251 .name = "gcc_ufs_rx_symbol_0_clk", 2252 .ops = &clk_branch2_ops, 2253 }, 2254 }, 2255}; 2256 2257static struct clk_branch gcc_ufs_rx_symbol_1_clk = { 2258 .halt_reg = 0x1d64, 2259 .halt_check = BRANCH_HALT_DELAY, 2260 .clkr = { 2261 .enable_reg = 0x1d64, 2262 .enable_mask = BIT(0), 2263 .hw.init = &(struct clk_init_data) 2264 { 2265 .name = "gcc_ufs_rx_symbol_1_clk", 2266 .ops = &clk_branch2_ops, 2267 }, 2268 }, 2269}; 2270 2271static struct clk_branch gcc_ufs_tx_cfg_clk = { 2272 .halt_reg = 0x1d50, 2273 .clkr = { 2274 .enable_reg = 0x1d50, 2275 .enable_mask = BIT(0), 2276 .hw.init = &(struct clk_init_data) 2277 { 2278 .name = "gcc_ufs_tx_cfg_clk", 2279 .parent_names = (const char *[]) { 2280 "ufs_axi_clk_src", 2281 }, 2282 .num_parents = 1, 2283 .flags = CLK_SET_RATE_PARENT, 2284 .ops = &clk_branch2_ops, 2285 }, 2286 }, 2287}; 2288 2289static struct clk_branch gcc_ufs_tx_symbol_0_clk = { 2290 .halt_reg = 0x1d58, 2291 .halt_check = BRANCH_HALT_DELAY, 2292 .clkr = { 2293 .enable_reg = 0x1d58, 2294 .enable_mask = BIT(0), 2295 .hw.init = &(struct clk_init_data) 2296 { 2297 .name = "gcc_ufs_tx_symbol_0_clk", 2298 .ops = &clk_branch2_ops, 2299 }, 2300 }, 2301}; 2302 2303static struct clk_branch gcc_ufs_tx_symbol_1_clk = { 2304 .halt_reg = 0x1d5c, 2305 .halt_check = BRANCH_HALT_DELAY, 2306 .clkr = { 2307 .enable_reg = 0x1d5c, 2308 .enable_mask = BIT(0), 2309 .hw.init = &(struct clk_init_data) 2310 { 2311 .name = "gcc_ufs_tx_symbol_1_clk", 2312 .ops = &clk_branch2_ops, 2313 }, 2314 }, 2315}; 2316 2317static struct clk_branch gcc_usb2_hs_phy_sleep_clk = { 2318 .halt_reg = 0x04ac, 2319 .clkr = { 2320 .enable_reg = 0x04ac, 2321 .enable_mask = BIT(0), 2322 .hw.init = &(struct clk_init_data) 2323 { 2324 .name = "gcc_usb2_hs_phy_sleep_clk", 2325 .ops = &clk_branch2_ops, 2326 }, 2327 }, 2328}; 2329 2330static struct clk_branch gcc_usb30_master_clk = { 2331 .halt_reg = 0x03c8, 2332 .clkr = { 2333 .enable_reg = 0x03c8, 2334 .enable_mask = BIT(0), 2335 .hw.init = &(struct clk_init_data) 2336 { 2337 .name = "gcc_usb30_master_clk", 2338 .parent_names = (const char *[]) { 2339 "usb30_master_clk_src", 2340 }, 2341 .num_parents = 1, 2342 .flags = CLK_SET_RATE_PARENT, 2343 .ops = &clk_branch2_ops, 2344 }, 2345 }, 2346}; 2347 2348static struct clk_branch gcc_usb30_mock_utmi_clk = { 2349 .halt_reg = 0x03d0, 2350 .clkr = { 2351 .enable_reg = 0x03d0, 2352 .enable_mask = BIT(0), 2353 .hw.init = &(struct clk_init_data) 2354 { 2355 .name = "gcc_usb30_mock_utmi_clk", 2356 .parent_names = (const char *[]) { 2357 "usb30_mock_utmi_clk_src", 2358 }, 2359 .num_parents = 1, 2360 .flags = CLK_SET_RATE_PARENT, 2361 .ops = &clk_branch2_ops, 2362 }, 2363 }, 2364}; 2365 2366static struct clk_branch gcc_usb30_sleep_clk = { 2367 .halt_reg = 0x03cc, 2368 .clkr = { 2369 .enable_reg = 0x03cc, 2370 .enable_mask = BIT(0), 2371 .hw.init = &(struct clk_init_data) 2372 { 2373 .name = "gcc_usb30_sleep_clk", 2374 .ops = &clk_branch2_ops, 2375 }, 2376 }, 2377}; 2378 2379static struct clk_branch gcc_usb3_phy_aux_clk = { 2380 .halt_reg = 0x1408, 2381 .clkr = { 2382 .enable_reg = 0x1408, 2383 .enable_mask = BIT(0), 2384 .hw.init = &(struct clk_init_data) 2385 { 2386 .name = "gcc_usb3_phy_aux_clk", 2387 .parent_names = (const char *[]) { 2388 "usb3_phy_aux_clk_src", 2389 }, 2390 .num_parents = 1, 2391 .flags = CLK_SET_RATE_PARENT, 2392 .ops = &clk_branch2_ops, 2393 }, 2394 }, 2395}; 2396 2397static struct clk_branch gcc_usb_hs_ahb_clk = { 2398 .halt_reg = 0x0488, 2399 .clkr = { 2400 .enable_reg = 0x0488, 2401 .enable_mask = BIT(0), 2402 .hw.init = &(struct clk_init_data) 2403 { 2404 .name = "gcc_usb_hs_ahb_clk", 2405 .ops = &clk_branch2_ops, 2406 }, 2407 }, 2408}; 2409 2410static struct clk_branch gcc_usb_hs_system_clk = { 2411 .halt_reg = 0x0484, 2412 .clkr = { 2413 .enable_reg = 0x0484, 2414 .enable_mask = BIT(0), 2415 .hw.init = &(struct clk_init_data) 2416 { 2417 .name = "gcc_usb_hs_system_clk", 2418 .parent_names = (const char *[]) { 2419 "usb_hs_system_clk_src", 2420 }, 2421 .num_parents = 1, 2422 .flags = CLK_SET_RATE_PARENT, 2423 .ops = &clk_branch2_ops, 2424 }, 2425 }, 2426}; 2427 2428static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = { 2429 .halt_reg = 0x1a84, 2430 .clkr = { 2431 .enable_reg = 0x1a84, 2432 .enable_mask = BIT(0), 2433 .hw.init = &(struct clk_init_data) 2434 { 2435 .name = "gcc_usb_phy_cfg_ahb2phy_clk", 2436 .ops = &clk_branch2_ops, 2437 }, 2438 }, 2439}; 2440 2441static struct gdsc pcie_gdsc = { 2442 .gdscr = 0x1e18, 2443 .pd = { 2444 .name = "pcie", 2445 }, 2446 .pwrsts = PWRSTS_OFF_ON, 2447}; 2448 2449static struct gdsc pcie_0_gdsc = { 2450 .gdscr = 0x1ac4, 2451 .pd = { 2452 .name = "pcie_0", 2453 }, 2454 .pwrsts = PWRSTS_OFF_ON, 2455}; 2456 2457static struct gdsc pcie_1_gdsc = { 2458 .gdscr = 0x1b44, 2459 .pd = { 2460 .name = "pcie_1", 2461 }, 2462 .pwrsts = PWRSTS_OFF_ON, 2463}; 2464 2465static struct gdsc usb30_gdsc = { 2466 .gdscr = 0x3c4, 2467 .pd = { 2468 .name = "usb30", 2469 }, 2470 .pwrsts = PWRSTS_OFF_ON, 2471}; 2472 2473static struct gdsc ufs_gdsc = { 2474 .gdscr = 0x1d44, 2475 .pd = { 2476 .name = "ufs", 2477 }, 2478 .pwrsts = PWRSTS_OFF_ON, 2479}; 2480 2481static struct clk_regmap *gcc_msm8994_clocks[] = { 2482 [GPLL0_EARLY] = &gpll0_early.clkr, 2483 [GPLL0] = &gpll0.clkr, 2484 [GPLL4_EARLY] = &gpll4_early.clkr, 2485 [GPLL4] = &gpll4.clkr, 2486 [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr, 2487 [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr, 2488 [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr, 2489 [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr, 2490 [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr, 2491 [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr, 2492 [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr, 2493 [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr, 2494 [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr, 2495 [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr, 2496 [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr, 2497 [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr, 2498 [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr, 2499 [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr, 2500 [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr, 2501 [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr, 2502 [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr, 2503 [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr, 2504 [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr, 2505 [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr, 2506 [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr, 2507 [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr, 2508 [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr, 2509 [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr, 2510 [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr, 2511 [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr, 2512 [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr, 2513 [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr, 2514 [BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr, 2515 [BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr, 2516 [BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr, 2517 [BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr, 2518 [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr, 2519 [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr, 2520 [BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr, 2521 [BLSP2_UART4_APPS_CLK_SRC] = &blsp2_uart4_apps_clk_src.clkr, 2522 [BLSP2_UART5_APPS_CLK_SRC] = &blsp2_uart5_apps_clk_src.clkr, 2523 [BLSP2_UART6_APPS_CLK_SRC] = &blsp2_uart6_apps_clk_src.clkr, 2524 [GP1_CLK_SRC] = &gp1_clk_src.clkr, 2525 [GP2_CLK_SRC] = &gp2_clk_src.clkr, 2526 [GP3_CLK_SRC] = &gp3_clk_src.clkr, 2527 [PCIE_0_AUX_CLK_SRC] = &pcie_0_aux_clk_src.clkr, 2528 [PCIE_0_PIPE_CLK_SRC] = &pcie_0_pipe_clk_src.clkr, 2529 [PCIE_1_AUX_CLK_SRC] = &pcie_1_aux_clk_src.clkr, 2530 [PCIE_1_PIPE_CLK_SRC] = &pcie_1_pipe_clk_src.clkr, 2531 [PDM2_CLK_SRC] = &pdm2_clk_src.clkr, 2532 [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr, 2533 [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr, 2534 [SDCC3_APPS_CLK_SRC] = &sdcc3_apps_clk_src.clkr, 2535 [SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr, 2536 [TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr, 2537 [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr, 2538 [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr, 2539 [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr, 2540 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr, 2541 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr, 2542 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr, 2543 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr, 2544 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr, 2545 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr, 2546 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr, 2547 [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr, 2548 [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr, 2549 [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr, 2550 [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr, 2551 [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr, 2552 [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr, 2553 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr, 2554 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr, 2555 [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr, 2556 [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr, 2557 [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr, 2558 [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr, 2559 [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr, 2560 [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr, 2561 [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr, 2562 [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr, 2563 [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr, 2564 [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr, 2565 [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr, 2566 [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr, 2567 [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr, 2568 [GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr, 2569 [GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr, 2570 [GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr, 2571 [GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr, 2572 [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr, 2573 [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr, 2574 [GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr, 2575 [GCC_BLSP2_UART4_APPS_CLK] = &gcc_blsp2_uart4_apps_clk.clkr, 2576 [GCC_BLSP2_UART5_APPS_CLK] = &gcc_blsp2_uart5_apps_clk.clkr, 2577 [GCC_BLSP2_UART6_APPS_CLK] = &gcc_blsp2_uart6_apps_clk.clkr, 2578 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 2579 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 2580 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 2581 [GCC_LPASS_Q6_AXI_CLK] = &gcc_lpass_q6_axi_clk.clkr, 2582 [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr, 2583 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr, 2584 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr, 2585 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr, 2586 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr, 2587 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr, 2588 [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr, 2589 [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr, 2590 [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr, 2591 [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr, 2592 [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr, 2593 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 2594 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 2595 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, 2596 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, 2597 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, 2598 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, 2599 [GCC_SDCC3_AHB_CLK] = &gcc_sdcc3_ahb_clk.clkr, 2600 [GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr, 2601 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr, 2602 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr, 2603 [GCC_SYS_NOC_UFS_AXI_CLK] = &gcc_sys_noc_ufs_axi_clk.clkr, 2604 [GCC_SYS_NOC_USB3_AXI_CLK] = &gcc_sys_noc_usb3_axi_clk.clkr, 2605 [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr, 2606 [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr, 2607 [GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr, 2608 [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr, 2609 [GCC_UFS_RX_CFG_CLK] = &gcc_ufs_rx_cfg_clk.clkr, 2610 [GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr, 2611 [GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr, 2612 [GCC_UFS_TX_CFG_CLK] = &gcc_ufs_tx_cfg_clk.clkr, 2613 [GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr, 2614 [GCC_UFS_TX_SYMBOL_1_CLK] = &gcc_ufs_tx_symbol_1_clk.clkr, 2615 [GCC_USB2_HS_PHY_SLEEP_CLK] = &gcc_usb2_hs_phy_sleep_clk.clkr, 2616 [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr, 2617 [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr, 2618 [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr, 2619 [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr, 2620 [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr, 2621 [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr, 2622 [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr, 2623}; 2624 2625static struct gdsc *gcc_msm8994_gdscs[] = { 2626 [PCIE_GDSC] = &pcie_gdsc, 2627 [PCIE_0_GDSC] = &pcie_0_gdsc, 2628 [PCIE_1_GDSC] = &pcie_1_gdsc, 2629 [USB30_GDSC] = &usb30_gdsc, 2630 [UFS_GDSC] = &ufs_gdsc, 2631}; 2632 2633static const struct qcom_reset_map gcc_msm8994_resets[] = { 2634 [USB3_PHY_RESET] = { 0x1400 }, 2635 [USB3PHY_PHY_RESET] = { 0x1404 }, 2636 [PCIE_PHY_0_RESET] = { 0x1b18 }, 2637 [PCIE_PHY_1_RESET] = { 0x1b98 }, 2638 [QUSB2_PHY_RESET] = { 0x04b8 }, 2639}; 2640 2641static const struct regmap_config gcc_msm8994_regmap_config = { 2642 .reg_bits = 32, 2643 .reg_stride = 4, 2644 .val_bits = 32, 2645 .max_register = 0x2000, 2646 .fast_io = true, 2647}; 2648 2649static const struct qcom_cc_desc gcc_msm8994_desc = { 2650 .config = &gcc_msm8994_regmap_config, 2651 .clks = gcc_msm8994_clocks, 2652 .num_clks = ARRAY_SIZE(gcc_msm8994_clocks), 2653 .resets = gcc_msm8994_resets, 2654 .num_resets = ARRAY_SIZE(gcc_msm8994_resets), 2655 .gdscs = gcc_msm8994_gdscs, 2656 .num_gdscs = ARRAY_SIZE(gcc_msm8994_gdscs), 2657}; 2658 2659static const struct of_device_id gcc_msm8994_match_table[] = { 2660 { .compatible = "qcom,gcc-msm8994" }, 2661 {} 2662}; 2663MODULE_DEVICE_TABLE(of, gcc_msm8994_match_table); 2664 2665static int gcc_msm8994_probe(struct platform_device *pdev) 2666{ 2667 struct device *dev = &pdev->dev; 2668 struct clk *clk; 2669 2670 clk = devm_clk_register(dev, &xo.hw); 2671 if (IS_ERR(clk)) 2672 return PTR_ERR(clk); 2673 2674 return qcom_cc_probe(pdev, &gcc_msm8994_desc); 2675} 2676 2677static struct platform_driver gcc_msm8994_driver = { 2678 .probe = gcc_msm8994_probe, 2679 .driver = { 2680 .name = "gcc-msm8994", 2681 .of_match_table = gcc_msm8994_match_table, 2682 }, 2683}; 2684 2685static int __init gcc_msm8994_init(void) 2686{ 2687 return platform_driver_register(&gcc_msm8994_driver); 2688} 2689core_initcall(gcc_msm8994_init); 2690 2691static void __exit gcc_msm8994_exit(void) 2692{ 2693 platform_driver_unregister(&gcc_msm8994_driver); 2694} 2695module_exit(gcc_msm8994_exit); 2696 2697MODULE_DESCRIPTION("Qualcomm GCC MSM8994 Driver"); 2698MODULE_LICENSE("GPL v2"); 2699MODULE_ALIAS("platform:gcc-msm8994"); 2700