1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2013, The Linux Foundation. All rights reserved. 4 */ 5 6#include <linux/kernel.h> 7#include <linux/bitops.h> 8#include <linux/err.h> 9#include <linux/platform_device.h> 10#include <linux/module.h> 11#include <linux/of.h> 12#include <linux/of_device.h> 13#include <linux/clk-provider.h> 14#include <linux/regmap.h> 15#include <linux/reset-controller.h> 16 17#include <dt-bindings/clock/qcom,gcc-msm8974.h> 18#include <dt-bindings/reset/qcom,gcc-msm8974.h> 19 20#include "common.h" 21#include "clk-regmap.h" 22#include "clk-pll.h" 23#include "clk-rcg.h" 24#include "clk-branch.h" 25#include "reset.h" 26#include "gdsc.h" 27 28enum { 29 P_XO, 30 P_GPLL0, 31 P_GPLL1, 32 P_GPLL4, 33}; 34 35static const struct parent_map gcc_xo_gpll0_map[] = { 36 { P_XO, 0 }, 37 { P_GPLL0, 1 } 38}; 39 40static const char * const gcc_xo_gpll0[] = { 41 "xo", 42 "gpll0_vote", 43}; 44 45static const struct parent_map gcc_xo_gpll0_gpll4_map[] = { 46 { P_XO, 0 }, 47 { P_GPLL0, 1 }, 48 { P_GPLL4, 5 } 49}; 50 51static const char * const gcc_xo_gpll0_gpll4[] = { 52 "xo", 53 "gpll0_vote", 54 "gpll4_vote", 55}; 56 57static struct clk_pll gpll0 = { 58 .l_reg = 0x0004, 59 .m_reg = 0x0008, 60 .n_reg = 0x000c, 61 .config_reg = 0x0014, 62 .mode_reg = 0x0000, 63 .status_reg = 0x001c, 64 .status_bit = 17, 65 .clkr.hw.init = &(struct clk_init_data){ 66 .name = "gpll0", 67 .parent_names = (const char *[]){ "xo" }, 68 .num_parents = 1, 69 .ops = &clk_pll_ops, 70 }, 71}; 72 73static struct clk_regmap gpll0_vote = { 74 .enable_reg = 0x1480, 75 .enable_mask = BIT(0), 76 .hw.init = &(struct clk_init_data){ 77 .name = "gpll0_vote", 78 .parent_names = (const char *[]){ "gpll0" }, 79 .num_parents = 1, 80 .ops = &clk_pll_vote_ops, 81 }, 82}; 83 84static struct clk_rcg2 config_noc_clk_src = { 85 .cmd_rcgr = 0x0150, 86 .hid_width = 5, 87 .parent_map = gcc_xo_gpll0_map, 88 .clkr.hw.init = &(struct clk_init_data){ 89 .name = "config_noc_clk_src", 90 .parent_names = gcc_xo_gpll0, 91 .num_parents = 2, 92 .ops = &clk_rcg2_ops, 93 }, 94}; 95 96static struct clk_rcg2 periph_noc_clk_src = { 97 .cmd_rcgr = 0x0190, 98 .hid_width = 5, 99 .parent_map = gcc_xo_gpll0_map, 100 .clkr.hw.init = &(struct clk_init_data){ 101 .name = "periph_noc_clk_src", 102 .parent_names = gcc_xo_gpll0, 103 .num_parents = 2, 104 .ops = &clk_rcg2_ops, 105 }, 106}; 107 108static struct clk_rcg2 system_noc_clk_src = { 109 .cmd_rcgr = 0x0120, 110 .hid_width = 5, 111 .parent_map = gcc_xo_gpll0_map, 112 .clkr.hw.init = &(struct clk_init_data){ 113 .name = "system_noc_clk_src", 114 .parent_names = gcc_xo_gpll0, 115 .num_parents = 2, 116 .ops = &clk_rcg2_ops, 117 }, 118}; 119 120static struct clk_pll gpll1 = { 121 .l_reg = 0x0044, 122 .m_reg = 0x0048, 123 .n_reg = 0x004c, 124 .config_reg = 0x0054, 125 .mode_reg = 0x0040, 126 .status_reg = 0x005c, 127 .status_bit = 17, 128 .clkr.hw.init = &(struct clk_init_data){ 129 .name = "gpll1", 130 .parent_names = (const char *[]){ "xo" }, 131 .num_parents = 1, 132 .ops = &clk_pll_ops, 133 }, 134}; 135 136static struct clk_regmap gpll1_vote = { 137 .enable_reg = 0x1480, 138 .enable_mask = BIT(1), 139 .hw.init = &(struct clk_init_data){ 140 .name = "gpll1_vote", 141 .parent_names = (const char *[]){ "gpll1" }, 142 .num_parents = 1, 143 .ops = &clk_pll_vote_ops, 144 }, 145}; 146 147static struct clk_pll gpll4 = { 148 .l_reg = 0x1dc4, 149 .m_reg = 0x1dc8, 150 .n_reg = 0x1dcc, 151 .config_reg = 0x1dd4, 152 .mode_reg = 0x1dc0, 153 .status_reg = 0x1ddc, 154 .status_bit = 17, 155 .clkr.hw.init = &(struct clk_init_data){ 156 .name = "gpll4", 157 .parent_names = (const char *[]){ "xo" }, 158 .num_parents = 1, 159 .ops = &clk_pll_ops, 160 }, 161}; 162 163static struct clk_regmap gpll4_vote = { 164 .enable_reg = 0x1480, 165 .enable_mask = BIT(4), 166 .hw.init = &(struct clk_init_data){ 167 .name = "gpll4_vote", 168 .parent_names = (const char *[]){ "gpll4" }, 169 .num_parents = 1, 170 .ops = &clk_pll_vote_ops, 171 }, 172}; 173 174static const struct freq_tbl ftbl_gcc_usb30_master_clk[] = { 175 F(125000000, P_GPLL0, 1, 5, 24), 176 { } 177}; 178 179static struct clk_rcg2 usb30_master_clk_src = { 180 .cmd_rcgr = 0x03d4, 181 .mnd_width = 8, 182 .hid_width = 5, 183 .parent_map = gcc_xo_gpll0_map, 184 .freq_tbl = ftbl_gcc_usb30_master_clk, 185 .clkr.hw.init = &(struct clk_init_data){ 186 .name = "usb30_master_clk_src", 187 .parent_names = gcc_xo_gpll0, 188 .num_parents = 2, 189 .ops = &clk_rcg2_ops, 190 }, 191}; 192 193static const struct freq_tbl ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk[] = { 194 F(19200000, P_XO, 1, 0, 0), 195 F(37500000, P_GPLL0, 16, 0, 0), 196 F(50000000, P_GPLL0, 12, 0, 0), 197 { } 198}; 199 200static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = { 201 .cmd_rcgr = 0x0660, 202 .hid_width = 5, 203 .parent_map = gcc_xo_gpll0_map, 204 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, 205 .clkr.hw.init = &(struct clk_init_data){ 206 .name = "blsp1_qup1_i2c_apps_clk_src", 207 .parent_names = gcc_xo_gpll0, 208 .num_parents = 2, 209 .ops = &clk_rcg2_ops, 210 }, 211}; 212 213static const struct freq_tbl ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk[] = { 214 F(960000, P_XO, 10, 1, 2), 215 F(4800000, P_XO, 4, 0, 0), 216 F(9600000, P_XO, 2, 0, 0), 217 F(15000000, P_GPLL0, 10, 1, 4), 218 F(19200000, P_XO, 1, 0, 0), 219 F(25000000, P_GPLL0, 12, 1, 2), 220 F(50000000, P_GPLL0, 12, 0, 0), 221 { } 222}; 223 224static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = { 225 .cmd_rcgr = 0x064c, 226 .mnd_width = 8, 227 .hid_width = 5, 228 .parent_map = gcc_xo_gpll0_map, 229 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, 230 .clkr.hw.init = &(struct clk_init_data){ 231 .name = "blsp1_qup1_spi_apps_clk_src", 232 .parent_names = gcc_xo_gpll0, 233 .num_parents = 2, 234 .ops = &clk_rcg2_ops, 235 }, 236}; 237 238static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = { 239 .cmd_rcgr = 0x06e0, 240 .hid_width = 5, 241 .parent_map = gcc_xo_gpll0_map, 242 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, 243 .clkr.hw.init = &(struct clk_init_data){ 244 .name = "blsp1_qup2_i2c_apps_clk_src", 245 .parent_names = gcc_xo_gpll0, 246 .num_parents = 2, 247 .ops = &clk_rcg2_ops, 248 }, 249}; 250 251static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = { 252 .cmd_rcgr = 0x06cc, 253 .mnd_width = 8, 254 .hid_width = 5, 255 .parent_map = gcc_xo_gpll0_map, 256 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, 257 .clkr.hw.init = &(struct clk_init_data){ 258 .name = "blsp1_qup2_spi_apps_clk_src", 259 .parent_names = gcc_xo_gpll0, 260 .num_parents = 2, 261 .ops = &clk_rcg2_ops, 262 }, 263}; 264 265static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = { 266 .cmd_rcgr = 0x0760, 267 .hid_width = 5, 268 .parent_map = gcc_xo_gpll0_map, 269 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, 270 .clkr.hw.init = &(struct clk_init_data){ 271 .name = "blsp1_qup3_i2c_apps_clk_src", 272 .parent_names = gcc_xo_gpll0, 273 .num_parents = 2, 274 .ops = &clk_rcg2_ops, 275 }, 276}; 277 278static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = { 279 .cmd_rcgr = 0x074c, 280 .mnd_width = 8, 281 .hid_width = 5, 282 .parent_map = gcc_xo_gpll0_map, 283 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, 284 .clkr.hw.init = &(struct clk_init_data){ 285 .name = "blsp1_qup3_spi_apps_clk_src", 286 .parent_names = gcc_xo_gpll0, 287 .num_parents = 2, 288 .ops = &clk_rcg2_ops, 289 }, 290}; 291 292static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = { 293 .cmd_rcgr = 0x07e0, 294 .hid_width = 5, 295 .parent_map = gcc_xo_gpll0_map, 296 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, 297 .clkr.hw.init = &(struct clk_init_data){ 298 .name = "blsp1_qup4_i2c_apps_clk_src", 299 .parent_names = gcc_xo_gpll0, 300 .num_parents = 2, 301 .ops = &clk_rcg2_ops, 302 }, 303}; 304 305static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = { 306 .cmd_rcgr = 0x07cc, 307 .mnd_width = 8, 308 .hid_width = 5, 309 .parent_map = gcc_xo_gpll0_map, 310 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, 311 .clkr.hw.init = &(struct clk_init_data){ 312 .name = "blsp1_qup4_spi_apps_clk_src", 313 .parent_names = gcc_xo_gpll0, 314 .num_parents = 2, 315 .ops = &clk_rcg2_ops, 316 }, 317}; 318 319static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = { 320 .cmd_rcgr = 0x0860, 321 .hid_width = 5, 322 .parent_map = gcc_xo_gpll0_map, 323 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, 324 .clkr.hw.init = &(struct clk_init_data){ 325 .name = "blsp1_qup5_i2c_apps_clk_src", 326 .parent_names = gcc_xo_gpll0, 327 .num_parents = 2, 328 .ops = &clk_rcg2_ops, 329 }, 330}; 331 332static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = { 333 .cmd_rcgr = 0x084c, 334 .mnd_width = 8, 335 .hid_width = 5, 336 .parent_map = gcc_xo_gpll0_map, 337 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, 338 .clkr.hw.init = &(struct clk_init_data){ 339 .name = "blsp1_qup5_spi_apps_clk_src", 340 .parent_names = gcc_xo_gpll0, 341 .num_parents = 2, 342 .ops = &clk_rcg2_ops, 343 }, 344}; 345 346static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = { 347 .cmd_rcgr = 0x08e0, 348 .hid_width = 5, 349 .parent_map = gcc_xo_gpll0_map, 350 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, 351 .clkr.hw.init = &(struct clk_init_data){ 352 .name = "blsp1_qup6_i2c_apps_clk_src", 353 .parent_names = gcc_xo_gpll0, 354 .num_parents = 2, 355 .ops = &clk_rcg2_ops, 356 }, 357}; 358 359static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = { 360 .cmd_rcgr = 0x08cc, 361 .mnd_width = 8, 362 .hid_width = 5, 363 .parent_map = gcc_xo_gpll0_map, 364 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, 365 .clkr.hw.init = &(struct clk_init_data){ 366 .name = "blsp1_qup6_spi_apps_clk_src", 367 .parent_names = gcc_xo_gpll0, 368 .num_parents = 2, 369 .ops = &clk_rcg2_ops, 370 }, 371}; 372 373static const struct freq_tbl ftbl_gcc_blsp1_2_uart1_6_apps_clk[] = { 374 F(3686400, P_GPLL0, 1, 96, 15625), 375 F(7372800, P_GPLL0, 1, 192, 15625), 376 F(14745600, P_GPLL0, 1, 384, 15625), 377 F(16000000, P_GPLL0, 5, 2, 15), 378 F(19200000, P_XO, 1, 0, 0), 379 F(24000000, P_GPLL0, 5, 1, 5), 380 F(32000000, P_GPLL0, 1, 4, 75), 381 F(40000000, P_GPLL0, 15, 0, 0), 382 F(46400000, P_GPLL0, 1, 29, 375), 383 F(48000000, P_GPLL0, 12.5, 0, 0), 384 F(51200000, P_GPLL0, 1, 32, 375), 385 F(56000000, P_GPLL0, 1, 7, 75), 386 F(58982400, P_GPLL0, 1, 1536, 15625), 387 F(60000000, P_GPLL0, 10, 0, 0), 388 F(63160000, P_GPLL0, 9.5, 0, 0), 389 { } 390}; 391 392static struct clk_rcg2 blsp1_uart1_apps_clk_src = { 393 .cmd_rcgr = 0x068c, 394 .mnd_width = 16, 395 .hid_width = 5, 396 .parent_map = gcc_xo_gpll0_map, 397 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, 398 .clkr.hw.init = &(struct clk_init_data){ 399 .name = "blsp1_uart1_apps_clk_src", 400 .parent_names = gcc_xo_gpll0, 401 .num_parents = 2, 402 .ops = &clk_rcg2_ops, 403 }, 404}; 405 406static struct clk_rcg2 blsp1_uart2_apps_clk_src = { 407 .cmd_rcgr = 0x070c, 408 .mnd_width = 16, 409 .hid_width = 5, 410 .parent_map = gcc_xo_gpll0_map, 411 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, 412 .clkr.hw.init = &(struct clk_init_data){ 413 .name = "blsp1_uart2_apps_clk_src", 414 .parent_names = gcc_xo_gpll0, 415 .num_parents = 2, 416 .ops = &clk_rcg2_ops, 417 }, 418}; 419 420static struct clk_rcg2 blsp1_uart3_apps_clk_src = { 421 .cmd_rcgr = 0x078c, 422 .mnd_width = 16, 423 .hid_width = 5, 424 .parent_map = gcc_xo_gpll0_map, 425 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, 426 .clkr.hw.init = &(struct clk_init_data){ 427 .name = "blsp1_uart3_apps_clk_src", 428 .parent_names = gcc_xo_gpll0, 429 .num_parents = 2, 430 .ops = &clk_rcg2_ops, 431 }, 432}; 433 434static struct clk_rcg2 blsp1_uart4_apps_clk_src = { 435 .cmd_rcgr = 0x080c, 436 .mnd_width = 16, 437 .hid_width = 5, 438 .parent_map = gcc_xo_gpll0_map, 439 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, 440 .clkr.hw.init = &(struct clk_init_data){ 441 .name = "blsp1_uart4_apps_clk_src", 442 .parent_names = gcc_xo_gpll0, 443 .num_parents = 2, 444 .ops = &clk_rcg2_ops, 445 }, 446}; 447 448static struct clk_rcg2 blsp1_uart5_apps_clk_src = { 449 .cmd_rcgr = 0x088c, 450 .mnd_width = 16, 451 .hid_width = 5, 452 .parent_map = gcc_xo_gpll0_map, 453 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, 454 .clkr.hw.init = &(struct clk_init_data){ 455 .name = "blsp1_uart5_apps_clk_src", 456 .parent_names = gcc_xo_gpll0, 457 .num_parents = 2, 458 .ops = &clk_rcg2_ops, 459 }, 460}; 461 462static struct clk_rcg2 blsp1_uart6_apps_clk_src = { 463 .cmd_rcgr = 0x090c, 464 .mnd_width = 16, 465 .hid_width = 5, 466 .parent_map = gcc_xo_gpll0_map, 467 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, 468 .clkr.hw.init = &(struct clk_init_data){ 469 .name = "blsp1_uart6_apps_clk_src", 470 .parent_names = gcc_xo_gpll0, 471 .num_parents = 2, 472 .ops = &clk_rcg2_ops, 473 }, 474}; 475 476static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = { 477 .cmd_rcgr = 0x09a0, 478 .hid_width = 5, 479 .parent_map = gcc_xo_gpll0_map, 480 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, 481 .clkr.hw.init = &(struct clk_init_data){ 482 .name = "blsp2_qup1_i2c_apps_clk_src", 483 .parent_names = gcc_xo_gpll0, 484 .num_parents = 2, 485 .ops = &clk_rcg2_ops, 486 }, 487}; 488 489static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = { 490 .cmd_rcgr = 0x098c, 491 .mnd_width = 8, 492 .hid_width = 5, 493 .parent_map = gcc_xo_gpll0_map, 494 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, 495 .clkr.hw.init = &(struct clk_init_data){ 496 .name = "blsp2_qup1_spi_apps_clk_src", 497 .parent_names = gcc_xo_gpll0, 498 .num_parents = 2, 499 .ops = &clk_rcg2_ops, 500 }, 501}; 502 503static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = { 504 .cmd_rcgr = 0x0a20, 505 .hid_width = 5, 506 .parent_map = gcc_xo_gpll0_map, 507 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, 508 .clkr.hw.init = &(struct clk_init_data){ 509 .name = "blsp2_qup2_i2c_apps_clk_src", 510 .parent_names = gcc_xo_gpll0, 511 .num_parents = 2, 512 .ops = &clk_rcg2_ops, 513 }, 514}; 515 516static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = { 517 .cmd_rcgr = 0x0a0c, 518 .mnd_width = 8, 519 .hid_width = 5, 520 .parent_map = gcc_xo_gpll0_map, 521 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, 522 .clkr.hw.init = &(struct clk_init_data){ 523 .name = "blsp2_qup2_spi_apps_clk_src", 524 .parent_names = gcc_xo_gpll0, 525 .num_parents = 2, 526 .ops = &clk_rcg2_ops, 527 }, 528}; 529 530static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = { 531 .cmd_rcgr = 0x0aa0, 532 .hid_width = 5, 533 .parent_map = gcc_xo_gpll0_map, 534 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, 535 .clkr.hw.init = &(struct clk_init_data){ 536 .name = "blsp2_qup3_i2c_apps_clk_src", 537 .parent_names = gcc_xo_gpll0, 538 .num_parents = 2, 539 .ops = &clk_rcg2_ops, 540 }, 541}; 542 543static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = { 544 .cmd_rcgr = 0x0a8c, 545 .mnd_width = 8, 546 .hid_width = 5, 547 .parent_map = gcc_xo_gpll0_map, 548 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, 549 .clkr.hw.init = &(struct clk_init_data){ 550 .name = "blsp2_qup3_spi_apps_clk_src", 551 .parent_names = gcc_xo_gpll0, 552 .num_parents = 2, 553 .ops = &clk_rcg2_ops, 554 }, 555}; 556 557static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = { 558 .cmd_rcgr = 0x0b20, 559 .hid_width = 5, 560 .parent_map = gcc_xo_gpll0_map, 561 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, 562 .clkr.hw.init = &(struct clk_init_data){ 563 .name = "blsp2_qup4_i2c_apps_clk_src", 564 .parent_names = gcc_xo_gpll0, 565 .num_parents = 2, 566 .ops = &clk_rcg2_ops, 567 }, 568}; 569 570static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = { 571 .cmd_rcgr = 0x0b0c, 572 .mnd_width = 8, 573 .hid_width = 5, 574 .parent_map = gcc_xo_gpll0_map, 575 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, 576 .clkr.hw.init = &(struct clk_init_data){ 577 .name = "blsp2_qup4_spi_apps_clk_src", 578 .parent_names = gcc_xo_gpll0, 579 .num_parents = 2, 580 .ops = &clk_rcg2_ops, 581 }, 582}; 583 584static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = { 585 .cmd_rcgr = 0x0ba0, 586 .hid_width = 5, 587 .parent_map = gcc_xo_gpll0_map, 588 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, 589 .clkr.hw.init = &(struct clk_init_data){ 590 .name = "blsp2_qup5_i2c_apps_clk_src", 591 .parent_names = gcc_xo_gpll0, 592 .num_parents = 2, 593 .ops = &clk_rcg2_ops, 594 }, 595}; 596 597static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = { 598 .cmd_rcgr = 0x0b8c, 599 .mnd_width = 8, 600 .hid_width = 5, 601 .parent_map = gcc_xo_gpll0_map, 602 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, 603 .clkr.hw.init = &(struct clk_init_data){ 604 .name = "blsp2_qup5_spi_apps_clk_src", 605 .parent_names = gcc_xo_gpll0, 606 .num_parents = 2, 607 .ops = &clk_rcg2_ops, 608 }, 609}; 610 611static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = { 612 .cmd_rcgr = 0x0c20, 613 .hid_width = 5, 614 .parent_map = gcc_xo_gpll0_map, 615 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, 616 .clkr.hw.init = &(struct clk_init_data){ 617 .name = "blsp2_qup6_i2c_apps_clk_src", 618 .parent_names = gcc_xo_gpll0, 619 .num_parents = 2, 620 .ops = &clk_rcg2_ops, 621 }, 622}; 623 624static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = { 625 .cmd_rcgr = 0x0c0c, 626 .mnd_width = 8, 627 .hid_width = 5, 628 .parent_map = gcc_xo_gpll0_map, 629 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, 630 .clkr.hw.init = &(struct clk_init_data){ 631 .name = "blsp2_qup6_spi_apps_clk_src", 632 .parent_names = gcc_xo_gpll0, 633 .num_parents = 2, 634 .ops = &clk_rcg2_ops, 635 }, 636}; 637 638static struct clk_rcg2 blsp2_uart1_apps_clk_src = { 639 .cmd_rcgr = 0x09cc, 640 .mnd_width = 16, 641 .hid_width = 5, 642 .parent_map = gcc_xo_gpll0_map, 643 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, 644 .clkr.hw.init = &(struct clk_init_data){ 645 .name = "blsp2_uart1_apps_clk_src", 646 .parent_names = gcc_xo_gpll0, 647 .num_parents = 2, 648 .ops = &clk_rcg2_ops, 649 }, 650}; 651 652static struct clk_rcg2 blsp2_uart2_apps_clk_src = { 653 .cmd_rcgr = 0x0a4c, 654 .mnd_width = 16, 655 .hid_width = 5, 656 .parent_map = gcc_xo_gpll0_map, 657 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, 658 .clkr.hw.init = &(struct clk_init_data){ 659 .name = "blsp2_uart2_apps_clk_src", 660 .parent_names = gcc_xo_gpll0, 661 .num_parents = 2, 662 .ops = &clk_rcg2_ops, 663 }, 664}; 665 666static struct clk_rcg2 blsp2_uart3_apps_clk_src = { 667 .cmd_rcgr = 0x0acc, 668 .mnd_width = 16, 669 .hid_width = 5, 670 .parent_map = gcc_xo_gpll0_map, 671 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, 672 .clkr.hw.init = &(struct clk_init_data){ 673 .name = "blsp2_uart3_apps_clk_src", 674 .parent_names = gcc_xo_gpll0, 675 .num_parents = 2, 676 .ops = &clk_rcg2_ops, 677 }, 678}; 679 680static struct clk_rcg2 blsp2_uart4_apps_clk_src = { 681 .cmd_rcgr = 0x0b4c, 682 .mnd_width = 16, 683 .hid_width = 5, 684 .parent_map = gcc_xo_gpll0_map, 685 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, 686 .clkr.hw.init = &(struct clk_init_data){ 687 .name = "blsp2_uart4_apps_clk_src", 688 .parent_names = gcc_xo_gpll0, 689 .num_parents = 2, 690 .ops = &clk_rcg2_ops, 691 }, 692}; 693 694static struct clk_rcg2 blsp2_uart5_apps_clk_src = { 695 .cmd_rcgr = 0x0bcc, 696 .mnd_width = 16, 697 .hid_width = 5, 698 .parent_map = gcc_xo_gpll0_map, 699 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, 700 .clkr.hw.init = &(struct clk_init_data){ 701 .name = "blsp2_uart5_apps_clk_src", 702 .parent_names = gcc_xo_gpll0, 703 .num_parents = 2, 704 .ops = &clk_rcg2_ops, 705 }, 706}; 707 708static struct clk_rcg2 blsp2_uart6_apps_clk_src = { 709 .cmd_rcgr = 0x0c4c, 710 .mnd_width = 16, 711 .hid_width = 5, 712 .parent_map = gcc_xo_gpll0_map, 713 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, 714 .clkr.hw.init = &(struct clk_init_data){ 715 .name = "blsp2_uart6_apps_clk_src", 716 .parent_names = gcc_xo_gpll0, 717 .num_parents = 2, 718 .ops = &clk_rcg2_ops, 719 }, 720}; 721 722static const struct freq_tbl ftbl_gcc_ce1_clk[] = { 723 F(50000000, P_GPLL0, 12, 0, 0), 724 F(75000000, P_GPLL0, 8, 0, 0), 725 F(100000000, P_GPLL0, 6, 0, 0), 726 F(150000000, P_GPLL0, 4, 0, 0), 727 { } 728}; 729 730static struct clk_rcg2 ce1_clk_src = { 731 .cmd_rcgr = 0x1050, 732 .hid_width = 5, 733 .parent_map = gcc_xo_gpll0_map, 734 .freq_tbl = ftbl_gcc_ce1_clk, 735 .clkr.hw.init = &(struct clk_init_data){ 736 .name = "ce1_clk_src", 737 .parent_names = gcc_xo_gpll0, 738 .num_parents = 2, 739 .ops = &clk_rcg2_ops, 740 }, 741}; 742 743static const struct freq_tbl ftbl_gcc_ce2_clk[] = { 744 F(50000000, P_GPLL0, 12, 0, 0), 745 F(75000000, P_GPLL0, 8, 0, 0), 746 F(100000000, P_GPLL0, 6, 0, 0), 747 F(150000000, P_GPLL0, 4, 0, 0), 748 { } 749}; 750 751static struct clk_rcg2 ce2_clk_src = { 752 .cmd_rcgr = 0x1090, 753 .hid_width = 5, 754 .parent_map = gcc_xo_gpll0_map, 755 .freq_tbl = ftbl_gcc_ce2_clk, 756 .clkr.hw.init = &(struct clk_init_data){ 757 .name = "ce2_clk_src", 758 .parent_names = gcc_xo_gpll0, 759 .num_parents = 2, 760 .ops = &clk_rcg2_ops, 761 }, 762}; 763 764static const struct freq_tbl ftbl_gcc_gp_clk[] = { 765 F(4800000, P_XO, 4, 0, 0), 766 F(6000000, P_GPLL0, 10, 1, 10), 767 F(6750000, P_GPLL0, 1, 1, 89), 768 F(8000000, P_GPLL0, 15, 1, 5), 769 F(9600000, P_XO, 2, 0, 0), 770 F(16000000, P_GPLL0, 1, 2, 75), 771 F(19200000, P_XO, 1, 0, 0), 772 F(24000000, P_GPLL0, 5, 1, 5), 773 { } 774}; 775 776 777static struct clk_rcg2 gp1_clk_src = { 778 .cmd_rcgr = 0x1904, 779 .mnd_width = 8, 780 .hid_width = 5, 781 .parent_map = gcc_xo_gpll0_map, 782 .freq_tbl = ftbl_gcc_gp_clk, 783 .clkr.hw.init = &(struct clk_init_data){ 784 .name = "gp1_clk_src", 785 .parent_names = gcc_xo_gpll0, 786 .num_parents = 2, 787 .ops = &clk_rcg2_ops, 788 }, 789}; 790 791static struct clk_rcg2 gp2_clk_src = { 792 .cmd_rcgr = 0x1944, 793 .mnd_width = 8, 794 .hid_width = 5, 795 .parent_map = gcc_xo_gpll0_map, 796 .freq_tbl = ftbl_gcc_gp_clk, 797 .clkr.hw.init = &(struct clk_init_data){ 798 .name = "gp2_clk_src", 799 .parent_names = gcc_xo_gpll0, 800 .num_parents = 2, 801 .ops = &clk_rcg2_ops, 802 }, 803}; 804 805static struct clk_rcg2 gp3_clk_src = { 806 .cmd_rcgr = 0x1984, 807 .mnd_width = 8, 808 .hid_width = 5, 809 .parent_map = gcc_xo_gpll0_map, 810 .freq_tbl = ftbl_gcc_gp_clk, 811 .clkr.hw.init = &(struct clk_init_data){ 812 .name = "gp3_clk_src", 813 .parent_names = gcc_xo_gpll0, 814 .num_parents = 2, 815 .ops = &clk_rcg2_ops, 816 }, 817}; 818 819static const struct freq_tbl ftbl_gcc_pdm2_clk[] = { 820 F(60000000, P_GPLL0, 10, 0, 0), 821 { } 822}; 823 824static struct clk_rcg2 pdm2_clk_src = { 825 .cmd_rcgr = 0x0cd0, 826 .hid_width = 5, 827 .parent_map = gcc_xo_gpll0_map, 828 .freq_tbl = ftbl_gcc_pdm2_clk, 829 .clkr.hw.init = &(struct clk_init_data){ 830 .name = "pdm2_clk_src", 831 .parent_names = gcc_xo_gpll0, 832 .num_parents = 2, 833 .ops = &clk_rcg2_ops, 834 }, 835}; 836 837static const struct freq_tbl ftbl_gcc_sdcc1_4_apps_clk[] = { 838 F(144000, P_XO, 16, 3, 25), 839 F(400000, P_XO, 12, 1, 4), 840 F(20000000, P_GPLL0, 15, 1, 2), 841 F(25000000, P_GPLL0, 12, 1, 2), 842 F(50000000, P_GPLL0, 12, 0, 0), 843 F(100000000, P_GPLL0, 6, 0, 0), 844 F(200000000, P_GPLL0, 3, 0, 0), 845 { } 846}; 847 848static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_pro[] = { 849 F(144000, P_XO, 16, 3, 25), 850 F(400000, P_XO, 12, 1, 4), 851 F(20000000, P_GPLL0, 15, 1, 2), 852 F(25000000, P_GPLL0, 12, 1, 2), 853 F(50000000, P_GPLL0, 12, 0, 0), 854 F(100000000, P_GPLL0, 6, 0, 0), 855 F(192000000, P_GPLL4, 4, 0, 0), 856 F(200000000, P_GPLL0, 3, 0, 0), 857 F(384000000, P_GPLL4, 2, 0, 0), 858 { } 859}; 860 861static struct clk_init_data sdcc1_apps_clk_src_init = { 862 .name = "sdcc1_apps_clk_src", 863 .parent_names = gcc_xo_gpll0, 864 .num_parents = 2, 865 .ops = &clk_rcg2_floor_ops, 866}; 867 868static struct clk_rcg2 sdcc1_apps_clk_src = { 869 .cmd_rcgr = 0x04d0, 870 .mnd_width = 8, 871 .hid_width = 5, 872 .parent_map = gcc_xo_gpll0_map, 873 .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk, 874 .clkr.hw.init = &sdcc1_apps_clk_src_init, 875}; 876 877static struct clk_rcg2 sdcc2_apps_clk_src = { 878 .cmd_rcgr = 0x0510, 879 .mnd_width = 8, 880 .hid_width = 5, 881 .parent_map = gcc_xo_gpll0_map, 882 .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk, 883 .clkr.hw.init = &(struct clk_init_data){ 884 .name = "sdcc2_apps_clk_src", 885 .parent_names = gcc_xo_gpll0, 886 .num_parents = 2, 887 .ops = &clk_rcg2_floor_ops, 888 }, 889}; 890 891static struct clk_rcg2 sdcc3_apps_clk_src = { 892 .cmd_rcgr = 0x0550, 893 .mnd_width = 8, 894 .hid_width = 5, 895 .parent_map = gcc_xo_gpll0_map, 896 .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk, 897 .clkr.hw.init = &(struct clk_init_data){ 898 .name = "sdcc3_apps_clk_src", 899 .parent_names = gcc_xo_gpll0, 900 .num_parents = 2, 901 .ops = &clk_rcg2_floor_ops, 902 }, 903}; 904 905static struct clk_rcg2 sdcc4_apps_clk_src = { 906 .cmd_rcgr = 0x0590, 907 .mnd_width = 8, 908 .hid_width = 5, 909 .parent_map = gcc_xo_gpll0_map, 910 .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk, 911 .clkr.hw.init = &(struct clk_init_data){ 912 .name = "sdcc4_apps_clk_src", 913 .parent_names = gcc_xo_gpll0, 914 .num_parents = 2, 915 .ops = &clk_rcg2_floor_ops, 916 }, 917}; 918 919static const struct freq_tbl ftbl_gcc_tsif_ref_clk[] = { 920 F(105000, P_XO, 2, 1, 91), 921 { } 922}; 923 924static struct clk_rcg2 tsif_ref_clk_src = { 925 .cmd_rcgr = 0x0d90, 926 .mnd_width = 8, 927 .hid_width = 5, 928 .parent_map = gcc_xo_gpll0_map, 929 .freq_tbl = ftbl_gcc_tsif_ref_clk, 930 .clkr.hw.init = &(struct clk_init_data){ 931 .name = "tsif_ref_clk_src", 932 .parent_names = gcc_xo_gpll0, 933 .num_parents = 2, 934 .ops = &clk_rcg2_ops, 935 }, 936}; 937 938static const struct freq_tbl ftbl_gcc_usb30_mock_utmi_clk[] = { 939 F(60000000, P_GPLL0, 10, 0, 0), 940 { } 941}; 942 943static struct clk_rcg2 usb30_mock_utmi_clk_src = { 944 .cmd_rcgr = 0x03e8, 945 .hid_width = 5, 946 .parent_map = gcc_xo_gpll0_map, 947 .freq_tbl = ftbl_gcc_usb30_mock_utmi_clk, 948 .clkr.hw.init = &(struct clk_init_data){ 949 .name = "usb30_mock_utmi_clk_src", 950 .parent_names = gcc_xo_gpll0, 951 .num_parents = 2, 952 .ops = &clk_rcg2_ops, 953 }, 954}; 955 956static const struct freq_tbl ftbl_gcc_usb_hs_system_clk[] = { 957 F(60000000, P_GPLL0, 10, 0, 0), 958 F(75000000, P_GPLL0, 8, 0, 0), 959 { } 960}; 961 962static struct clk_rcg2 usb_hs_system_clk_src = { 963 .cmd_rcgr = 0x0490, 964 .hid_width = 5, 965 .parent_map = gcc_xo_gpll0_map, 966 .freq_tbl = ftbl_gcc_usb_hs_system_clk, 967 .clkr.hw.init = &(struct clk_init_data){ 968 .name = "usb_hs_system_clk_src", 969 .parent_names = gcc_xo_gpll0, 970 .num_parents = 2, 971 .ops = &clk_rcg2_ops, 972 }, 973}; 974 975static const struct freq_tbl ftbl_gcc_usb_hsic_clk[] = { 976 F(480000000, P_GPLL1, 1, 0, 0), 977 { } 978}; 979 980static const struct parent_map usb_hsic_clk_src_map[] = { 981 { P_XO, 0 }, 982 { P_GPLL1, 4 } 983}; 984 985static struct clk_rcg2 usb_hsic_clk_src = { 986 .cmd_rcgr = 0x0440, 987 .hid_width = 5, 988 .parent_map = usb_hsic_clk_src_map, 989 .freq_tbl = ftbl_gcc_usb_hsic_clk, 990 .clkr.hw.init = &(struct clk_init_data){ 991 .name = "usb_hsic_clk_src", 992 .parent_names = (const char *[]){ 993 "xo", 994 "gpll1_vote", 995 }, 996 .num_parents = 2, 997 .ops = &clk_rcg2_ops, 998 }, 999}; 1000 1001static const struct freq_tbl ftbl_gcc_usb_hsic_io_cal_clk[] = { 1002 F(9600000, P_XO, 2, 0, 0), 1003 { } 1004}; 1005 1006static struct clk_rcg2 usb_hsic_io_cal_clk_src = { 1007 .cmd_rcgr = 0x0458, 1008 .hid_width = 5, 1009 .parent_map = gcc_xo_gpll0_map, 1010 .freq_tbl = ftbl_gcc_usb_hsic_io_cal_clk, 1011 .clkr.hw.init = &(struct clk_init_data){ 1012 .name = "usb_hsic_io_cal_clk_src", 1013 .parent_names = gcc_xo_gpll0, 1014 .num_parents = 1, 1015 .ops = &clk_rcg2_ops, 1016 }, 1017}; 1018 1019static const struct freq_tbl ftbl_gcc_usb_hsic_system_clk[] = { 1020 F(60000000, P_GPLL0, 10, 0, 0), 1021 F(75000000, P_GPLL0, 8, 0, 0), 1022 { } 1023}; 1024 1025static struct clk_rcg2 usb_hsic_system_clk_src = { 1026 .cmd_rcgr = 0x041c, 1027 .hid_width = 5, 1028 .parent_map = gcc_xo_gpll0_map, 1029 .freq_tbl = ftbl_gcc_usb_hsic_system_clk, 1030 .clkr.hw.init = &(struct clk_init_data){ 1031 .name = "usb_hsic_system_clk_src", 1032 .parent_names = gcc_xo_gpll0, 1033 .num_parents = 2, 1034 .ops = &clk_rcg2_ops, 1035 }, 1036}; 1037 1038static struct clk_regmap gcc_mmss_gpll0_clk_src = { 1039 .enable_reg = 0x1484, 1040 .enable_mask = BIT(26), 1041 .hw.init = &(struct clk_init_data){ 1042 .name = "mmss_gpll0_vote", 1043 .parent_names = (const char *[]){ 1044 "gpll0_vote", 1045 }, 1046 .num_parents = 1, 1047 .ops = &clk_branch_simple_ops, 1048 }, 1049}; 1050 1051static struct clk_branch gcc_bam_dma_ahb_clk = { 1052 .halt_reg = 0x0d44, 1053 .halt_check = BRANCH_HALT_VOTED, 1054 .clkr = { 1055 .enable_reg = 0x1484, 1056 .enable_mask = BIT(12), 1057 .hw.init = &(struct clk_init_data){ 1058 .name = "gcc_bam_dma_ahb_clk", 1059 .parent_names = (const char *[]){ 1060 "periph_noc_clk_src", 1061 }, 1062 .num_parents = 1, 1063 .ops = &clk_branch2_ops, 1064 }, 1065 }, 1066}; 1067 1068static struct clk_branch gcc_blsp1_ahb_clk = { 1069 .halt_reg = 0x05c4, 1070 .halt_check = BRANCH_HALT_VOTED, 1071 .clkr = { 1072 .enable_reg = 0x1484, 1073 .enable_mask = BIT(17), 1074 .hw.init = &(struct clk_init_data){ 1075 .name = "gcc_blsp1_ahb_clk", 1076 .parent_names = (const char *[]){ 1077 "periph_noc_clk_src", 1078 }, 1079 .num_parents = 1, 1080 .ops = &clk_branch2_ops, 1081 }, 1082 }, 1083}; 1084 1085static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = { 1086 .halt_reg = 0x0648, 1087 .clkr = { 1088 .enable_reg = 0x0648, 1089 .enable_mask = BIT(0), 1090 .hw.init = &(struct clk_init_data){ 1091 .name = "gcc_blsp1_qup1_i2c_apps_clk", 1092 .parent_names = (const char *[]){ 1093 "blsp1_qup1_i2c_apps_clk_src", 1094 }, 1095 .num_parents = 1, 1096 .flags = CLK_SET_RATE_PARENT, 1097 .ops = &clk_branch2_ops, 1098 }, 1099 }, 1100}; 1101 1102static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = { 1103 .halt_reg = 0x0644, 1104 .clkr = { 1105 .enable_reg = 0x0644, 1106 .enable_mask = BIT(0), 1107 .hw.init = &(struct clk_init_data){ 1108 .name = "gcc_blsp1_qup1_spi_apps_clk", 1109 .parent_names = (const char *[]){ 1110 "blsp1_qup1_spi_apps_clk_src", 1111 }, 1112 .num_parents = 1, 1113 .flags = CLK_SET_RATE_PARENT, 1114 .ops = &clk_branch2_ops, 1115 }, 1116 }, 1117}; 1118 1119static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = { 1120 .halt_reg = 0x06c8, 1121 .clkr = { 1122 .enable_reg = 0x06c8, 1123 .enable_mask = BIT(0), 1124 .hw.init = &(struct clk_init_data){ 1125 .name = "gcc_blsp1_qup2_i2c_apps_clk", 1126 .parent_names = (const char *[]){ 1127 "blsp1_qup2_i2c_apps_clk_src", 1128 }, 1129 .num_parents = 1, 1130 .flags = CLK_SET_RATE_PARENT, 1131 .ops = &clk_branch2_ops, 1132 }, 1133 }, 1134}; 1135 1136static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = { 1137 .halt_reg = 0x06c4, 1138 .clkr = { 1139 .enable_reg = 0x06c4, 1140 .enable_mask = BIT(0), 1141 .hw.init = &(struct clk_init_data){ 1142 .name = "gcc_blsp1_qup2_spi_apps_clk", 1143 .parent_names = (const char *[]){ 1144 "blsp1_qup2_spi_apps_clk_src", 1145 }, 1146 .num_parents = 1, 1147 .flags = CLK_SET_RATE_PARENT, 1148 .ops = &clk_branch2_ops, 1149 }, 1150 }, 1151}; 1152 1153static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = { 1154 .halt_reg = 0x0748, 1155 .clkr = { 1156 .enable_reg = 0x0748, 1157 .enable_mask = BIT(0), 1158 .hw.init = &(struct clk_init_data){ 1159 .name = "gcc_blsp1_qup3_i2c_apps_clk", 1160 .parent_names = (const char *[]){ 1161 "blsp1_qup3_i2c_apps_clk_src", 1162 }, 1163 .num_parents = 1, 1164 .flags = CLK_SET_RATE_PARENT, 1165 .ops = &clk_branch2_ops, 1166 }, 1167 }, 1168}; 1169 1170static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = { 1171 .halt_reg = 0x0744, 1172 .clkr = { 1173 .enable_reg = 0x0744, 1174 .enable_mask = BIT(0), 1175 .hw.init = &(struct clk_init_data){ 1176 .name = "gcc_blsp1_qup3_spi_apps_clk", 1177 .parent_names = (const char *[]){ 1178 "blsp1_qup3_spi_apps_clk_src", 1179 }, 1180 .num_parents = 1, 1181 .flags = CLK_SET_RATE_PARENT, 1182 .ops = &clk_branch2_ops, 1183 }, 1184 }, 1185}; 1186 1187static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = { 1188 .halt_reg = 0x07c8, 1189 .clkr = { 1190 .enable_reg = 0x07c8, 1191 .enable_mask = BIT(0), 1192 .hw.init = &(struct clk_init_data){ 1193 .name = "gcc_blsp1_qup4_i2c_apps_clk", 1194 .parent_names = (const char *[]){ 1195 "blsp1_qup4_i2c_apps_clk_src", 1196 }, 1197 .num_parents = 1, 1198 .flags = CLK_SET_RATE_PARENT, 1199 .ops = &clk_branch2_ops, 1200 }, 1201 }, 1202}; 1203 1204static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = { 1205 .halt_reg = 0x07c4, 1206 .clkr = { 1207 .enable_reg = 0x07c4, 1208 .enable_mask = BIT(0), 1209 .hw.init = &(struct clk_init_data){ 1210 .name = "gcc_blsp1_qup4_spi_apps_clk", 1211 .parent_names = (const char *[]){ 1212 "blsp1_qup4_spi_apps_clk_src", 1213 }, 1214 .num_parents = 1, 1215 .flags = CLK_SET_RATE_PARENT, 1216 .ops = &clk_branch2_ops, 1217 }, 1218 }, 1219}; 1220 1221static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = { 1222 .halt_reg = 0x0848, 1223 .clkr = { 1224 .enable_reg = 0x0848, 1225 .enable_mask = BIT(0), 1226 .hw.init = &(struct clk_init_data){ 1227 .name = "gcc_blsp1_qup5_i2c_apps_clk", 1228 .parent_names = (const char *[]){ 1229 "blsp1_qup5_i2c_apps_clk_src", 1230 }, 1231 .num_parents = 1, 1232 .flags = CLK_SET_RATE_PARENT, 1233 .ops = &clk_branch2_ops, 1234 }, 1235 }, 1236}; 1237 1238static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = { 1239 .halt_reg = 0x0844, 1240 .clkr = { 1241 .enable_reg = 0x0844, 1242 .enable_mask = BIT(0), 1243 .hw.init = &(struct clk_init_data){ 1244 .name = "gcc_blsp1_qup5_spi_apps_clk", 1245 .parent_names = (const char *[]){ 1246 "blsp1_qup5_spi_apps_clk_src", 1247 }, 1248 .num_parents = 1, 1249 .flags = CLK_SET_RATE_PARENT, 1250 .ops = &clk_branch2_ops, 1251 }, 1252 }, 1253}; 1254 1255static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = { 1256 .halt_reg = 0x08c8, 1257 .clkr = { 1258 .enable_reg = 0x08c8, 1259 .enable_mask = BIT(0), 1260 .hw.init = &(struct clk_init_data){ 1261 .name = "gcc_blsp1_qup6_i2c_apps_clk", 1262 .parent_names = (const char *[]){ 1263 "blsp1_qup6_i2c_apps_clk_src", 1264 }, 1265 .num_parents = 1, 1266 .flags = CLK_SET_RATE_PARENT, 1267 .ops = &clk_branch2_ops, 1268 }, 1269 }, 1270}; 1271 1272static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = { 1273 .halt_reg = 0x08c4, 1274 .clkr = { 1275 .enable_reg = 0x08c4, 1276 .enable_mask = BIT(0), 1277 .hw.init = &(struct clk_init_data){ 1278 .name = "gcc_blsp1_qup6_spi_apps_clk", 1279 .parent_names = (const char *[]){ 1280 "blsp1_qup6_spi_apps_clk_src", 1281 }, 1282 .num_parents = 1, 1283 .flags = CLK_SET_RATE_PARENT, 1284 .ops = &clk_branch2_ops, 1285 }, 1286 }, 1287}; 1288 1289static struct clk_branch gcc_blsp1_uart1_apps_clk = { 1290 .halt_reg = 0x0684, 1291 .clkr = { 1292 .enable_reg = 0x0684, 1293 .enable_mask = BIT(0), 1294 .hw.init = &(struct clk_init_data){ 1295 .name = "gcc_blsp1_uart1_apps_clk", 1296 .parent_names = (const char *[]){ 1297 "blsp1_uart1_apps_clk_src", 1298 }, 1299 .num_parents = 1, 1300 .flags = CLK_SET_RATE_PARENT, 1301 .ops = &clk_branch2_ops, 1302 }, 1303 }, 1304}; 1305 1306static struct clk_branch gcc_blsp1_uart2_apps_clk = { 1307 .halt_reg = 0x0704, 1308 .clkr = { 1309 .enable_reg = 0x0704, 1310 .enable_mask = BIT(0), 1311 .hw.init = &(struct clk_init_data){ 1312 .name = "gcc_blsp1_uart2_apps_clk", 1313 .parent_names = (const char *[]){ 1314 "blsp1_uart2_apps_clk_src", 1315 }, 1316 .num_parents = 1, 1317 .flags = CLK_SET_RATE_PARENT, 1318 .ops = &clk_branch2_ops, 1319 }, 1320 }, 1321}; 1322 1323static struct clk_branch gcc_blsp1_uart3_apps_clk = { 1324 .halt_reg = 0x0784, 1325 .clkr = { 1326 .enable_reg = 0x0784, 1327 .enable_mask = BIT(0), 1328 .hw.init = &(struct clk_init_data){ 1329 .name = "gcc_blsp1_uart3_apps_clk", 1330 .parent_names = (const char *[]){ 1331 "blsp1_uart3_apps_clk_src", 1332 }, 1333 .num_parents = 1, 1334 .flags = CLK_SET_RATE_PARENT, 1335 .ops = &clk_branch2_ops, 1336 }, 1337 }, 1338}; 1339 1340static struct clk_branch gcc_blsp1_uart4_apps_clk = { 1341 .halt_reg = 0x0804, 1342 .clkr = { 1343 .enable_reg = 0x0804, 1344 .enable_mask = BIT(0), 1345 .hw.init = &(struct clk_init_data){ 1346 .name = "gcc_blsp1_uart4_apps_clk", 1347 .parent_names = (const char *[]){ 1348 "blsp1_uart4_apps_clk_src", 1349 }, 1350 .num_parents = 1, 1351 .flags = CLK_SET_RATE_PARENT, 1352 .ops = &clk_branch2_ops, 1353 }, 1354 }, 1355}; 1356 1357static struct clk_branch gcc_blsp1_uart5_apps_clk = { 1358 .halt_reg = 0x0884, 1359 .clkr = { 1360 .enable_reg = 0x0884, 1361 .enable_mask = BIT(0), 1362 .hw.init = &(struct clk_init_data){ 1363 .name = "gcc_blsp1_uart5_apps_clk", 1364 .parent_names = (const char *[]){ 1365 "blsp1_uart5_apps_clk_src", 1366 }, 1367 .num_parents = 1, 1368 .flags = CLK_SET_RATE_PARENT, 1369 .ops = &clk_branch2_ops, 1370 }, 1371 }, 1372}; 1373 1374static struct clk_branch gcc_blsp1_uart6_apps_clk = { 1375 .halt_reg = 0x0904, 1376 .clkr = { 1377 .enable_reg = 0x0904, 1378 .enable_mask = BIT(0), 1379 .hw.init = &(struct clk_init_data){ 1380 .name = "gcc_blsp1_uart6_apps_clk", 1381 .parent_names = (const char *[]){ 1382 "blsp1_uart6_apps_clk_src", 1383 }, 1384 .num_parents = 1, 1385 .flags = CLK_SET_RATE_PARENT, 1386 .ops = &clk_branch2_ops, 1387 }, 1388 }, 1389}; 1390 1391static struct clk_branch gcc_blsp2_ahb_clk = { 1392 .halt_reg = 0x0944, 1393 .halt_check = BRANCH_HALT_VOTED, 1394 .clkr = { 1395 .enable_reg = 0x1484, 1396 .enable_mask = BIT(15), 1397 .hw.init = &(struct clk_init_data){ 1398 .name = "gcc_blsp2_ahb_clk", 1399 .parent_names = (const char *[]){ 1400 "periph_noc_clk_src", 1401 }, 1402 .num_parents = 1, 1403 .ops = &clk_branch2_ops, 1404 }, 1405 }, 1406}; 1407 1408static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = { 1409 .halt_reg = 0x0988, 1410 .clkr = { 1411 .enable_reg = 0x0988, 1412 .enable_mask = BIT(0), 1413 .hw.init = &(struct clk_init_data){ 1414 .name = "gcc_blsp2_qup1_i2c_apps_clk", 1415 .parent_names = (const char *[]){ 1416 "blsp2_qup1_i2c_apps_clk_src", 1417 }, 1418 .num_parents = 1, 1419 .flags = CLK_SET_RATE_PARENT, 1420 .ops = &clk_branch2_ops, 1421 }, 1422 }, 1423}; 1424 1425static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = { 1426 .halt_reg = 0x0984, 1427 .clkr = { 1428 .enable_reg = 0x0984, 1429 .enable_mask = BIT(0), 1430 .hw.init = &(struct clk_init_data){ 1431 .name = "gcc_blsp2_qup1_spi_apps_clk", 1432 .parent_names = (const char *[]){ 1433 "blsp2_qup1_spi_apps_clk_src", 1434 }, 1435 .num_parents = 1, 1436 .flags = CLK_SET_RATE_PARENT, 1437 .ops = &clk_branch2_ops, 1438 }, 1439 }, 1440}; 1441 1442static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = { 1443 .halt_reg = 0x0a08, 1444 .clkr = { 1445 .enable_reg = 0x0a08, 1446 .enable_mask = BIT(0), 1447 .hw.init = &(struct clk_init_data){ 1448 .name = "gcc_blsp2_qup2_i2c_apps_clk", 1449 .parent_names = (const char *[]){ 1450 "blsp2_qup2_i2c_apps_clk_src", 1451 }, 1452 .num_parents = 1, 1453 .flags = CLK_SET_RATE_PARENT, 1454 .ops = &clk_branch2_ops, 1455 }, 1456 }, 1457}; 1458 1459static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = { 1460 .halt_reg = 0x0a04, 1461 .clkr = { 1462 .enable_reg = 0x0a04, 1463 .enable_mask = BIT(0), 1464 .hw.init = &(struct clk_init_data){ 1465 .name = "gcc_blsp2_qup2_spi_apps_clk", 1466 .parent_names = (const char *[]){ 1467 "blsp2_qup2_spi_apps_clk_src", 1468 }, 1469 .num_parents = 1, 1470 .flags = CLK_SET_RATE_PARENT, 1471 .ops = &clk_branch2_ops, 1472 }, 1473 }, 1474}; 1475 1476static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = { 1477 .halt_reg = 0x0a88, 1478 .clkr = { 1479 .enable_reg = 0x0a88, 1480 .enable_mask = BIT(0), 1481 .hw.init = &(struct clk_init_data){ 1482 .name = "gcc_blsp2_qup3_i2c_apps_clk", 1483 .parent_names = (const char *[]){ 1484 "blsp2_qup3_i2c_apps_clk_src", 1485 }, 1486 .num_parents = 1, 1487 .flags = CLK_SET_RATE_PARENT, 1488 .ops = &clk_branch2_ops, 1489 }, 1490 }, 1491}; 1492 1493static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = { 1494 .halt_reg = 0x0a84, 1495 .clkr = { 1496 .enable_reg = 0x0a84, 1497 .enable_mask = BIT(0), 1498 .hw.init = &(struct clk_init_data){ 1499 .name = "gcc_blsp2_qup3_spi_apps_clk", 1500 .parent_names = (const char *[]){ 1501 "blsp2_qup3_spi_apps_clk_src", 1502 }, 1503 .num_parents = 1, 1504 .flags = CLK_SET_RATE_PARENT, 1505 .ops = &clk_branch2_ops, 1506 }, 1507 }, 1508}; 1509 1510static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = { 1511 .halt_reg = 0x0b08, 1512 .clkr = { 1513 .enable_reg = 0x0b08, 1514 .enable_mask = BIT(0), 1515 .hw.init = &(struct clk_init_data){ 1516 .name = "gcc_blsp2_qup4_i2c_apps_clk", 1517 .parent_names = (const char *[]){ 1518 "blsp2_qup4_i2c_apps_clk_src", 1519 }, 1520 .num_parents = 1, 1521 .flags = CLK_SET_RATE_PARENT, 1522 .ops = &clk_branch2_ops, 1523 }, 1524 }, 1525}; 1526 1527static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = { 1528 .halt_reg = 0x0b04, 1529 .clkr = { 1530 .enable_reg = 0x0b04, 1531 .enable_mask = BIT(0), 1532 .hw.init = &(struct clk_init_data){ 1533 .name = "gcc_blsp2_qup4_spi_apps_clk", 1534 .parent_names = (const char *[]){ 1535 "blsp2_qup4_spi_apps_clk_src", 1536 }, 1537 .num_parents = 1, 1538 .flags = CLK_SET_RATE_PARENT, 1539 .ops = &clk_branch2_ops, 1540 }, 1541 }, 1542}; 1543 1544static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = { 1545 .halt_reg = 0x0b88, 1546 .clkr = { 1547 .enable_reg = 0x0b88, 1548 .enable_mask = BIT(0), 1549 .hw.init = &(struct clk_init_data){ 1550 .name = "gcc_blsp2_qup5_i2c_apps_clk", 1551 .parent_names = (const char *[]){ 1552 "blsp2_qup5_i2c_apps_clk_src", 1553 }, 1554 .num_parents = 1, 1555 .flags = CLK_SET_RATE_PARENT, 1556 .ops = &clk_branch2_ops, 1557 }, 1558 }, 1559}; 1560 1561static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = { 1562 .halt_reg = 0x0b84, 1563 .clkr = { 1564 .enable_reg = 0x0b84, 1565 .enable_mask = BIT(0), 1566 .hw.init = &(struct clk_init_data){ 1567 .name = "gcc_blsp2_qup5_spi_apps_clk", 1568 .parent_names = (const char *[]){ 1569 "blsp2_qup5_spi_apps_clk_src", 1570 }, 1571 .num_parents = 1, 1572 .flags = CLK_SET_RATE_PARENT, 1573 .ops = &clk_branch2_ops, 1574 }, 1575 }, 1576}; 1577 1578static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = { 1579 .halt_reg = 0x0c08, 1580 .clkr = { 1581 .enable_reg = 0x0c08, 1582 .enable_mask = BIT(0), 1583 .hw.init = &(struct clk_init_data){ 1584 .name = "gcc_blsp2_qup6_i2c_apps_clk", 1585 .parent_names = (const char *[]){ 1586 "blsp2_qup6_i2c_apps_clk_src", 1587 }, 1588 .num_parents = 1, 1589 .flags = CLK_SET_RATE_PARENT, 1590 .ops = &clk_branch2_ops, 1591 }, 1592 }, 1593}; 1594 1595static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = { 1596 .halt_reg = 0x0c04, 1597 .clkr = { 1598 .enable_reg = 0x0c04, 1599 .enable_mask = BIT(0), 1600 .hw.init = &(struct clk_init_data){ 1601 .name = "gcc_blsp2_qup6_spi_apps_clk", 1602 .parent_names = (const char *[]){ 1603 "blsp2_qup6_spi_apps_clk_src", 1604 }, 1605 .num_parents = 1, 1606 .flags = CLK_SET_RATE_PARENT, 1607 .ops = &clk_branch2_ops, 1608 }, 1609 }, 1610}; 1611 1612static struct clk_branch gcc_blsp2_uart1_apps_clk = { 1613 .halt_reg = 0x09c4, 1614 .clkr = { 1615 .enable_reg = 0x09c4, 1616 .enable_mask = BIT(0), 1617 .hw.init = &(struct clk_init_data){ 1618 .name = "gcc_blsp2_uart1_apps_clk", 1619 .parent_names = (const char *[]){ 1620 "blsp2_uart1_apps_clk_src", 1621 }, 1622 .num_parents = 1, 1623 .flags = CLK_SET_RATE_PARENT, 1624 .ops = &clk_branch2_ops, 1625 }, 1626 }, 1627}; 1628 1629static struct clk_branch gcc_blsp2_uart2_apps_clk = { 1630 .halt_reg = 0x0a44, 1631 .clkr = { 1632 .enable_reg = 0x0a44, 1633 .enable_mask = BIT(0), 1634 .hw.init = &(struct clk_init_data){ 1635 .name = "gcc_blsp2_uart2_apps_clk", 1636 .parent_names = (const char *[]){ 1637 "blsp2_uart2_apps_clk_src", 1638 }, 1639 .num_parents = 1, 1640 .flags = CLK_SET_RATE_PARENT, 1641 .ops = &clk_branch2_ops, 1642 }, 1643 }, 1644}; 1645 1646static struct clk_branch gcc_blsp2_uart3_apps_clk = { 1647 .halt_reg = 0x0ac4, 1648 .clkr = { 1649 .enable_reg = 0x0ac4, 1650 .enable_mask = BIT(0), 1651 .hw.init = &(struct clk_init_data){ 1652 .name = "gcc_blsp2_uart3_apps_clk", 1653 .parent_names = (const char *[]){ 1654 "blsp2_uart3_apps_clk_src", 1655 }, 1656 .num_parents = 1, 1657 .flags = CLK_SET_RATE_PARENT, 1658 .ops = &clk_branch2_ops, 1659 }, 1660 }, 1661}; 1662 1663static struct clk_branch gcc_blsp2_uart4_apps_clk = { 1664 .halt_reg = 0x0b44, 1665 .clkr = { 1666 .enable_reg = 0x0b44, 1667 .enable_mask = BIT(0), 1668 .hw.init = &(struct clk_init_data){ 1669 .name = "gcc_blsp2_uart4_apps_clk", 1670 .parent_names = (const char *[]){ 1671 "blsp2_uart4_apps_clk_src", 1672 }, 1673 .num_parents = 1, 1674 .flags = CLK_SET_RATE_PARENT, 1675 .ops = &clk_branch2_ops, 1676 }, 1677 }, 1678}; 1679 1680static struct clk_branch gcc_blsp2_uart5_apps_clk = { 1681 .halt_reg = 0x0bc4, 1682 .clkr = { 1683 .enable_reg = 0x0bc4, 1684 .enable_mask = BIT(0), 1685 .hw.init = &(struct clk_init_data){ 1686 .name = "gcc_blsp2_uart5_apps_clk", 1687 .parent_names = (const char *[]){ 1688 "blsp2_uart5_apps_clk_src", 1689 }, 1690 .num_parents = 1, 1691 .flags = CLK_SET_RATE_PARENT, 1692 .ops = &clk_branch2_ops, 1693 }, 1694 }, 1695}; 1696 1697static struct clk_branch gcc_blsp2_uart6_apps_clk = { 1698 .halt_reg = 0x0c44, 1699 .clkr = { 1700 .enable_reg = 0x0c44, 1701 .enable_mask = BIT(0), 1702 .hw.init = &(struct clk_init_data){ 1703 .name = "gcc_blsp2_uart6_apps_clk", 1704 .parent_names = (const char *[]){ 1705 "blsp2_uart6_apps_clk_src", 1706 }, 1707 .num_parents = 1, 1708 .flags = CLK_SET_RATE_PARENT, 1709 .ops = &clk_branch2_ops, 1710 }, 1711 }, 1712}; 1713 1714static struct clk_branch gcc_boot_rom_ahb_clk = { 1715 .halt_reg = 0x0e04, 1716 .halt_check = BRANCH_HALT_VOTED, 1717 .clkr = { 1718 .enable_reg = 0x1484, 1719 .enable_mask = BIT(10), 1720 .hw.init = &(struct clk_init_data){ 1721 .name = "gcc_boot_rom_ahb_clk", 1722 .parent_names = (const char *[]){ 1723 "config_noc_clk_src", 1724 }, 1725 .num_parents = 1, 1726 .ops = &clk_branch2_ops, 1727 }, 1728 }, 1729}; 1730 1731static struct clk_branch gcc_ce1_ahb_clk = { 1732 .halt_reg = 0x104c, 1733 .halt_check = BRANCH_HALT_VOTED, 1734 .clkr = { 1735 .enable_reg = 0x1484, 1736 .enable_mask = BIT(3), 1737 .hw.init = &(struct clk_init_data){ 1738 .name = "gcc_ce1_ahb_clk", 1739 .parent_names = (const char *[]){ 1740 "config_noc_clk_src", 1741 }, 1742 .num_parents = 1, 1743 .ops = &clk_branch2_ops, 1744 }, 1745 }, 1746}; 1747 1748static struct clk_branch gcc_ce1_axi_clk = { 1749 .halt_reg = 0x1048, 1750 .halt_check = BRANCH_HALT_VOTED, 1751 .clkr = { 1752 .enable_reg = 0x1484, 1753 .enable_mask = BIT(4), 1754 .hw.init = &(struct clk_init_data){ 1755 .name = "gcc_ce1_axi_clk", 1756 .parent_names = (const char *[]){ 1757 "system_noc_clk_src", 1758 }, 1759 .num_parents = 1, 1760 .ops = &clk_branch2_ops, 1761 }, 1762 }, 1763}; 1764 1765static struct clk_branch gcc_ce1_clk = { 1766 .halt_reg = 0x1050, 1767 .halt_check = BRANCH_HALT_VOTED, 1768 .clkr = { 1769 .enable_reg = 0x1484, 1770 .enable_mask = BIT(5), 1771 .hw.init = &(struct clk_init_data){ 1772 .name = "gcc_ce1_clk", 1773 .parent_names = (const char *[]){ 1774 "ce1_clk_src", 1775 }, 1776 .num_parents = 1, 1777 .flags = CLK_SET_RATE_PARENT, 1778 .ops = &clk_branch2_ops, 1779 }, 1780 }, 1781}; 1782 1783static struct clk_branch gcc_ce2_ahb_clk = { 1784 .halt_reg = 0x108c, 1785 .halt_check = BRANCH_HALT_VOTED, 1786 .clkr = { 1787 .enable_reg = 0x1484, 1788 .enable_mask = BIT(0), 1789 .hw.init = &(struct clk_init_data){ 1790 .name = "gcc_ce2_ahb_clk", 1791 .parent_names = (const char *[]){ 1792 "config_noc_clk_src", 1793 }, 1794 .num_parents = 1, 1795 .ops = &clk_branch2_ops, 1796 }, 1797 }, 1798}; 1799 1800static struct clk_branch gcc_ce2_axi_clk = { 1801 .halt_reg = 0x1088, 1802 .halt_check = BRANCH_HALT_VOTED, 1803 .clkr = { 1804 .enable_reg = 0x1484, 1805 .enable_mask = BIT(1), 1806 .hw.init = &(struct clk_init_data){ 1807 .name = "gcc_ce2_axi_clk", 1808 .parent_names = (const char *[]){ 1809 "system_noc_clk_src", 1810 }, 1811 .num_parents = 1, 1812 .ops = &clk_branch2_ops, 1813 }, 1814 }, 1815}; 1816 1817static struct clk_branch gcc_ce2_clk = { 1818 .halt_reg = 0x1090, 1819 .halt_check = BRANCH_HALT_VOTED, 1820 .clkr = { 1821 .enable_reg = 0x1484, 1822 .enable_mask = BIT(2), 1823 .hw.init = &(struct clk_init_data){ 1824 .name = "gcc_ce2_clk", 1825 .parent_names = (const char *[]){ 1826 "ce2_clk_src", 1827 }, 1828 .num_parents = 1, 1829 .flags = CLK_SET_RATE_PARENT, 1830 .ops = &clk_branch2_ops, 1831 }, 1832 }, 1833}; 1834 1835static struct clk_branch gcc_gp1_clk = { 1836 .halt_reg = 0x1900, 1837 .clkr = { 1838 .enable_reg = 0x1900, 1839 .enable_mask = BIT(0), 1840 .hw.init = &(struct clk_init_data){ 1841 .name = "gcc_gp1_clk", 1842 .parent_names = (const char *[]){ 1843 "gp1_clk_src", 1844 }, 1845 .num_parents = 1, 1846 .flags = CLK_SET_RATE_PARENT, 1847 .ops = &clk_branch2_ops, 1848 }, 1849 }, 1850}; 1851 1852static struct clk_branch gcc_gp2_clk = { 1853 .halt_reg = 0x1940, 1854 .clkr = { 1855 .enable_reg = 0x1940, 1856 .enable_mask = BIT(0), 1857 .hw.init = &(struct clk_init_data){ 1858 .name = "gcc_gp2_clk", 1859 .parent_names = (const char *[]){ 1860 "gp2_clk_src", 1861 }, 1862 .num_parents = 1, 1863 .flags = CLK_SET_RATE_PARENT, 1864 .ops = &clk_branch2_ops, 1865 }, 1866 }, 1867}; 1868 1869static struct clk_branch gcc_gp3_clk = { 1870 .halt_reg = 0x1980, 1871 .clkr = { 1872 .enable_reg = 0x1980, 1873 .enable_mask = BIT(0), 1874 .hw.init = &(struct clk_init_data){ 1875 .name = "gcc_gp3_clk", 1876 .parent_names = (const char *[]){ 1877 "gp3_clk_src", 1878 }, 1879 .num_parents = 1, 1880 .flags = CLK_SET_RATE_PARENT, 1881 .ops = &clk_branch2_ops, 1882 }, 1883 }, 1884}; 1885 1886static struct clk_branch gcc_lpass_q6_axi_clk = { 1887 .halt_reg = 0x11c0, 1888 .clkr = { 1889 .enable_reg = 0x11c0, 1890 .enable_mask = BIT(0), 1891 .hw.init = &(struct clk_init_data){ 1892 .name = "gcc_lpass_q6_axi_clk", 1893 .parent_names = (const char *[]){ 1894 "system_noc_clk_src", 1895 }, 1896 .num_parents = 1, 1897 .ops = &clk_branch2_ops, 1898 }, 1899 }, 1900}; 1901 1902static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = { 1903 .halt_reg = 0x024c, 1904 .clkr = { 1905 .enable_reg = 0x024c, 1906 .enable_mask = BIT(0), 1907 .hw.init = &(struct clk_init_data){ 1908 .name = "gcc_mmss_noc_cfg_ahb_clk", 1909 .parent_names = (const char *[]){ 1910 "config_noc_clk_src", 1911 }, 1912 .num_parents = 1, 1913 .ops = &clk_branch2_ops, 1914 .flags = CLK_IGNORE_UNUSED, 1915 }, 1916 }, 1917}; 1918 1919static struct clk_branch gcc_ocmem_noc_cfg_ahb_clk = { 1920 .halt_reg = 0x0248, 1921 .clkr = { 1922 .enable_reg = 0x0248, 1923 .enable_mask = BIT(0), 1924 .hw.init = &(struct clk_init_data){ 1925 .name = "gcc_ocmem_noc_cfg_ahb_clk", 1926 .parent_names = (const char *[]){ 1927 "config_noc_clk_src", 1928 }, 1929 .num_parents = 1, 1930 .ops = &clk_branch2_ops, 1931 }, 1932 }, 1933}; 1934 1935static struct clk_branch gcc_mss_cfg_ahb_clk = { 1936 .halt_reg = 0x0280, 1937 .clkr = { 1938 .enable_reg = 0x0280, 1939 .enable_mask = BIT(0), 1940 .hw.init = &(struct clk_init_data){ 1941 .name = "gcc_mss_cfg_ahb_clk", 1942 .parent_names = (const char *[]){ 1943 "config_noc_clk_src", 1944 }, 1945 .num_parents = 1, 1946 .ops = &clk_branch2_ops, 1947 }, 1948 }, 1949}; 1950 1951static struct clk_branch gcc_mss_q6_bimc_axi_clk = { 1952 .halt_reg = 0x0284, 1953 .clkr = { 1954 .enable_reg = 0x0284, 1955 .enable_mask = BIT(0), 1956 .hw.init = &(struct clk_init_data){ 1957 .name = "gcc_mss_q6_bimc_axi_clk", 1958 .ops = &clk_branch2_ops, 1959 }, 1960 }, 1961}; 1962 1963static struct clk_branch gcc_pdm2_clk = { 1964 .halt_reg = 0x0ccc, 1965 .clkr = { 1966 .enable_reg = 0x0ccc, 1967 .enable_mask = BIT(0), 1968 .hw.init = &(struct clk_init_data){ 1969 .name = "gcc_pdm2_clk", 1970 .parent_names = (const char *[]){ 1971 "pdm2_clk_src", 1972 }, 1973 .num_parents = 1, 1974 .flags = CLK_SET_RATE_PARENT, 1975 .ops = &clk_branch2_ops, 1976 }, 1977 }, 1978}; 1979 1980static struct clk_branch gcc_pdm_ahb_clk = { 1981 .halt_reg = 0x0cc4, 1982 .clkr = { 1983 .enable_reg = 0x0cc4, 1984 .enable_mask = BIT(0), 1985 .hw.init = &(struct clk_init_data){ 1986 .name = "gcc_pdm_ahb_clk", 1987 .parent_names = (const char *[]){ 1988 "periph_noc_clk_src", 1989 }, 1990 .num_parents = 1, 1991 .ops = &clk_branch2_ops, 1992 }, 1993 }, 1994}; 1995 1996static struct clk_branch gcc_prng_ahb_clk = { 1997 .halt_reg = 0x0d04, 1998 .halt_check = BRANCH_HALT_VOTED, 1999 .clkr = { 2000 .enable_reg = 0x1484, 2001 .enable_mask = BIT(13), 2002 .hw.init = &(struct clk_init_data){ 2003 .name = "gcc_prng_ahb_clk", 2004 .parent_names = (const char *[]){ 2005 "periph_noc_clk_src", 2006 }, 2007 .num_parents = 1, 2008 .ops = &clk_branch2_ops, 2009 }, 2010 }, 2011}; 2012 2013static struct clk_branch gcc_sdcc1_ahb_clk = { 2014 .halt_reg = 0x04c8, 2015 .clkr = { 2016 .enable_reg = 0x04c8, 2017 .enable_mask = BIT(0), 2018 .hw.init = &(struct clk_init_data){ 2019 .name = "gcc_sdcc1_ahb_clk", 2020 .parent_names = (const char *[]){ 2021 "periph_noc_clk_src", 2022 }, 2023 .num_parents = 1, 2024 .ops = &clk_branch2_ops, 2025 }, 2026 }, 2027}; 2028 2029static struct clk_branch gcc_sdcc1_apps_clk = { 2030 .halt_reg = 0x04c4, 2031 .clkr = { 2032 .enable_reg = 0x04c4, 2033 .enable_mask = BIT(0), 2034 .hw.init = &(struct clk_init_data){ 2035 .name = "gcc_sdcc1_apps_clk", 2036 .parent_names = (const char *[]){ 2037 "sdcc1_apps_clk_src", 2038 }, 2039 .num_parents = 1, 2040 .flags = CLK_SET_RATE_PARENT, 2041 .ops = &clk_branch2_ops, 2042 }, 2043 }, 2044}; 2045 2046static struct clk_branch gcc_sdcc1_cdccal_ff_clk = { 2047 .halt_reg = 0x04e8, 2048 .clkr = { 2049 .enable_reg = 0x04e8, 2050 .enable_mask = BIT(0), 2051 .hw.init = &(struct clk_init_data){ 2052 .name = "gcc_sdcc1_cdccal_ff_clk", 2053 .parent_names = (const char *[]){ 2054 "xo" 2055 }, 2056 .num_parents = 1, 2057 .ops = &clk_branch2_ops, 2058 }, 2059 }, 2060}; 2061 2062static struct clk_branch gcc_sdcc1_cdccal_sleep_clk = { 2063 .halt_reg = 0x04e4, 2064 .clkr = { 2065 .enable_reg = 0x04e4, 2066 .enable_mask = BIT(0), 2067 .hw.init = &(struct clk_init_data){ 2068 .name = "gcc_sdcc1_cdccal_sleep_clk", 2069 .parent_names = (const char *[]){ 2070 "sleep_clk_src" 2071 }, 2072 .num_parents = 1, 2073 .ops = &clk_branch2_ops, 2074 }, 2075 }, 2076}; 2077 2078static struct clk_branch gcc_sdcc2_ahb_clk = { 2079 .halt_reg = 0x0508, 2080 .clkr = { 2081 .enable_reg = 0x0508, 2082 .enable_mask = BIT(0), 2083 .hw.init = &(struct clk_init_data){ 2084 .name = "gcc_sdcc2_ahb_clk", 2085 .parent_names = (const char *[]){ 2086 "periph_noc_clk_src", 2087 }, 2088 .num_parents = 1, 2089 .ops = &clk_branch2_ops, 2090 }, 2091 }, 2092}; 2093 2094static struct clk_branch gcc_sdcc2_apps_clk = { 2095 .halt_reg = 0x0504, 2096 .clkr = { 2097 .enable_reg = 0x0504, 2098 .enable_mask = BIT(0), 2099 .hw.init = &(struct clk_init_data){ 2100 .name = "gcc_sdcc2_apps_clk", 2101 .parent_names = (const char *[]){ 2102 "sdcc2_apps_clk_src", 2103 }, 2104 .num_parents = 1, 2105 .flags = CLK_SET_RATE_PARENT, 2106 .ops = &clk_branch2_ops, 2107 }, 2108 }, 2109}; 2110 2111static struct clk_branch gcc_sdcc3_ahb_clk = { 2112 .halt_reg = 0x0548, 2113 .clkr = { 2114 .enable_reg = 0x0548, 2115 .enable_mask = BIT(0), 2116 .hw.init = &(struct clk_init_data){ 2117 .name = "gcc_sdcc3_ahb_clk", 2118 .parent_names = (const char *[]){ 2119 "periph_noc_clk_src", 2120 }, 2121 .num_parents = 1, 2122 .ops = &clk_branch2_ops, 2123 }, 2124 }, 2125}; 2126 2127static struct clk_branch gcc_sdcc3_apps_clk = { 2128 .halt_reg = 0x0544, 2129 .clkr = { 2130 .enable_reg = 0x0544, 2131 .enable_mask = BIT(0), 2132 .hw.init = &(struct clk_init_data){ 2133 .name = "gcc_sdcc3_apps_clk", 2134 .parent_names = (const char *[]){ 2135 "sdcc3_apps_clk_src", 2136 }, 2137 .num_parents = 1, 2138 .flags = CLK_SET_RATE_PARENT, 2139 .ops = &clk_branch2_ops, 2140 }, 2141 }, 2142}; 2143 2144static struct clk_branch gcc_sdcc4_ahb_clk = { 2145 .halt_reg = 0x0588, 2146 .clkr = { 2147 .enable_reg = 0x0588, 2148 .enable_mask = BIT(0), 2149 .hw.init = &(struct clk_init_data){ 2150 .name = "gcc_sdcc4_ahb_clk", 2151 .parent_names = (const char *[]){ 2152 "periph_noc_clk_src", 2153 }, 2154 .num_parents = 1, 2155 .ops = &clk_branch2_ops, 2156 }, 2157 }, 2158}; 2159 2160static struct clk_branch gcc_sdcc4_apps_clk = { 2161 .halt_reg = 0x0584, 2162 .clkr = { 2163 .enable_reg = 0x0584, 2164 .enable_mask = BIT(0), 2165 .hw.init = &(struct clk_init_data){ 2166 .name = "gcc_sdcc4_apps_clk", 2167 .parent_names = (const char *[]){ 2168 "sdcc4_apps_clk_src", 2169 }, 2170 .num_parents = 1, 2171 .flags = CLK_SET_RATE_PARENT, 2172 .ops = &clk_branch2_ops, 2173 }, 2174 }, 2175}; 2176 2177static struct clk_branch gcc_sys_noc_usb3_axi_clk = { 2178 .halt_reg = 0x0108, 2179 .clkr = { 2180 .enable_reg = 0x0108, 2181 .enable_mask = BIT(0), 2182 .hw.init = &(struct clk_init_data){ 2183 .name = "gcc_sys_noc_usb3_axi_clk", 2184 .parent_names = (const char *[]){ 2185 "usb30_master_clk_src", 2186 }, 2187 .num_parents = 1, 2188 .flags = CLK_SET_RATE_PARENT, 2189 .ops = &clk_branch2_ops, 2190 }, 2191 }, 2192}; 2193 2194static struct clk_branch gcc_tsif_ahb_clk = { 2195 .halt_reg = 0x0d84, 2196 .clkr = { 2197 .enable_reg = 0x0d84, 2198 .enable_mask = BIT(0), 2199 .hw.init = &(struct clk_init_data){ 2200 .name = "gcc_tsif_ahb_clk", 2201 .parent_names = (const char *[]){ 2202 "periph_noc_clk_src", 2203 }, 2204 .num_parents = 1, 2205 .ops = &clk_branch2_ops, 2206 }, 2207 }, 2208}; 2209 2210static struct clk_branch gcc_tsif_ref_clk = { 2211 .halt_reg = 0x0d88, 2212 .clkr = { 2213 .enable_reg = 0x0d88, 2214 .enable_mask = BIT(0), 2215 .hw.init = &(struct clk_init_data){ 2216 .name = "gcc_tsif_ref_clk", 2217 .parent_names = (const char *[]){ 2218 "tsif_ref_clk_src", 2219 }, 2220 .num_parents = 1, 2221 .flags = CLK_SET_RATE_PARENT, 2222 .ops = &clk_branch2_ops, 2223 }, 2224 }, 2225}; 2226 2227static struct clk_branch gcc_usb2a_phy_sleep_clk = { 2228 .halt_reg = 0x04ac, 2229 .clkr = { 2230 .enable_reg = 0x04ac, 2231 .enable_mask = BIT(0), 2232 .hw.init = &(struct clk_init_data){ 2233 .name = "gcc_usb2a_phy_sleep_clk", 2234 .parent_names = (const char *[]){ 2235 "sleep_clk_src", 2236 }, 2237 .num_parents = 1, 2238 .ops = &clk_branch2_ops, 2239 }, 2240 }, 2241}; 2242 2243static struct clk_branch gcc_usb2b_phy_sleep_clk = { 2244 .halt_reg = 0x04b4, 2245 .clkr = { 2246 .enable_reg = 0x04b4, 2247 .enable_mask = BIT(0), 2248 .hw.init = &(struct clk_init_data){ 2249 .name = "gcc_usb2b_phy_sleep_clk", 2250 .parent_names = (const char *[]){ 2251 "sleep_clk_src", 2252 }, 2253 .num_parents = 1, 2254 .ops = &clk_branch2_ops, 2255 }, 2256 }, 2257}; 2258 2259static struct clk_branch gcc_usb30_master_clk = { 2260 .halt_reg = 0x03c8, 2261 .clkr = { 2262 .enable_reg = 0x03c8, 2263 .enable_mask = BIT(0), 2264 .hw.init = &(struct clk_init_data){ 2265 .name = "gcc_usb30_master_clk", 2266 .parent_names = (const char *[]){ 2267 "usb30_master_clk_src", 2268 }, 2269 .num_parents = 1, 2270 .flags = CLK_SET_RATE_PARENT, 2271 .ops = &clk_branch2_ops, 2272 }, 2273 }, 2274}; 2275 2276static struct clk_branch gcc_usb30_mock_utmi_clk = { 2277 .halt_reg = 0x03d0, 2278 .clkr = { 2279 .enable_reg = 0x03d0, 2280 .enable_mask = BIT(0), 2281 .hw.init = &(struct clk_init_data){ 2282 .name = "gcc_usb30_mock_utmi_clk", 2283 .parent_names = (const char *[]){ 2284 "usb30_mock_utmi_clk_src", 2285 }, 2286 .num_parents = 1, 2287 .flags = CLK_SET_RATE_PARENT, 2288 .ops = &clk_branch2_ops, 2289 }, 2290 }, 2291}; 2292 2293static struct clk_branch gcc_usb30_sleep_clk = { 2294 .halt_reg = 0x03cc, 2295 .clkr = { 2296 .enable_reg = 0x03cc, 2297 .enable_mask = BIT(0), 2298 .hw.init = &(struct clk_init_data){ 2299 .name = "gcc_usb30_sleep_clk", 2300 .parent_names = (const char *[]){ 2301 "sleep_clk_src", 2302 }, 2303 .num_parents = 1, 2304 .ops = &clk_branch2_ops, 2305 }, 2306 }, 2307}; 2308 2309static struct clk_branch gcc_usb_hs_ahb_clk = { 2310 .halt_reg = 0x0488, 2311 .clkr = { 2312 .enable_reg = 0x0488, 2313 .enable_mask = BIT(0), 2314 .hw.init = &(struct clk_init_data){ 2315 .name = "gcc_usb_hs_ahb_clk", 2316 .parent_names = (const char *[]){ 2317 "periph_noc_clk_src", 2318 }, 2319 .num_parents = 1, 2320 .ops = &clk_branch2_ops, 2321 }, 2322 }, 2323}; 2324 2325static struct clk_branch gcc_usb_hs_system_clk = { 2326 .halt_reg = 0x0484, 2327 .clkr = { 2328 .enable_reg = 0x0484, 2329 .enable_mask = BIT(0), 2330 .hw.init = &(struct clk_init_data){ 2331 .name = "gcc_usb_hs_system_clk", 2332 .parent_names = (const char *[]){ 2333 "usb_hs_system_clk_src", 2334 }, 2335 .num_parents = 1, 2336 .flags = CLK_SET_RATE_PARENT, 2337 .ops = &clk_branch2_ops, 2338 }, 2339 }, 2340}; 2341 2342static struct clk_branch gcc_usb_hsic_ahb_clk = { 2343 .halt_reg = 0x0408, 2344 .clkr = { 2345 .enable_reg = 0x0408, 2346 .enable_mask = BIT(0), 2347 .hw.init = &(struct clk_init_data){ 2348 .name = "gcc_usb_hsic_ahb_clk", 2349 .parent_names = (const char *[]){ 2350 "periph_noc_clk_src", 2351 }, 2352 .num_parents = 1, 2353 .ops = &clk_branch2_ops, 2354 }, 2355 }, 2356}; 2357 2358static struct clk_branch gcc_usb_hsic_clk = { 2359 .halt_reg = 0x0410, 2360 .clkr = { 2361 .enable_reg = 0x0410, 2362 .enable_mask = BIT(0), 2363 .hw.init = &(struct clk_init_data){ 2364 .name = "gcc_usb_hsic_clk", 2365 .parent_names = (const char *[]){ 2366 "usb_hsic_clk_src", 2367 }, 2368 .num_parents = 1, 2369 .flags = CLK_SET_RATE_PARENT, 2370 .ops = &clk_branch2_ops, 2371 }, 2372 }, 2373}; 2374 2375static struct clk_branch gcc_usb_hsic_io_cal_clk = { 2376 .halt_reg = 0x0414, 2377 .clkr = { 2378 .enable_reg = 0x0414, 2379 .enable_mask = BIT(0), 2380 .hw.init = &(struct clk_init_data){ 2381 .name = "gcc_usb_hsic_io_cal_clk", 2382 .parent_names = (const char *[]){ 2383 "usb_hsic_io_cal_clk_src", 2384 }, 2385 .num_parents = 1, 2386 .flags = CLK_SET_RATE_PARENT, 2387 .ops = &clk_branch2_ops, 2388 }, 2389 }, 2390}; 2391 2392static struct clk_branch gcc_usb_hsic_io_cal_sleep_clk = { 2393 .halt_reg = 0x0418, 2394 .clkr = { 2395 .enable_reg = 0x0418, 2396 .enable_mask = BIT(0), 2397 .hw.init = &(struct clk_init_data){ 2398 .name = "gcc_usb_hsic_io_cal_sleep_clk", 2399 .parent_names = (const char *[]){ 2400 "sleep_clk_src", 2401 }, 2402 .num_parents = 1, 2403 .ops = &clk_branch2_ops, 2404 }, 2405 }, 2406}; 2407 2408static struct clk_branch gcc_usb_hsic_system_clk = { 2409 .halt_reg = 0x040c, 2410 .clkr = { 2411 .enable_reg = 0x040c, 2412 .enable_mask = BIT(0), 2413 .hw.init = &(struct clk_init_data){ 2414 .name = "gcc_usb_hsic_system_clk", 2415 .parent_names = (const char *[]){ 2416 "usb_hsic_system_clk_src", 2417 }, 2418 .num_parents = 1, 2419 .flags = CLK_SET_RATE_PARENT, 2420 .ops = &clk_branch2_ops, 2421 }, 2422 }, 2423}; 2424 2425static struct gdsc usb_hs_hsic_gdsc = { 2426 .gdscr = 0x404, 2427 .pd = { 2428 .name = "usb_hs_hsic", 2429 }, 2430 .pwrsts = PWRSTS_OFF_ON, 2431}; 2432 2433static struct clk_regmap *gcc_msm8974_clocks[] = { 2434 [GPLL0] = &gpll0.clkr, 2435 [GPLL0_VOTE] = &gpll0_vote, 2436 [CONFIG_NOC_CLK_SRC] = &config_noc_clk_src.clkr, 2437 [PERIPH_NOC_CLK_SRC] = &periph_noc_clk_src.clkr, 2438 [SYSTEM_NOC_CLK_SRC] = &system_noc_clk_src.clkr, 2439 [GPLL1] = &gpll1.clkr, 2440 [GPLL1_VOTE] = &gpll1_vote, 2441 [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr, 2442 [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr, 2443 [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr, 2444 [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr, 2445 [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr, 2446 [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr, 2447 [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr, 2448 [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr, 2449 [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr, 2450 [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr, 2451 [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr, 2452 [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr, 2453 [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr, 2454 [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr, 2455 [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr, 2456 [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr, 2457 [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr, 2458 [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr, 2459 [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr, 2460 [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr, 2461 [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr, 2462 [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr, 2463 [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr, 2464 [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr, 2465 [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr, 2466 [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr, 2467 [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr, 2468 [BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr, 2469 [BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr, 2470 [BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr, 2471 [BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr, 2472 [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr, 2473 [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr, 2474 [BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr, 2475 [BLSP2_UART4_APPS_CLK_SRC] = &blsp2_uart4_apps_clk_src.clkr, 2476 [BLSP2_UART5_APPS_CLK_SRC] = &blsp2_uart5_apps_clk_src.clkr, 2477 [BLSP2_UART6_APPS_CLK_SRC] = &blsp2_uart6_apps_clk_src.clkr, 2478 [CE1_CLK_SRC] = &ce1_clk_src.clkr, 2479 [CE2_CLK_SRC] = &ce2_clk_src.clkr, 2480 [GP1_CLK_SRC] = &gp1_clk_src.clkr, 2481 [GP2_CLK_SRC] = &gp2_clk_src.clkr, 2482 [GP3_CLK_SRC] = &gp3_clk_src.clkr, 2483 [PDM2_CLK_SRC] = &pdm2_clk_src.clkr, 2484 [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr, 2485 [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr, 2486 [SDCC3_APPS_CLK_SRC] = &sdcc3_apps_clk_src.clkr, 2487 [SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr, 2488 [TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr, 2489 [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr, 2490 [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr, 2491 [USB_HSIC_CLK_SRC] = &usb_hsic_clk_src.clkr, 2492 [USB_HSIC_IO_CAL_CLK_SRC] = &usb_hsic_io_cal_clk_src.clkr, 2493 [USB_HSIC_SYSTEM_CLK_SRC] = &usb_hsic_system_clk_src.clkr, 2494 [GCC_BAM_DMA_AHB_CLK] = &gcc_bam_dma_ahb_clk.clkr, 2495 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr, 2496 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr, 2497 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr, 2498 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr, 2499 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr, 2500 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr, 2501 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr, 2502 [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr, 2503 [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr, 2504 [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr, 2505 [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr, 2506 [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr, 2507 [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr, 2508 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr, 2509 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr, 2510 [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr, 2511 [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr, 2512 [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr, 2513 [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr, 2514 [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr, 2515 [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr, 2516 [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr, 2517 [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr, 2518 [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr, 2519 [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr, 2520 [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr, 2521 [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr, 2522 [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr, 2523 [GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr, 2524 [GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr, 2525 [GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr, 2526 [GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr, 2527 [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr, 2528 [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr, 2529 [GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr, 2530 [GCC_BLSP2_UART4_APPS_CLK] = &gcc_blsp2_uart4_apps_clk.clkr, 2531 [GCC_BLSP2_UART5_APPS_CLK] = &gcc_blsp2_uart5_apps_clk.clkr, 2532 [GCC_BLSP2_UART6_APPS_CLK] = &gcc_blsp2_uart6_apps_clk.clkr, 2533 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 2534 [GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr, 2535 [GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr, 2536 [GCC_CE1_CLK] = &gcc_ce1_clk.clkr, 2537 [GCC_CE2_AHB_CLK] = &gcc_ce2_ahb_clk.clkr, 2538 [GCC_CE2_AXI_CLK] = &gcc_ce2_axi_clk.clkr, 2539 [GCC_CE2_CLK] = &gcc_ce2_clk.clkr, 2540 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 2541 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 2542 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 2543 [GCC_LPASS_Q6_AXI_CLK] = &gcc_lpass_q6_axi_clk.clkr, 2544 [GCC_MMSS_NOC_CFG_AHB_CLK] = &gcc_mmss_noc_cfg_ahb_clk.clkr, 2545 [GCC_OCMEM_NOC_CFG_AHB_CLK] = &gcc_ocmem_noc_cfg_ahb_clk.clkr, 2546 [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr, 2547 [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr, 2548 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 2549 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 2550 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, 2551 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, 2552 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, 2553 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, 2554 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, 2555 [GCC_SDCC3_AHB_CLK] = &gcc_sdcc3_ahb_clk.clkr, 2556 [GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr, 2557 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr, 2558 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr, 2559 [GCC_SYS_NOC_USB3_AXI_CLK] = &gcc_sys_noc_usb3_axi_clk.clkr, 2560 [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr, 2561 [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr, 2562 [GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr, 2563 [GCC_USB2B_PHY_SLEEP_CLK] = &gcc_usb2b_phy_sleep_clk.clkr, 2564 [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr, 2565 [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr, 2566 [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr, 2567 [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr, 2568 [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr, 2569 [GCC_USB_HSIC_AHB_CLK] = &gcc_usb_hsic_ahb_clk.clkr, 2570 [GCC_USB_HSIC_CLK] = &gcc_usb_hsic_clk.clkr, 2571 [GCC_USB_HSIC_IO_CAL_CLK] = &gcc_usb_hsic_io_cal_clk.clkr, 2572 [GCC_USB_HSIC_IO_CAL_SLEEP_CLK] = &gcc_usb_hsic_io_cal_sleep_clk.clkr, 2573 [GCC_USB_HSIC_SYSTEM_CLK] = &gcc_usb_hsic_system_clk.clkr, 2574 [GCC_MMSS_GPLL0_CLK_SRC] = &gcc_mmss_gpll0_clk_src, 2575 [GPLL4] = NULL, 2576 [GPLL4_VOTE] = NULL, 2577 [GCC_SDCC1_CDCCAL_SLEEP_CLK] = NULL, 2578 [GCC_SDCC1_CDCCAL_FF_CLK] = NULL, 2579}; 2580 2581static const struct qcom_reset_map gcc_msm8974_resets[] = { 2582 [GCC_SYSTEM_NOC_BCR] = { 0x0100 }, 2583 [GCC_CONFIG_NOC_BCR] = { 0x0140 }, 2584 [GCC_PERIPH_NOC_BCR] = { 0x0180 }, 2585 [GCC_IMEM_BCR] = { 0x0200 }, 2586 [GCC_MMSS_BCR] = { 0x0240 }, 2587 [GCC_QDSS_BCR] = { 0x0300 }, 2588 [GCC_USB_30_BCR] = { 0x03c0 }, 2589 [GCC_USB3_PHY_BCR] = { 0x03fc }, 2590 [GCC_USB_HS_HSIC_BCR] = { 0x0400 }, 2591 [GCC_USB_HS_BCR] = { 0x0480 }, 2592 [GCC_USB2A_PHY_BCR] = { 0x04a8 }, 2593 [GCC_USB2B_PHY_BCR] = { 0x04b0 }, 2594 [GCC_SDCC1_BCR] = { 0x04c0 }, 2595 [GCC_SDCC2_BCR] = { 0x0500 }, 2596 [GCC_SDCC3_BCR] = { 0x0540 }, 2597 [GCC_SDCC4_BCR] = { 0x0580 }, 2598 [GCC_BLSP1_BCR] = { 0x05c0 }, 2599 [GCC_BLSP1_QUP1_BCR] = { 0x0640 }, 2600 [GCC_BLSP1_UART1_BCR] = { 0x0680 }, 2601 [GCC_BLSP1_QUP2_BCR] = { 0x06c0 }, 2602 [GCC_BLSP1_UART2_BCR] = { 0x0700 }, 2603 [GCC_BLSP1_QUP3_BCR] = { 0x0740 }, 2604 [GCC_BLSP1_UART3_BCR] = { 0x0780 }, 2605 [GCC_BLSP1_QUP4_BCR] = { 0x07c0 }, 2606 [GCC_BLSP1_UART4_BCR] = { 0x0800 }, 2607 [GCC_BLSP1_QUP5_BCR] = { 0x0840 }, 2608 [GCC_BLSP1_UART5_BCR] = { 0x0880 }, 2609 [GCC_BLSP1_QUP6_BCR] = { 0x08c0 }, 2610 [GCC_BLSP1_UART6_BCR] = { 0x0900 }, 2611 [GCC_BLSP2_BCR] = { 0x0940 }, 2612 [GCC_BLSP2_QUP1_BCR] = { 0x0980 }, 2613 [GCC_BLSP2_UART1_BCR] = { 0x09c0 }, 2614 [GCC_BLSP2_QUP2_BCR] = { 0x0a00 }, 2615 [GCC_BLSP2_UART2_BCR] = { 0x0a40 }, 2616 [GCC_BLSP2_QUP3_BCR] = { 0x0a80 }, 2617 [GCC_BLSP2_UART3_BCR] = { 0x0ac0 }, 2618 [GCC_BLSP2_QUP4_BCR] = { 0x0b00 }, 2619 [GCC_BLSP2_UART4_BCR] = { 0x0b40 }, 2620 [GCC_BLSP2_QUP5_BCR] = { 0x0b80 }, 2621 [GCC_BLSP2_UART5_BCR] = { 0x0bc0 }, 2622 [GCC_BLSP2_QUP6_BCR] = { 0x0c00 }, 2623 [GCC_BLSP2_UART6_BCR] = { 0x0c40 }, 2624 [GCC_PDM_BCR] = { 0x0cc0 }, 2625 [GCC_BAM_DMA_BCR] = { 0x0d40 }, 2626 [GCC_TSIF_BCR] = { 0x0d80 }, 2627 [GCC_TCSR_BCR] = { 0x0dc0 }, 2628 [GCC_BOOT_ROM_BCR] = { 0x0e00 }, 2629 [GCC_MSG_RAM_BCR] = { 0x0e40 }, 2630 [GCC_TLMM_BCR] = { 0x0e80 }, 2631 [GCC_MPM_BCR] = { 0x0ec0 }, 2632 [GCC_SEC_CTRL_BCR] = { 0x0f40 }, 2633 [GCC_SPMI_BCR] = { 0x0fc0 }, 2634 [GCC_SPDM_BCR] = { 0x1000 }, 2635 [GCC_CE1_BCR] = { 0x1040 }, 2636 [GCC_CE2_BCR] = { 0x1080 }, 2637 [GCC_BIMC_BCR] = { 0x1100 }, 2638 [GCC_MPM_NON_AHB_RESET] = { 0x0ec4, 2 }, 2639 [GCC_MPM_AHB_RESET] = { 0x0ec4, 1 }, 2640 [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x1240 }, 2641 [GCC_SNOC_BUS_TIMEOUT2_BCR] = { 0x1248 }, 2642 [GCC_PNOC_BUS_TIMEOUT0_BCR] = { 0x1280 }, 2643 [GCC_PNOC_BUS_TIMEOUT1_BCR] = { 0x1288 }, 2644 [GCC_PNOC_BUS_TIMEOUT2_BCR] = { 0x1290 }, 2645 [GCC_PNOC_BUS_TIMEOUT3_BCR] = { 0x1298 }, 2646 [GCC_PNOC_BUS_TIMEOUT4_BCR] = { 0x12a0 }, 2647 [GCC_CNOC_BUS_TIMEOUT0_BCR] = { 0x12c0 }, 2648 [GCC_CNOC_BUS_TIMEOUT1_BCR] = { 0x12c8 }, 2649 [GCC_CNOC_BUS_TIMEOUT2_BCR] = { 0x12d0 }, 2650 [GCC_CNOC_BUS_TIMEOUT3_BCR] = { 0x12d8 }, 2651 [GCC_CNOC_BUS_TIMEOUT4_BCR] = { 0x12e0 }, 2652 [GCC_CNOC_BUS_TIMEOUT5_BCR] = { 0x12e8 }, 2653 [GCC_CNOC_BUS_TIMEOUT6_BCR] = { 0x12f0 }, 2654 [GCC_DEHR_BCR] = { 0x1300 }, 2655 [GCC_RBCPR_BCR] = { 0x1380 }, 2656 [GCC_MSS_RESTART] = { 0x1680 }, 2657 [GCC_LPASS_RESTART] = { 0x16c0 }, 2658 [GCC_WCSS_RESTART] = { 0x1700 }, 2659 [GCC_VENUS_RESTART] = { 0x1740 }, 2660}; 2661 2662static struct gdsc *gcc_msm8974_gdscs[] = { 2663 [USB_HS_HSIC_GDSC] = &usb_hs_hsic_gdsc, 2664}; 2665 2666static const struct regmap_config gcc_msm8974_regmap_config = { 2667 .reg_bits = 32, 2668 .reg_stride = 4, 2669 .val_bits = 32, 2670 .max_register = 0x1fc0, 2671 .fast_io = true, 2672}; 2673 2674static const struct qcom_cc_desc gcc_msm8974_desc = { 2675 .config = &gcc_msm8974_regmap_config, 2676 .clks = gcc_msm8974_clocks, 2677 .num_clks = ARRAY_SIZE(gcc_msm8974_clocks), 2678 .resets = gcc_msm8974_resets, 2679 .num_resets = ARRAY_SIZE(gcc_msm8974_resets), 2680 .gdscs = gcc_msm8974_gdscs, 2681 .num_gdscs = ARRAY_SIZE(gcc_msm8974_gdscs), 2682}; 2683 2684static const struct of_device_id gcc_msm8974_match_table[] = { 2685 { .compatible = "qcom,gcc-msm8974" }, 2686 { .compatible = "qcom,gcc-msm8974pro" , .data = (void *)1UL }, 2687 { .compatible = "qcom,gcc-msm8974pro-ac", .data = (void *)1UL }, 2688 { } 2689}; 2690MODULE_DEVICE_TABLE(of, gcc_msm8974_match_table); 2691 2692static void msm8974_pro_clock_override(void) 2693{ 2694 sdcc1_apps_clk_src_init.parent_names = gcc_xo_gpll0_gpll4; 2695 sdcc1_apps_clk_src_init.num_parents = 3; 2696 sdcc1_apps_clk_src.freq_tbl = ftbl_gcc_sdcc1_apps_clk_pro; 2697 sdcc1_apps_clk_src.parent_map = gcc_xo_gpll0_gpll4_map; 2698 2699 gcc_msm8974_clocks[GPLL4] = &gpll4.clkr; 2700 gcc_msm8974_clocks[GPLL4_VOTE] = &gpll4_vote; 2701 gcc_msm8974_clocks[GCC_SDCC1_CDCCAL_SLEEP_CLK] = 2702 &gcc_sdcc1_cdccal_sleep_clk.clkr; 2703 gcc_msm8974_clocks[GCC_SDCC1_CDCCAL_FF_CLK] = 2704 &gcc_sdcc1_cdccal_ff_clk.clkr; 2705} 2706 2707static int gcc_msm8974_probe(struct platform_device *pdev) 2708{ 2709 int ret; 2710 struct device *dev = &pdev->dev; 2711 bool pro; 2712 const struct of_device_id *id; 2713 2714 id = of_match_device(gcc_msm8974_match_table, dev); 2715 if (!id) 2716 return -ENODEV; 2717 pro = !!(id->data); 2718 2719 if (pro) 2720 msm8974_pro_clock_override(); 2721 2722 ret = qcom_cc_register_board_clk(dev, "xo_board", "xo", 19200000); 2723 if (ret) 2724 return ret; 2725 2726 ret = qcom_cc_register_sleep_clk(dev); 2727 if (ret) 2728 return ret; 2729 2730 return qcom_cc_probe(pdev, &gcc_msm8974_desc); 2731} 2732 2733static struct platform_driver gcc_msm8974_driver = { 2734 .probe = gcc_msm8974_probe, 2735 .driver = { 2736 .name = "gcc-msm8974", 2737 .of_match_table = gcc_msm8974_match_table, 2738 }, 2739}; 2740 2741static int __init gcc_msm8974_init(void) 2742{ 2743 return platform_driver_register(&gcc_msm8974_driver); 2744} 2745core_initcall(gcc_msm8974_init); 2746 2747static void __exit gcc_msm8974_exit(void) 2748{ 2749 platform_driver_unregister(&gcc_msm8974_driver); 2750} 2751module_exit(gcc_msm8974_exit); 2752 2753MODULE_DESCRIPTION("QCOM GCC MSM8974 Driver"); 2754MODULE_LICENSE("GPL v2"); 2755MODULE_ALIAS("platform:gcc-msm8974"); 2756