1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2014, The Linux Foundation. All rights reserved. 4 */ 5 6#include <linux/kernel.h> 7#include <linux/bitops.h> 8#include <linux/err.h> 9#include <linux/platform_device.h> 10#include <linux/module.h> 11#include <linux/of.h> 12#include <linux/of_device.h> 13#include <linux/clk-provider.h> 14#include <linux/regmap.h> 15#include <linux/reset-controller.h> 16 17#include <dt-bindings/clock/qcom,gcc-ipq806x.h> 18#include <dt-bindings/reset/qcom,gcc-ipq806x.h> 19 20#include "common.h" 21#include "clk-regmap.h" 22#include "clk-pll.h" 23#include "clk-rcg.h" 24#include "clk-branch.h" 25#include "clk-hfpll.h" 26#include "reset.h" 27 28static struct clk_pll pll0 = { 29 .l_reg = 0x30c4, 30 .m_reg = 0x30c8, 31 .n_reg = 0x30cc, 32 .config_reg = 0x30d4, 33 .mode_reg = 0x30c0, 34 .status_reg = 0x30d8, 35 .status_bit = 16, 36 .clkr.hw.init = &(struct clk_init_data){ 37 .name = "pll0", 38 .parent_names = (const char *[]){ "pxo" }, 39 .num_parents = 1, 40 .ops = &clk_pll_ops, 41 }, 42}; 43 44static struct clk_regmap pll0_vote = { 45 .enable_reg = 0x34c0, 46 .enable_mask = BIT(0), 47 .hw.init = &(struct clk_init_data){ 48 .name = "pll0_vote", 49 .parent_names = (const char *[]){ "pll0" }, 50 .num_parents = 1, 51 .ops = &clk_pll_vote_ops, 52 }, 53}; 54 55static struct clk_pll pll3 = { 56 .l_reg = 0x3164, 57 .m_reg = 0x3168, 58 .n_reg = 0x316c, 59 .config_reg = 0x3174, 60 .mode_reg = 0x3160, 61 .status_reg = 0x3178, 62 .status_bit = 16, 63 .clkr.hw.init = &(struct clk_init_data){ 64 .name = "pll3", 65 .parent_names = (const char *[]){ "pxo" }, 66 .num_parents = 1, 67 .ops = &clk_pll_ops, 68 }, 69}; 70 71static struct clk_regmap pll4_vote = { 72 .enable_reg = 0x34c0, 73 .enable_mask = BIT(4), 74 .hw.init = &(struct clk_init_data){ 75 .name = "pll4_vote", 76 .parent_names = (const char *[]){ "pll4" }, 77 .num_parents = 1, 78 .ops = &clk_pll_vote_ops, 79 }, 80}; 81 82static struct clk_pll pll8 = { 83 .l_reg = 0x3144, 84 .m_reg = 0x3148, 85 .n_reg = 0x314c, 86 .config_reg = 0x3154, 87 .mode_reg = 0x3140, 88 .status_reg = 0x3158, 89 .status_bit = 16, 90 .clkr.hw.init = &(struct clk_init_data){ 91 .name = "pll8", 92 .parent_names = (const char *[]){ "pxo" }, 93 .num_parents = 1, 94 .ops = &clk_pll_ops, 95 }, 96}; 97 98static struct clk_regmap pll8_vote = { 99 .enable_reg = 0x34c0, 100 .enable_mask = BIT(8), 101 .hw.init = &(struct clk_init_data){ 102 .name = "pll8_vote", 103 .parent_names = (const char *[]){ "pll8" }, 104 .num_parents = 1, 105 .ops = &clk_pll_vote_ops, 106 }, 107}; 108 109static struct hfpll_data hfpll0_data = { 110 .mode_reg = 0x3200, 111 .l_reg = 0x3208, 112 .m_reg = 0x320c, 113 .n_reg = 0x3210, 114 .config_reg = 0x3204, 115 .status_reg = 0x321c, 116 .config_val = 0x7845c665, 117 .droop_reg = 0x3214, 118 .droop_val = 0x0108c000, 119 .min_rate = 600000000UL, 120 .max_rate = 1800000000UL, 121}; 122 123static struct clk_hfpll hfpll0 = { 124 .d = &hfpll0_data, 125 .clkr.hw.init = &(struct clk_init_data){ 126 .parent_names = (const char *[]){ "pxo" }, 127 .num_parents = 1, 128 .name = "hfpll0", 129 .ops = &clk_ops_hfpll, 130 .flags = CLK_IGNORE_UNUSED, 131 }, 132 .lock = __SPIN_LOCK_UNLOCKED(hfpll0.lock), 133}; 134 135static struct hfpll_data hfpll1_data = { 136 .mode_reg = 0x3240, 137 .l_reg = 0x3248, 138 .m_reg = 0x324c, 139 .n_reg = 0x3250, 140 .config_reg = 0x3244, 141 .status_reg = 0x325c, 142 .config_val = 0x7845c665, 143 .droop_reg = 0x3314, 144 .droop_val = 0x0108c000, 145 .min_rate = 600000000UL, 146 .max_rate = 1800000000UL, 147}; 148 149static struct clk_hfpll hfpll1 = { 150 .d = &hfpll1_data, 151 .clkr.hw.init = &(struct clk_init_data){ 152 .parent_names = (const char *[]){ "pxo" }, 153 .num_parents = 1, 154 .name = "hfpll1", 155 .ops = &clk_ops_hfpll, 156 .flags = CLK_IGNORE_UNUSED, 157 }, 158 .lock = __SPIN_LOCK_UNLOCKED(hfpll1.lock), 159}; 160 161static struct hfpll_data hfpll_l2_data = { 162 .mode_reg = 0x3300, 163 .l_reg = 0x3308, 164 .m_reg = 0x330c, 165 .n_reg = 0x3310, 166 .config_reg = 0x3304, 167 .status_reg = 0x331c, 168 .config_val = 0x7845c665, 169 .droop_reg = 0x3314, 170 .droop_val = 0x0108c000, 171 .min_rate = 600000000UL, 172 .max_rate = 1800000000UL, 173}; 174 175static struct clk_hfpll hfpll_l2 = { 176 .d = &hfpll_l2_data, 177 .clkr.hw.init = &(struct clk_init_data){ 178 .parent_names = (const char *[]){ "pxo" }, 179 .num_parents = 1, 180 .name = "hfpll_l2", 181 .ops = &clk_ops_hfpll, 182 .flags = CLK_IGNORE_UNUSED, 183 }, 184 .lock = __SPIN_LOCK_UNLOCKED(hfpll_l2.lock), 185}; 186 187static struct clk_pll pll14 = { 188 .l_reg = 0x31c4, 189 .m_reg = 0x31c8, 190 .n_reg = 0x31cc, 191 .config_reg = 0x31d4, 192 .mode_reg = 0x31c0, 193 .status_reg = 0x31d8, 194 .status_bit = 16, 195 .clkr.hw.init = &(struct clk_init_data){ 196 .name = "pll14", 197 .parent_names = (const char *[]){ "pxo" }, 198 .num_parents = 1, 199 .ops = &clk_pll_ops, 200 }, 201}; 202 203static struct clk_regmap pll14_vote = { 204 .enable_reg = 0x34c0, 205 .enable_mask = BIT(14), 206 .hw.init = &(struct clk_init_data){ 207 .name = "pll14_vote", 208 .parent_names = (const char *[]){ "pll14" }, 209 .num_parents = 1, 210 .ops = &clk_pll_vote_ops, 211 }, 212}; 213 214#define NSS_PLL_RATE(f, _l, _m, _n, i) \ 215 { \ 216 .freq = f, \ 217 .l = _l, \ 218 .m = _m, \ 219 .n = _n, \ 220 .ibits = i, \ 221 } 222 223static struct pll_freq_tbl pll18_freq_tbl[] = { 224 NSS_PLL_RATE(550000000, 44, 0, 1, 0x01495625), 225 NSS_PLL_RATE(733000000, 58, 16, 25, 0x014b5625), 226}; 227 228static struct clk_pll pll18 = { 229 .l_reg = 0x31a4, 230 .m_reg = 0x31a8, 231 .n_reg = 0x31ac, 232 .config_reg = 0x31b4, 233 .mode_reg = 0x31a0, 234 .status_reg = 0x31b8, 235 .status_bit = 16, 236 .post_div_shift = 16, 237 .post_div_width = 1, 238 .freq_tbl = pll18_freq_tbl, 239 .clkr.hw.init = &(struct clk_init_data){ 240 .name = "pll18", 241 .parent_names = (const char *[]){ "pxo" }, 242 .num_parents = 1, 243 .ops = &clk_pll_ops, 244 }, 245}; 246 247enum { 248 P_PXO, 249 P_PLL8, 250 P_PLL3, 251 P_PLL0, 252 P_CXO, 253 P_PLL14, 254 P_PLL18, 255}; 256 257static const struct parent_map gcc_pxo_pll8_map[] = { 258 { P_PXO, 0 }, 259 { P_PLL8, 3 } 260}; 261 262static const char * const gcc_pxo_pll8[] = { 263 "pxo", 264 "pll8_vote", 265}; 266 267static const struct parent_map gcc_pxo_pll8_cxo_map[] = { 268 { P_PXO, 0 }, 269 { P_PLL8, 3 }, 270 { P_CXO, 5 } 271}; 272 273static const char * const gcc_pxo_pll8_cxo[] = { 274 "pxo", 275 "pll8_vote", 276 "cxo", 277}; 278 279static const struct parent_map gcc_pxo_pll3_map[] = { 280 { P_PXO, 0 }, 281 { P_PLL3, 1 } 282}; 283 284static const struct parent_map gcc_pxo_pll3_sata_map[] = { 285 { P_PXO, 0 }, 286 { P_PLL3, 6 } 287}; 288 289static const char * const gcc_pxo_pll3[] = { 290 "pxo", 291 "pll3", 292}; 293 294static const struct parent_map gcc_pxo_pll8_pll0[] = { 295 { P_PXO, 0 }, 296 { P_PLL8, 3 }, 297 { P_PLL0, 2 } 298}; 299 300static const char * const gcc_pxo_pll8_pll0_map[] = { 301 "pxo", 302 "pll8_vote", 303 "pll0_vote", 304}; 305 306static const struct parent_map gcc_pxo_pll8_pll14_pll18_pll0_map[] = { 307 { P_PXO, 0 }, 308 { P_PLL8, 4 }, 309 { P_PLL0, 2 }, 310 { P_PLL14, 5 }, 311 { P_PLL18, 1 } 312}; 313 314static const char * const gcc_pxo_pll8_pll14_pll18_pll0[] = { 315 "pxo", 316 "pll8_vote", 317 "pll0_vote", 318 "pll14", 319 "pll18", 320}; 321 322static struct freq_tbl clk_tbl_gsbi_uart[] = { 323 { 1843200, P_PLL8, 2, 6, 625 }, 324 { 3686400, P_PLL8, 2, 12, 625 }, 325 { 7372800, P_PLL8, 2, 24, 625 }, 326 { 14745600, P_PLL8, 2, 48, 625 }, 327 { 16000000, P_PLL8, 4, 1, 6 }, 328 { 24000000, P_PLL8, 4, 1, 4 }, 329 { 32000000, P_PLL8, 4, 1, 3 }, 330 { 40000000, P_PLL8, 1, 5, 48 }, 331 { 46400000, P_PLL8, 1, 29, 240 }, 332 { 48000000, P_PLL8, 4, 1, 2 }, 333 { 51200000, P_PLL8, 1, 2, 15 }, 334 { 56000000, P_PLL8, 1, 7, 48 }, 335 { 58982400, P_PLL8, 1, 96, 625 }, 336 { 64000000, P_PLL8, 2, 1, 3 }, 337 { } 338}; 339 340static struct clk_rcg gsbi1_uart_src = { 341 .ns_reg = 0x29d4, 342 .md_reg = 0x29d0, 343 .mn = { 344 .mnctr_en_bit = 8, 345 .mnctr_reset_bit = 7, 346 .mnctr_mode_shift = 5, 347 .n_val_shift = 16, 348 .m_val_shift = 16, 349 .width = 16, 350 }, 351 .p = { 352 .pre_div_shift = 3, 353 .pre_div_width = 2, 354 }, 355 .s = { 356 .src_sel_shift = 0, 357 .parent_map = gcc_pxo_pll8_map, 358 }, 359 .freq_tbl = clk_tbl_gsbi_uart, 360 .clkr = { 361 .enable_reg = 0x29d4, 362 .enable_mask = BIT(11), 363 .hw.init = &(struct clk_init_data){ 364 .name = "gsbi1_uart_src", 365 .parent_names = gcc_pxo_pll8, 366 .num_parents = 2, 367 .ops = &clk_rcg_ops, 368 .flags = CLK_SET_PARENT_GATE, 369 }, 370 }, 371}; 372 373static struct clk_branch gsbi1_uart_clk = { 374 .halt_reg = 0x2fcc, 375 .halt_bit = 12, 376 .clkr = { 377 .enable_reg = 0x29d4, 378 .enable_mask = BIT(9), 379 .hw.init = &(struct clk_init_data){ 380 .name = "gsbi1_uart_clk", 381 .parent_names = (const char *[]){ 382 "gsbi1_uart_src", 383 }, 384 .num_parents = 1, 385 .ops = &clk_branch_ops, 386 .flags = CLK_SET_RATE_PARENT, 387 }, 388 }, 389}; 390 391static struct clk_rcg gsbi2_uart_src = { 392 .ns_reg = 0x29f4, 393 .md_reg = 0x29f0, 394 .mn = { 395 .mnctr_en_bit = 8, 396 .mnctr_reset_bit = 7, 397 .mnctr_mode_shift = 5, 398 .n_val_shift = 16, 399 .m_val_shift = 16, 400 .width = 16, 401 }, 402 .p = { 403 .pre_div_shift = 3, 404 .pre_div_width = 2, 405 }, 406 .s = { 407 .src_sel_shift = 0, 408 .parent_map = gcc_pxo_pll8_map, 409 }, 410 .freq_tbl = clk_tbl_gsbi_uart, 411 .clkr = { 412 .enable_reg = 0x29f4, 413 .enable_mask = BIT(11), 414 .hw.init = &(struct clk_init_data){ 415 .name = "gsbi2_uart_src", 416 .parent_names = gcc_pxo_pll8, 417 .num_parents = 2, 418 .ops = &clk_rcg_ops, 419 .flags = CLK_SET_PARENT_GATE, 420 }, 421 }, 422}; 423 424static struct clk_branch gsbi2_uart_clk = { 425 .halt_reg = 0x2fcc, 426 .halt_bit = 8, 427 .clkr = { 428 .enable_reg = 0x29f4, 429 .enable_mask = BIT(9), 430 .hw.init = &(struct clk_init_data){ 431 .name = "gsbi2_uart_clk", 432 .parent_names = (const char *[]){ 433 "gsbi2_uart_src", 434 }, 435 .num_parents = 1, 436 .ops = &clk_branch_ops, 437 .flags = CLK_SET_RATE_PARENT, 438 }, 439 }, 440}; 441 442static struct clk_rcg gsbi4_uart_src = { 443 .ns_reg = 0x2a34, 444 .md_reg = 0x2a30, 445 .mn = { 446 .mnctr_en_bit = 8, 447 .mnctr_reset_bit = 7, 448 .mnctr_mode_shift = 5, 449 .n_val_shift = 16, 450 .m_val_shift = 16, 451 .width = 16, 452 }, 453 .p = { 454 .pre_div_shift = 3, 455 .pre_div_width = 2, 456 }, 457 .s = { 458 .src_sel_shift = 0, 459 .parent_map = gcc_pxo_pll8_map, 460 }, 461 .freq_tbl = clk_tbl_gsbi_uart, 462 .clkr = { 463 .enable_reg = 0x2a34, 464 .enable_mask = BIT(11), 465 .hw.init = &(struct clk_init_data){ 466 .name = "gsbi4_uart_src", 467 .parent_names = gcc_pxo_pll8, 468 .num_parents = 2, 469 .ops = &clk_rcg_ops, 470 .flags = CLK_SET_PARENT_GATE, 471 }, 472 }, 473}; 474 475static struct clk_branch gsbi4_uart_clk = { 476 .halt_reg = 0x2fd0, 477 .halt_bit = 26, 478 .clkr = { 479 .enable_reg = 0x2a34, 480 .enable_mask = BIT(9), 481 .hw.init = &(struct clk_init_data){ 482 .name = "gsbi4_uart_clk", 483 .parent_names = (const char *[]){ 484 "gsbi4_uart_src", 485 }, 486 .num_parents = 1, 487 .ops = &clk_branch_ops, 488 .flags = CLK_SET_RATE_PARENT, 489 }, 490 }, 491}; 492 493static struct clk_rcg gsbi5_uart_src = { 494 .ns_reg = 0x2a54, 495 .md_reg = 0x2a50, 496 .mn = { 497 .mnctr_en_bit = 8, 498 .mnctr_reset_bit = 7, 499 .mnctr_mode_shift = 5, 500 .n_val_shift = 16, 501 .m_val_shift = 16, 502 .width = 16, 503 }, 504 .p = { 505 .pre_div_shift = 3, 506 .pre_div_width = 2, 507 }, 508 .s = { 509 .src_sel_shift = 0, 510 .parent_map = gcc_pxo_pll8_map, 511 }, 512 .freq_tbl = clk_tbl_gsbi_uart, 513 .clkr = { 514 .enable_reg = 0x2a54, 515 .enable_mask = BIT(11), 516 .hw.init = &(struct clk_init_data){ 517 .name = "gsbi5_uart_src", 518 .parent_names = gcc_pxo_pll8, 519 .num_parents = 2, 520 .ops = &clk_rcg_ops, 521 .flags = CLK_SET_PARENT_GATE, 522 }, 523 }, 524}; 525 526static struct clk_branch gsbi5_uart_clk = { 527 .halt_reg = 0x2fd0, 528 .halt_bit = 22, 529 .clkr = { 530 .enable_reg = 0x2a54, 531 .enable_mask = BIT(9), 532 .hw.init = &(struct clk_init_data){ 533 .name = "gsbi5_uart_clk", 534 .parent_names = (const char *[]){ 535 "gsbi5_uart_src", 536 }, 537 .num_parents = 1, 538 .ops = &clk_branch_ops, 539 .flags = CLK_SET_RATE_PARENT, 540 }, 541 }, 542}; 543 544static struct clk_rcg gsbi6_uart_src = { 545 .ns_reg = 0x2a74, 546 .md_reg = 0x2a70, 547 .mn = { 548 .mnctr_en_bit = 8, 549 .mnctr_reset_bit = 7, 550 .mnctr_mode_shift = 5, 551 .n_val_shift = 16, 552 .m_val_shift = 16, 553 .width = 16, 554 }, 555 .p = { 556 .pre_div_shift = 3, 557 .pre_div_width = 2, 558 }, 559 .s = { 560 .src_sel_shift = 0, 561 .parent_map = gcc_pxo_pll8_map, 562 }, 563 .freq_tbl = clk_tbl_gsbi_uart, 564 .clkr = { 565 .enable_reg = 0x2a74, 566 .enable_mask = BIT(11), 567 .hw.init = &(struct clk_init_data){ 568 .name = "gsbi6_uart_src", 569 .parent_names = gcc_pxo_pll8, 570 .num_parents = 2, 571 .ops = &clk_rcg_ops, 572 .flags = CLK_SET_PARENT_GATE, 573 }, 574 }, 575}; 576 577static struct clk_branch gsbi6_uart_clk = { 578 .halt_reg = 0x2fd0, 579 .halt_bit = 18, 580 .clkr = { 581 .enable_reg = 0x2a74, 582 .enable_mask = BIT(9), 583 .hw.init = &(struct clk_init_data){ 584 .name = "gsbi6_uart_clk", 585 .parent_names = (const char *[]){ 586 "gsbi6_uart_src", 587 }, 588 .num_parents = 1, 589 .ops = &clk_branch_ops, 590 .flags = CLK_SET_RATE_PARENT, 591 }, 592 }, 593}; 594 595static struct clk_rcg gsbi7_uart_src = { 596 .ns_reg = 0x2a94, 597 .md_reg = 0x2a90, 598 .mn = { 599 .mnctr_en_bit = 8, 600 .mnctr_reset_bit = 7, 601 .mnctr_mode_shift = 5, 602 .n_val_shift = 16, 603 .m_val_shift = 16, 604 .width = 16, 605 }, 606 .p = { 607 .pre_div_shift = 3, 608 .pre_div_width = 2, 609 }, 610 .s = { 611 .src_sel_shift = 0, 612 .parent_map = gcc_pxo_pll8_map, 613 }, 614 .freq_tbl = clk_tbl_gsbi_uart, 615 .clkr = { 616 .enable_reg = 0x2a94, 617 .enable_mask = BIT(11), 618 .hw.init = &(struct clk_init_data){ 619 .name = "gsbi7_uart_src", 620 .parent_names = gcc_pxo_pll8, 621 .num_parents = 2, 622 .ops = &clk_rcg_ops, 623 .flags = CLK_SET_PARENT_GATE, 624 }, 625 }, 626}; 627 628static struct clk_branch gsbi7_uart_clk = { 629 .halt_reg = 0x2fd0, 630 .halt_bit = 14, 631 .clkr = { 632 .enable_reg = 0x2a94, 633 .enable_mask = BIT(9), 634 .hw.init = &(struct clk_init_data){ 635 .name = "gsbi7_uart_clk", 636 .parent_names = (const char *[]){ 637 "gsbi7_uart_src", 638 }, 639 .num_parents = 1, 640 .ops = &clk_branch_ops, 641 .flags = CLK_SET_RATE_PARENT, 642 }, 643 }, 644}; 645 646static struct freq_tbl clk_tbl_gsbi_qup[] = { 647 { 1100000, P_PXO, 1, 2, 49 }, 648 { 5400000, P_PXO, 1, 1, 5 }, 649 { 10800000, P_PXO, 1, 2, 5 }, 650 { 15060000, P_PLL8, 1, 2, 51 }, 651 { 24000000, P_PLL8, 4, 1, 4 }, 652 { 25000000, P_PXO, 1, 0, 0 }, 653 { 25600000, P_PLL8, 1, 1, 15 }, 654 { 48000000, P_PLL8, 4, 1, 2 }, 655 { 51200000, P_PLL8, 1, 2, 15 }, 656 { } 657}; 658 659static struct clk_rcg gsbi1_qup_src = { 660 .ns_reg = 0x29cc, 661 .md_reg = 0x29c8, 662 .mn = { 663 .mnctr_en_bit = 8, 664 .mnctr_reset_bit = 7, 665 .mnctr_mode_shift = 5, 666 .n_val_shift = 16, 667 .m_val_shift = 16, 668 .width = 8, 669 }, 670 .p = { 671 .pre_div_shift = 3, 672 .pre_div_width = 2, 673 }, 674 .s = { 675 .src_sel_shift = 0, 676 .parent_map = gcc_pxo_pll8_map, 677 }, 678 .freq_tbl = clk_tbl_gsbi_qup, 679 .clkr = { 680 .enable_reg = 0x29cc, 681 .enable_mask = BIT(11), 682 .hw.init = &(struct clk_init_data){ 683 .name = "gsbi1_qup_src", 684 .parent_names = gcc_pxo_pll8, 685 .num_parents = 2, 686 .ops = &clk_rcg_ops, 687 .flags = CLK_SET_PARENT_GATE, 688 }, 689 }, 690}; 691 692static struct clk_branch gsbi1_qup_clk = { 693 .halt_reg = 0x2fcc, 694 .halt_bit = 11, 695 .clkr = { 696 .enable_reg = 0x29cc, 697 .enable_mask = BIT(9), 698 .hw.init = &(struct clk_init_data){ 699 .name = "gsbi1_qup_clk", 700 .parent_names = (const char *[]){ "gsbi1_qup_src" }, 701 .num_parents = 1, 702 .ops = &clk_branch_ops, 703 .flags = CLK_SET_RATE_PARENT, 704 }, 705 }, 706}; 707 708static struct clk_rcg gsbi2_qup_src = { 709 .ns_reg = 0x29ec, 710 .md_reg = 0x29e8, 711 .mn = { 712 .mnctr_en_bit = 8, 713 .mnctr_reset_bit = 7, 714 .mnctr_mode_shift = 5, 715 .n_val_shift = 16, 716 .m_val_shift = 16, 717 .width = 8, 718 }, 719 .p = { 720 .pre_div_shift = 3, 721 .pre_div_width = 2, 722 }, 723 .s = { 724 .src_sel_shift = 0, 725 .parent_map = gcc_pxo_pll8_map, 726 }, 727 .freq_tbl = clk_tbl_gsbi_qup, 728 .clkr = { 729 .enable_reg = 0x29ec, 730 .enable_mask = BIT(11), 731 .hw.init = &(struct clk_init_data){ 732 .name = "gsbi2_qup_src", 733 .parent_names = gcc_pxo_pll8, 734 .num_parents = 2, 735 .ops = &clk_rcg_ops, 736 .flags = CLK_SET_PARENT_GATE, 737 }, 738 }, 739}; 740 741static struct clk_branch gsbi2_qup_clk = { 742 .halt_reg = 0x2fcc, 743 .halt_bit = 6, 744 .clkr = { 745 .enable_reg = 0x29ec, 746 .enable_mask = BIT(9), 747 .hw.init = &(struct clk_init_data){ 748 .name = "gsbi2_qup_clk", 749 .parent_names = (const char *[]){ "gsbi2_qup_src" }, 750 .num_parents = 1, 751 .ops = &clk_branch_ops, 752 .flags = CLK_SET_RATE_PARENT, 753 }, 754 }, 755}; 756 757static struct clk_rcg gsbi4_qup_src = { 758 .ns_reg = 0x2a2c, 759 .md_reg = 0x2a28, 760 .mn = { 761 .mnctr_en_bit = 8, 762 .mnctr_reset_bit = 7, 763 .mnctr_mode_shift = 5, 764 .n_val_shift = 16, 765 .m_val_shift = 16, 766 .width = 8, 767 }, 768 .p = { 769 .pre_div_shift = 3, 770 .pre_div_width = 2, 771 }, 772 .s = { 773 .src_sel_shift = 0, 774 .parent_map = gcc_pxo_pll8_map, 775 }, 776 .freq_tbl = clk_tbl_gsbi_qup, 777 .clkr = { 778 .enable_reg = 0x2a2c, 779 .enable_mask = BIT(11), 780 .hw.init = &(struct clk_init_data){ 781 .name = "gsbi4_qup_src", 782 .parent_names = gcc_pxo_pll8, 783 .num_parents = 2, 784 .ops = &clk_rcg_ops, 785 .flags = CLK_SET_PARENT_GATE, 786 }, 787 }, 788}; 789 790static struct clk_branch gsbi4_qup_clk = { 791 .halt_reg = 0x2fd0, 792 .halt_bit = 24, 793 .clkr = { 794 .enable_reg = 0x2a2c, 795 .enable_mask = BIT(9), 796 .hw.init = &(struct clk_init_data){ 797 .name = "gsbi4_qup_clk", 798 .parent_names = (const char *[]){ "gsbi4_qup_src" }, 799 .num_parents = 1, 800 .ops = &clk_branch_ops, 801 .flags = CLK_SET_RATE_PARENT, 802 }, 803 }, 804}; 805 806static struct clk_rcg gsbi5_qup_src = { 807 .ns_reg = 0x2a4c, 808 .md_reg = 0x2a48, 809 .mn = { 810 .mnctr_en_bit = 8, 811 .mnctr_reset_bit = 7, 812 .mnctr_mode_shift = 5, 813 .n_val_shift = 16, 814 .m_val_shift = 16, 815 .width = 8, 816 }, 817 .p = { 818 .pre_div_shift = 3, 819 .pre_div_width = 2, 820 }, 821 .s = { 822 .src_sel_shift = 0, 823 .parent_map = gcc_pxo_pll8_map, 824 }, 825 .freq_tbl = clk_tbl_gsbi_qup, 826 .clkr = { 827 .enable_reg = 0x2a4c, 828 .enable_mask = BIT(11), 829 .hw.init = &(struct clk_init_data){ 830 .name = "gsbi5_qup_src", 831 .parent_names = gcc_pxo_pll8, 832 .num_parents = 2, 833 .ops = &clk_rcg_ops, 834 .flags = CLK_SET_PARENT_GATE, 835 }, 836 }, 837}; 838 839static struct clk_branch gsbi5_qup_clk = { 840 .halt_reg = 0x2fd0, 841 .halt_bit = 20, 842 .clkr = { 843 .enable_reg = 0x2a4c, 844 .enable_mask = BIT(9), 845 .hw.init = &(struct clk_init_data){ 846 .name = "gsbi5_qup_clk", 847 .parent_names = (const char *[]){ "gsbi5_qup_src" }, 848 .num_parents = 1, 849 .ops = &clk_branch_ops, 850 .flags = CLK_SET_RATE_PARENT, 851 }, 852 }, 853}; 854 855static struct clk_rcg gsbi6_qup_src = { 856 .ns_reg = 0x2a6c, 857 .md_reg = 0x2a68, 858 .mn = { 859 .mnctr_en_bit = 8, 860 .mnctr_reset_bit = 7, 861 .mnctr_mode_shift = 5, 862 .n_val_shift = 16, 863 .m_val_shift = 16, 864 .width = 8, 865 }, 866 .p = { 867 .pre_div_shift = 3, 868 .pre_div_width = 2, 869 }, 870 .s = { 871 .src_sel_shift = 0, 872 .parent_map = gcc_pxo_pll8_map, 873 }, 874 .freq_tbl = clk_tbl_gsbi_qup, 875 .clkr = { 876 .enable_reg = 0x2a6c, 877 .enable_mask = BIT(11), 878 .hw.init = &(struct clk_init_data){ 879 .name = "gsbi6_qup_src", 880 .parent_names = gcc_pxo_pll8, 881 .num_parents = 2, 882 .ops = &clk_rcg_ops, 883 .flags = CLK_SET_PARENT_GATE, 884 }, 885 }, 886}; 887 888static struct clk_branch gsbi6_qup_clk = { 889 .halt_reg = 0x2fd0, 890 .halt_bit = 16, 891 .clkr = { 892 .enable_reg = 0x2a6c, 893 .enable_mask = BIT(9), 894 .hw.init = &(struct clk_init_data){ 895 .name = "gsbi6_qup_clk", 896 .parent_names = (const char *[]){ "gsbi6_qup_src" }, 897 .num_parents = 1, 898 .ops = &clk_branch_ops, 899 .flags = CLK_SET_RATE_PARENT, 900 }, 901 }, 902}; 903 904static struct clk_rcg gsbi7_qup_src = { 905 .ns_reg = 0x2a8c, 906 .md_reg = 0x2a88, 907 .mn = { 908 .mnctr_en_bit = 8, 909 .mnctr_reset_bit = 7, 910 .mnctr_mode_shift = 5, 911 .n_val_shift = 16, 912 .m_val_shift = 16, 913 .width = 8, 914 }, 915 .p = { 916 .pre_div_shift = 3, 917 .pre_div_width = 2, 918 }, 919 .s = { 920 .src_sel_shift = 0, 921 .parent_map = gcc_pxo_pll8_map, 922 }, 923 .freq_tbl = clk_tbl_gsbi_qup, 924 .clkr = { 925 .enable_reg = 0x2a8c, 926 .enable_mask = BIT(11), 927 .hw.init = &(struct clk_init_data){ 928 .name = "gsbi7_qup_src", 929 .parent_names = gcc_pxo_pll8, 930 .num_parents = 2, 931 .ops = &clk_rcg_ops, 932 .flags = CLK_SET_PARENT_GATE, 933 }, 934 }, 935}; 936 937static struct clk_branch gsbi7_qup_clk = { 938 .halt_reg = 0x2fd0, 939 .halt_bit = 12, 940 .clkr = { 941 .enable_reg = 0x2a8c, 942 .enable_mask = BIT(9), 943 .hw.init = &(struct clk_init_data){ 944 .name = "gsbi7_qup_clk", 945 .parent_names = (const char *[]){ "gsbi7_qup_src" }, 946 .num_parents = 1, 947 .ops = &clk_branch_ops, 948 .flags = CLK_SET_RATE_PARENT, 949 }, 950 }, 951}; 952 953static struct clk_branch gsbi1_h_clk = { 954 .hwcg_reg = 0x29c0, 955 .hwcg_bit = 6, 956 .halt_reg = 0x2fcc, 957 .halt_bit = 13, 958 .clkr = { 959 .enable_reg = 0x29c0, 960 .enable_mask = BIT(4), 961 .hw.init = &(struct clk_init_data){ 962 .name = "gsbi1_h_clk", 963 .ops = &clk_branch_ops, 964 }, 965 }, 966}; 967 968static struct clk_branch gsbi2_h_clk = { 969 .hwcg_reg = 0x29e0, 970 .hwcg_bit = 6, 971 .halt_reg = 0x2fcc, 972 .halt_bit = 9, 973 .clkr = { 974 .enable_reg = 0x29e0, 975 .enable_mask = BIT(4), 976 .hw.init = &(struct clk_init_data){ 977 .name = "gsbi2_h_clk", 978 .ops = &clk_branch_ops, 979 }, 980 }, 981}; 982 983static struct clk_branch gsbi4_h_clk = { 984 .hwcg_reg = 0x2a20, 985 .hwcg_bit = 6, 986 .halt_reg = 0x2fd0, 987 .halt_bit = 27, 988 .clkr = { 989 .enable_reg = 0x2a20, 990 .enable_mask = BIT(4), 991 .hw.init = &(struct clk_init_data){ 992 .name = "gsbi4_h_clk", 993 .ops = &clk_branch_ops, 994 }, 995 }, 996}; 997 998static struct clk_branch gsbi5_h_clk = { 999 .hwcg_reg = 0x2a40, 1000 .hwcg_bit = 6, 1001 .halt_reg = 0x2fd0, 1002 .halt_bit = 23, 1003 .clkr = { 1004 .enable_reg = 0x2a40, 1005 .enable_mask = BIT(4), 1006 .hw.init = &(struct clk_init_data){ 1007 .name = "gsbi5_h_clk", 1008 .ops = &clk_branch_ops, 1009 }, 1010 }, 1011}; 1012 1013static struct clk_branch gsbi6_h_clk = { 1014 .hwcg_reg = 0x2a60, 1015 .hwcg_bit = 6, 1016 .halt_reg = 0x2fd0, 1017 .halt_bit = 19, 1018 .clkr = { 1019 .enable_reg = 0x2a60, 1020 .enable_mask = BIT(4), 1021 .hw.init = &(struct clk_init_data){ 1022 .name = "gsbi6_h_clk", 1023 .ops = &clk_branch_ops, 1024 }, 1025 }, 1026}; 1027 1028static struct clk_branch gsbi7_h_clk = { 1029 .hwcg_reg = 0x2a80, 1030 .hwcg_bit = 6, 1031 .halt_reg = 0x2fd0, 1032 .halt_bit = 15, 1033 .clkr = { 1034 .enable_reg = 0x2a80, 1035 .enable_mask = BIT(4), 1036 .hw.init = &(struct clk_init_data){ 1037 .name = "gsbi7_h_clk", 1038 .ops = &clk_branch_ops, 1039 }, 1040 }, 1041}; 1042 1043static const struct freq_tbl clk_tbl_gp[] = { 1044 { 12500000, P_PXO, 2, 0, 0 }, 1045 { 25000000, P_PXO, 1, 0, 0 }, 1046 { 64000000, P_PLL8, 2, 1, 3 }, 1047 { 76800000, P_PLL8, 1, 1, 5 }, 1048 { 96000000, P_PLL8, 4, 0, 0 }, 1049 { 128000000, P_PLL8, 3, 0, 0 }, 1050 { 192000000, P_PLL8, 2, 0, 0 }, 1051 { } 1052}; 1053 1054static struct clk_rcg gp0_src = { 1055 .ns_reg = 0x2d24, 1056 .md_reg = 0x2d00, 1057 .mn = { 1058 .mnctr_en_bit = 8, 1059 .mnctr_reset_bit = 7, 1060 .mnctr_mode_shift = 5, 1061 .n_val_shift = 16, 1062 .m_val_shift = 16, 1063 .width = 8, 1064 }, 1065 .p = { 1066 .pre_div_shift = 3, 1067 .pre_div_width = 2, 1068 }, 1069 .s = { 1070 .src_sel_shift = 0, 1071 .parent_map = gcc_pxo_pll8_cxo_map, 1072 }, 1073 .freq_tbl = clk_tbl_gp, 1074 .clkr = { 1075 .enable_reg = 0x2d24, 1076 .enable_mask = BIT(11), 1077 .hw.init = &(struct clk_init_data){ 1078 .name = "gp0_src", 1079 .parent_names = gcc_pxo_pll8_cxo, 1080 .num_parents = 3, 1081 .ops = &clk_rcg_ops, 1082 .flags = CLK_SET_PARENT_GATE, 1083 }, 1084 } 1085}; 1086 1087static struct clk_branch gp0_clk = { 1088 .halt_reg = 0x2fd8, 1089 .halt_bit = 7, 1090 .clkr = { 1091 .enable_reg = 0x2d24, 1092 .enable_mask = BIT(9), 1093 .hw.init = &(struct clk_init_data){ 1094 .name = "gp0_clk", 1095 .parent_names = (const char *[]){ "gp0_src" }, 1096 .num_parents = 1, 1097 .ops = &clk_branch_ops, 1098 .flags = CLK_SET_RATE_PARENT, 1099 }, 1100 }, 1101}; 1102 1103static struct clk_rcg gp1_src = { 1104 .ns_reg = 0x2d44, 1105 .md_reg = 0x2d40, 1106 .mn = { 1107 .mnctr_en_bit = 8, 1108 .mnctr_reset_bit = 7, 1109 .mnctr_mode_shift = 5, 1110 .n_val_shift = 16, 1111 .m_val_shift = 16, 1112 .width = 8, 1113 }, 1114 .p = { 1115 .pre_div_shift = 3, 1116 .pre_div_width = 2, 1117 }, 1118 .s = { 1119 .src_sel_shift = 0, 1120 .parent_map = gcc_pxo_pll8_cxo_map, 1121 }, 1122 .freq_tbl = clk_tbl_gp, 1123 .clkr = { 1124 .enable_reg = 0x2d44, 1125 .enable_mask = BIT(11), 1126 .hw.init = &(struct clk_init_data){ 1127 .name = "gp1_src", 1128 .parent_names = gcc_pxo_pll8_cxo, 1129 .num_parents = 3, 1130 .ops = &clk_rcg_ops, 1131 .flags = CLK_SET_RATE_GATE, 1132 }, 1133 } 1134}; 1135 1136static struct clk_branch gp1_clk = { 1137 .halt_reg = 0x2fd8, 1138 .halt_bit = 6, 1139 .clkr = { 1140 .enable_reg = 0x2d44, 1141 .enable_mask = BIT(9), 1142 .hw.init = &(struct clk_init_data){ 1143 .name = "gp1_clk", 1144 .parent_names = (const char *[]){ "gp1_src" }, 1145 .num_parents = 1, 1146 .ops = &clk_branch_ops, 1147 .flags = CLK_SET_RATE_PARENT, 1148 }, 1149 }, 1150}; 1151 1152static struct clk_rcg gp2_src = { 1153 .ns_reg = 0x2d64, 1154 .md_reg = 0x2d60, 1155 .mn = { 1156 .mnctr_en_bit = 8, 1157 .mnctr_reset_bit = 7, 1158 .mnctr_mode_shift = 5, 1159 .n_val_shift = 16, 1160 .m_val_shift = 16, 1161 .width = 8, 1162 }, 1163 .p = { 1164 .pre_div_shift = 3, 1165 .pre_div_width = 2, 1166 }, 1167 .s = { 1168 .src_sel_shift = 0, 1169 .parent_map = gcc_pxo_pll8_cxo_map, 1170 }, 1171 .freq_tbl = clk_tbl_gp, 1172 .clkr = { 1173 .enable_reg = 0x2d64, 1174 .enable_mask = BIT(11), 1175 .hw.init = &(struct clk_init_data){ 1176 .name = "gp2_src", 1177 .parent_names = gcc_pxo_pll8_cxo, 1178 .num_parents = 3, 1179 .ops = &clk_rcg_ops, 1180 .flags = CLK_SET_RATE_GATE, 1181 }, 1182 } 1183}; 1184 1185static struct clk_branch gp2_clk = { 1186 .halt_reg = 0x2fd8, 1187 .halt_bit = 5, 1188 .clkr = { 1189 .enable_reg = 0x2d64, 1190 .enable_mask = BIT(9), 1191 .hw.init = &(struct clk_init_data){ 1192 .name = "gp2_clk", 1193 .parent_names = (const char *[]){ "gp2_src" }, 1194 .num_parents = 1, 1195 .ops = &clk_branch_ops, 1196 .flags = CLK_SET_RATE_PARENT, 1197 }, 1198 }, 1199}; 1200 1201static struct clk_branch pmem_clk = { 1202 .hwcg_reg = 0x25a0, 1203 .hwcg_bit = 6, 1204 .halt_reg = 0x2fc8, 1205 .halt_bit = 20, 1206 .clkr = { 1207 .enable_reg = 0x25a0, 1208 .enable_mask = BIT(4), 1209 .hw.init = &(struct clk_init_data){ 1210 .name = "pmem_clk", 1211 .ops = &clk_branch_ops, 1212 }, 1213 }, 1214}; 1215 1216static struct clk_rcg prng_src = { 1217 .ns_reg = 0x2e80, 1218 .p = { 1219 .pre_div_shift = 3, 1220 .pre_div_width = 4, 1221 }, 1222 .s = { 1223 .src_sel_shift = 0, 1224 .parent_map = gcc_pxo_pll8_map, 1225 }, 1226 .clkr = { 1227 .enable_reg = 0x2e80, 1228 .enable_mask = BIT(11), 1229 .hw.init = &(struct clk_init_data){ 1230 .name = "prng_src", 1231 .parent_names = gcc_pxo_pll8, 1232 .num_parents = 2, 1233 .ops = &clk_rcg_ops, 1234 }, 1235 }, 1236}; 1237 1238static struct clk_branch prng_clk = { 1239 .halt_reg = 0x2fd8, 1240 .halt_check = BRANCH_HALT_VOTED, 1241 .halt_bit = 10, 1242 .clkr = { 1243 .enable_reg = 0x3080, 1244 .enable_mask = BIT(10), 1245 .hw.init = &(struct clk_init_data){ 1246 .name = "prng_clk", 1247 .parent_names = (const char *[]){ "prng_src" }, 1248 .num_parents = 1, 1249 .ops = &clk_branch_ops, 1250 }, 1251 }, 1252}; 1253 1254static const struct freq_tbl clk_tbl_sdc[] = { 1255 { 200000, P_PXO, 2, 2, 125 }, 1256 { 400000, P_PLL8, 4, 1, 240 }, 1257 { 16000000, P_PLL8, 4, 1, 6 }, 1258 { 17070000, P_PLL8, 1, 2, 45 }, 1259 { 20210000, P_PLL8, 1, 1, 19 }, 1260 { 24000000, P_PLL8, 4, 1, 4 }, 1261 { 48000000, P_PLL8, 4, 1, 2 }, 1262 { 64000000, P_PLL8, 3, 1, 2 }, 1263 { 96000000, P_PLL8, 4, 0, 0 }, 1264 { 192000000, P_PLL8, 2, 0, 0 }, 1265 { } 1266}; 1267 1268static struct clk_rcg sdc1_src = { 1269 .ns_reg = 0x282c, 1270 .md_reg = 0x2828, 1271 .mn = { 1272 .mnctr_en_bit = 8, 1273 .mnctr_reset_bit = 7, 1274 .mnctr_mode_shift = 5, 1275 .n_val_shift = 16, 1276 .m_val_shift = 16, 1277 .width = 8, 1278 }, 1279 .p = { 1280 .pre_div_shift = 3, 1281 .pre_div_width = 2, 1282 }, 1283 .s = { 1284 .src_sel_shift = 0, 1285 .parent_map = gcc_pxo_pll8_map, 1286 }, 1287 .freq_tbl = clk_tbl_sdc, 1288 .clkr = { 1289 .enable_reg = 0x282c, 1290 .enable_mask = BIT(11), 1291 .hw.init = &(struct clk_init_data){ 1292 .name = "sdc1_src", 1293 .parent_names = gcc_pxo_pll8, 1294 .num_parents = 2, 1295 .ops = &clk_rcg_ops, 1296 }, 1297 } 1298}; 1299 1300static struct clk_branch sdc1_clk = { 1301 .halt_reg = 0x2fc8, 1302 .halt_bit = 6, 1303 .clkr = { 1304 .enable_reg = 0x282c, 1305 .enable_mask = BIT(9), 1306 .hw.init = &(struct clk_init_data){ 1307 .name = "sdc1_clk", 1308 .parent_names = (const char *[]){ "sdc1_src" }, 1309 .num_parents = 1, 1310 .ops = &clk_branch_ops, 1311 .flags = CLK_SET_RATE_PARENT, 1312 }, 1313 }, 1314}; 1315 1316static struct clk_rcg sdc3_src = { 1317 .ns_reg = 0x286c, 1318 .md_reg = 0x2868, 1319 .mn = { 1320 .mnctr_en_bit = 8, 1321 .mnctr_reset_bit = 7, 1322 .mnctr_mode_shift = 5, 1323 .n_val_shift = 16, 1324 .m_val_shift = 16, 1325 .width = 8, 1326 }, 1327 .p = { 1328 .pre_div_shift = 3, 1329 .pre_div_width = 2, 1330 }, 1331 .s = { 1332 .src_sel_shift = 0, 1333 .parent_map = gcc_pxo_pll8_map, 1334 }, 1335 .freq_tbl = clk_tbl_sdc, 1336 .clkr = { 1337 .enable_reg = 0x286c, 1338 .enable_mask = BIT(11), 1339 .hw.init = &(struct clk_init_data){ 1340 .name = "sdc3_src", 1341 .parent_names = gcc_pxo_pll8, 1342 .num_parents = 2, 1343 .ops = &clk_rcg_ops, 1344 }, 1345 } 1346}; 1347 1348static struct clk_branch sdc3_clk = { 1349 .halt_reg = 0x2fc8, 1350 .halt_bit = 4, 1351 .clkr = { 1352 .enable_reg = 0x286c, 1353 .enable_mask = BIT(9), 1354 .hw.init = &(struct clk_init_data){ 1355 .name = "sdc3_clk", 1356 .parent_names = (const char *[]){ "sdc3_src" }, 1357 .num_parents = 1, 1358 .ops = &clk_branch_ops, 1359 .flags = CLK_SET_RATE_PARENT, 1360 }, 1361 }, 1362}; 1363 1364static struct clk_branch sdc1_h_clk = { 1365 .hwcg_reg = 0x2820, 1366 .hwcg_bit = 6, 1367 .halt_reg = 0x2fc8, 1368 .halt_bit = 11, 1369 .clkr = { 1370 .enable_reg = 0x2820, 1371 .enable_mask = BIT(4), 1372 .hw.init = &(struct clk_init_data){ 1373 .name = "sdc1_h_clk", 1374 .ops = &clk_branch_ops, 1375 }, 1376 }, 1377}; 1378 1379static struct clk_branch sdc3_h_clk = { 1380 .hwcg_reg = 0x2860, 1381 .hwcg_bit = 6, 1382 .halt_reg = 0x2fc8, 1383 .halt_bit = 9, 1384 .clkr = { 1385 .enable_reg = 0x2860, 1386 .enable_mask = BIT(4), 1387 .hw.init = &(struct clk_init_data){ 1388 .name = "sdc3_h_clk", 1389 .ops = &clk_branch_ops, 1390 }, 1391 }, 1392}; 1393 1394static const struct freq_tbl clk_tbl_tsif_ref[] = { 1395 { 105000, P_PXO, 1, 1, 256 }, 1396 { } 1397}; 1398 1399static struct clk_rcg tsif_ref_src = { 1400 .ns_reg = 0x2710, 1401 .md_reg = 0x270c, 1402 .mn = { 1403 .mnctr_en_bit = 8, 1404 .mnctr_reset_bit = 7, 1405 .mnctr_mode_shift = 5, 1406 .n_val_shift = 16, 1407 .m_val_shift = 16, 1408 .width = 16, 1409 }, 1410 .p = { 1411 .pre_div_shift = 3, 1412 .pre_div_width = 2, 1413 }, 1414 .s = { 1415 .src_sel_shift = 0, 1416 .parent_map = gcc_pxo_pll8_map, 1417 }, 1418 .freq_tbl = clk_tbl_tsif_ref, 1419 .clkr = { 1420 .enable_reg = 0x2710, 1421 .enable_mask = BIT(11), 1422 .hw.init = &(struct clk_init_data){ 1423 .name = "tsif_ref_src", 1424 .parent_names = gcc_pxo_pll8, 1425 .num_parents = 2, 1426 .ops = &clk_rcg_ops, 1427 }, 1428 } 1429}; 1430 1431static struct clk_branch tsif_ref_clk = { 1432 .halt_reg = 0x2fd4, 1433 .halt_bit = 5, 1434 .clkr = { 1435 .enable_reg = 0x2710, 1436 .enable_mask = BIT(9), 1437 .hw.init = &(struct clk_init_data){ 1438 .name = "tsif_ref_clk", 1439 .parent_names = (const char *[]){ "tsif_ref_src" }, 1440 .num_parents = 1, 1441 .ops = &clk_branch_ops, 1442 .flags = CLK_SET_RATE_PARENT, 1443 }, 1444 }, 1445}; 1446 1447static struct clk_branch tsif_h_clk = { 1448 .hwcg_reg = 0x2700, 1449 .hwcg_bit = 6, 1450 .halt_reg = 0x2fd4, 1451 .halt_bit = 7, 1452 .clkr = { 1453 .enable_reg = 0x2700, 1454 .enable_mask = BIT(4), 1455 .hw.init = &(struct clk_init_data){ 1456 .name = "tsif_h_clk", 1457 .ops = &clk_branch_ops, 1458 }, 1459 }, 1460}; 1461 1462static struct clk_branch dma_bam_h_clk = { 1463 .hwcg_reg = 0x25c0, 1464 .hwcg_bit = 6, 1465 .halt_reg = 0x2fc8, 1466 .halt_bit = 12, 1467 .clkr = { 1468 .enable_reg = 0x25c0, 1469 .enable_mask = BIT(4), 1470 .hw.init = &(struct clk_init_data){ 1471 .name = "dma_bam_h_clk", 1472 .ops = &clk_branch_ops, 1473 }, 1474 }, 1475}; 1476 1477static struct clk_branch adm0_clk = { 1478 .halt_reg = 0x2fdc, 1479 .halt_check = BRANCH_HALT_VOTED, 1480 .halt_bit = 12, 1481 .clkr = { 1482 .enable_reg = 0x3080, 1483 .enable_mask = BIT(2), 1484 .hw.init = &(struct clk_init_data){ 1485 .name = "adm0_clk", 1486 .ops = &clk_branch_ops, 1487 }, 1488 }, 1489}; 1490 1491static struct clk_branch adm0_pbus_clk = { 1492 .hwcg_reg = 0x2208, 1493 .hwcg_bit = 6, 1494 .halt_reg = 0x2fdc, 1495 .halt_check = BRANCH_HALT_VOTED, 1496 .halt_bit = 11, 1497 .clkr = { 1498 .enable_reg = 0x3080, 1499 .enable_mask = BIT(3), 1500 .hw.init = &(struct clk_init_data){ 1501 .name = "adm0_pbus_clk", 1502 .ops = &clk_branch_ops, 1503 }, 1504 }, 1505}; 1506 1507static struct clk_branch pmic_arb0_h_clk = { 1508 .halt_reg = 0x2fd8, 1509 .halt_check = BRANCH_HALT_VOTED, 1510 .halt_bit = 22, 1511 .clkr = { 1512 .enable_reg = 0x3080, 1513 .enable_mask = BIT(8), 1514 .hw.init = &(struct clk_init_data){ 1515 .name = "pmic_arb0_h_clk", 1516 .ops = &clk_branch_ops, 1517 }, 1518 }, 1519}; 1520 1521static struct clk_branch pmic_arb1_h_clk = { 1522 .halt_reg = 0x2fd8, 1523 .halt_check = BRANCH_HALT_VOTED, 1524 .halt_bit = 21, 1525 .clkr = { 1526 .enable_reg = 0x3080, 1527 .enable_mask = BIT(9), 1528 .hw.init = &(struct clk_init_data){ 1529 .name = "pmic_arb1_h_clk", 1530 .ops = &clk_branch_ops, 1531 }, 1532 }, 1533}; 1534 1535static struct clk_branch pmic_ssbi2_clk = { 1536 .halt_reg = 0x2fd8, 1537 .halt_check = BRANCH_HALT_VOTED, 1538 .halt_bit = 23, 1539 .clkr = { 1540 .enable_reg = 0x3080, 1541 .enable_mask = BIT(7), 1542 .hw.init = &(struct clk_init_data){ 1543 .name = "pmic_ssbi2_clk", 1544 .ops = &clk_branch_ops, 1545 }, 1546 }, 1547}; 1548 1549static struct clk_branch rpm_msg_ram_h_clk = { 1550 .hwcg_reg = 0x27e0, 1551 .hwcg_bit = 6, 1552 .halt_reg = 0x2fd8, 1553 .halt_check = BRANCH_HALT_VOTED, 1554 .halt_bit = 12, 1555 .clkr = { 1556 .enable_reg = 0x3080, 1557 .enable_mask = BIT(6), 1558 .hw.init = &(struct clk_init_data){ 1559 .name = "rpm_msg_ram_h_clk", 1560 .ops = &clk_branch_ops, 1561 }, 1562 }, 1563}; 1564 1565static const struct freq_tbl clk_tbl_pcie_ref[] = { 1566 { 100000000, P_PLL3, 12, 0, 0 }, 1567 { } 1568}; 1569 1570static struct clk_rcg pcie_ref_src = { 1571 .ns_reg = 0x3860, 1572 .p = { 1573 .pre_div_shift = 3, 1574 .pre_div_width = 4, 1575 }, 1576 .s = { 1577 .src_sel_shift = 0, 1578 .parent_map = gcc_pxo_pll3_map, 1579 }, 1580 .freq_tbl = clk_tbl_pcie_ref, 1581 .clkr = { 1582 .enable_reg = 0x3860, 1583 .enable_mask = BIT(11), 1584 .hw.init = &(struct clk_init_data){ 1585 .name = "pcie_ref_src", 1586 .parent_names = gcc_pxo_pll3, 1587 .num_parents = 2, 1588 .ops = &clk_rcg_ops, 1589 .flags = CLK_SET_RATE_GATE, 1590 }, 1591 }, 1592}; 1593 1594static struct clk_branch pcie_ref_src_clk = { 1595 .halt_reg = 0x2fdc, 1596 .halt_bit = 30, 1597 .clkr = { 1598 .enable_reg = 0x3860, 1599 .enable_mask = BIT(9), 1600 .hw.init = &(struct clk_init_data){ 1601 .name = "pcie_ref_src_clk", 1602 .parent_names = (const char *[]){ "pcie_ref_src" }, 1603 .num_parents = 1, 1604 .ops = &clk_branch_ops, 1605 .flags = CLK_SET_RATE_PARENT, 1606 }, 1607 }, 1608}; 1609 1610static struct clk_branch pcie_a_clk = { 1611 .halt_reg = 0x2fc0, 1612 .halt_bit = 13, 1613 .clkr = { 1614 .enable_reg = 0x22c0, 1615 .enable_mask = BIT(4), 1616 .hw.init = &(struct clk_init_data){ 1617 .name = "pcie_a_clk", 1618 .ops = &clk_branch_ops, 1619 }, 1620 }, 1621}; 1622 1623static struct clk_branch pcie_aux_clk = { 1624 .halt_reg = 0x2fdc, 1625 .halt_bit = 31, 1626 .clkr = { 1627 .enable_reg = 0x22c8, 1628 .enable_mask = BIT(4), 1629 .hw.init = &(struct clk_init_data){ 1630 .name = "pcie_aux_clk", 1631 .ops = &clk_branch_ops, 1632 }, 1633 }, 1634}; 1635 1636static struct clk_branch pcie_h_clk = { 1637 .halt_reg = 0x2fd4, 1638 .halt_bit = 8, 1639 .clkr = { 1640 .enable_reg = 0x22cc, 1641 .enable_mask = BIT(4), 1642 .hw.init = &(struct clk_init_data){ 1643 .name = "pcie_h_clk", 1644 .ops = &clk_branch_ops, 1645 }, 1646 }, 1647}; 1648 1649static struct clk_branch pcie_phy_clk = { 1650 .halt_reg = 0x2fdc, 1651 .halt_bit = 29, 1652 .clkr = { 1653 .enable_reg = 0x22d0, 1654 .enable_mask = BIT(4), 1655 .hw.init = &(struct clk_init_data){ 1656 .name = "pcie_phy_clk", 1657 .ops = &clk_branch_ops, 1658 }, 1659 }, 1660}; 1661 1662static struct clk_rcg pcie1_ref_src = { 1663 .ns_reg = 0x3aa0, 1664 .p = { 1665 .pre_div_shift = 3, 1666 .pre_div_width = 4, 1667 }, 1668 .s = { 1669 .src_sel_shift = 0, 1670 .parent_map = gcc_pxo_pll3_map, 1671 }, 1672 .freq_tbl = clk_tbl_pcie_ref, 1673 .clkr = { 1674 .enable_reg = 0x3aa0, 1675 .enable_mask = BIT(11), 1676 .hw.init = &(struct clk_init_data){ 1677 .name = "pcie1_ref_src", 1678 .parent_names = gcc_pxo_pll3, 1679 .num_parents = 2, 1680 .ops = &clk_rcg_ops, 1681 .flags = CLK_SET_RATE_GATE, 1682 }, 1683 }, 1684}; 1685 1686static struct clk_branch pcie1_ref_src_clk = { 1687 .halt_reg = 0x2fdc, 1688 .halt_bit = 27, 1689 .clkr = { 1690 .enable_reg = 0x3aa0, 1691 .enable_mask = BIT(9), 1692 .hw.init = &(struct clk_init_data){ 1693 .name = "pcie1_ref_src_clk", 1694 .parent_names = (const char *[]){ "pcie1_ref_src" }, 1695 .num_parents = 1, 1696 .ops = &clk_branch_ops, 1697 .flags = CLK_SET_RATE_PARENT, 1698 }, 1699 }, 1700}; 1701 1702static struct clk_branch pcie1_a_clk = { 1703 .halt_reg = 0x2fc0, 1704 .halt_bit = 10, 1705 .clkr = { 1706 .enable_reg = 0x3a80, 1707 .enable_mask = BIT(4), 1708 .hw.init = &(struct clk_init_data){ 1709 .name = "pcie1_a_clk", 1710 .ops = &clk_branch_ops, 1711 }, 1712 }, 1713}; 1714 1715static struct clk_branch pcie1_aux_clk = { 1716 .halt_reg = 0x2fdc, 1717 .halt_bit = 28, 1718 .clkr = { 1719 .enable_reg = 0x3a88, 1720 .enable_mask = BIT(4), 1721 .hw.init = &(struct clk_init_data){ 1722 .name = "pcie1_aux_clk", 1723 .ops = &clk_branch_ops, 1724 }, 1725 }, 1726}; 1727 1728static struct clk_branch pcie1_h_clk = { 1729 .halt_reg = 0x2fd4, 1730 .halt_bit = 9, 1731 .clkr = { 1732 .enable_reg = 0x3a8c, 1733 .enable_mask = BIT(4), 1734 .hw.init = &(struct clk_init_data){ 1735 .name = "pcie1_h_clk", 1736 .ops = &clk_branch_ops, 1737 }, 1738 }, 1739}; 1740 1741static struct clk_branch pcie1_phy_clk = { 1742 .halt_reg = 0x2fdc, 1743 .halt_bit = 26, 1744 .clkr = { 1745 .enable_reg = 0x3a90, 1746 .enable_mask = BIT(4), 1747 .hw.init = &(struct clk_init_data){ 1748 .name = "pcie1_phy_clk", 1749 .ops = &clk_branch_ops, 1750 }, 1751 }, 1752}; 1753 1754static struct clk_rcg pcie2_ref_src = { 1755 .ns_reg = 0x3ae0, 1756 .p = { 1757 .pre_div_shift = 3, 1758 .pre_div_width = 4, 1759 }, 1760 .s = { 1761 .src_sel_shift = 0, 1762 .parent_map = gcc_pxo_pll3_map, 1763 }, 1764 .freq_tbl = clk_tbl_pcie_ref, 1765 .clkr = { 1766 .enable_reg = 0x3ae0, 1767 .enable_mask = BIT(11), 1768 .hw.init = &(struct clk_init_data){ 1769 .name = "pcie2_ref_src", 1770 .parent_names = gcc_pxo_pll3, 1771 .num_parents = 2, 1772 .ops = &clk_rcg_ops, 1773 .flags = CLK_SET_RATE_GATE, 1774 }, 1775 }, 1776}; 1777 1778static struct clk_branch pcie2_ref_src_clk = { 1779 .halt_reg = 0x2fdc, 1780 .halt_bit = 24, 1781 .clkr = { 1782 .enable_reg = 0x3ae0, 1783 .enable_mask = BIT(9), 1784 .hw.init = &(struct clk_init_data){ 1785 .name = "pcie2_ref_src_clk", 1786 .parent_names = (const char *[]){ "pcie2_ref_src" }, 1787 .num_parents = 1, 1788 .ops = &clk_branch_ops, 1789 .flags = CLK_SET_RATE_PARENT, 1790 }, 1791 }, 1792}; 1793 1794static struct clk_branch pcie2_a_clk = { 1795 .halt_reg = 0x2fc0, 1796 .halt_bit = 9, 1797 .clkr = { 1798 .enable_reg = 0x3ac0, 1799 .enable_mask = BIT(4), 1800 .hw.init = &(struct clk_init_data){ 1801 .name = "pcie2_a_clk", 1802 .ops = &clk_branch_ops, 1803 }, 1804 }, 1805}; 1806 1807static struct clk_branch pcie2_aux_clk = { 1808 .halt_reg = 0x2fdc, 1809 .halt_bit = 25, 1810 .clkr = { 1811 .enable_reg = 0x3ac8, 1812 .enable_mask = BIT(4), 1813 .hw.init = &(struct clk_init_data){ 1814 .name = "pcie2_aux_clk", 1815 .ops = &clk_branch_ops, 1816 }, 1817 }, 1818}; 1819 1820static struct clk_branch pcie2_h_clk = { 1821 .halt_reg = 0x2fd4, 1822 .halt_bit = 10, 1823 .clkr = { 1824 .enable_reg = 0x3acc, 1825 .enable_mask = BIT(4), 1826 .hw.init = &(struct clk_init_data){ 1827 .name = "pcie2_h_clk", 1828 .ops = &clk_branch_ops, 1829 }, 1830 }, 1831}; 1832 1833static struct clk_branch pcie2_phy_clk = { 1834 .halt_reg = 0x2fdc, 1835 .halt_bit = 23, 1836 .clkr = { 1837 .enable_reg = 0x3ad0, 1838 .enable_mask = BIT(4), 1839 .hw.init = &(struct clk_init_data){ 1840 .name = "pcie2_phy_clk", 1841 .ops = &clk_branch_ops, 1842 }, 1843 }, 1844}; 1845 1846static const struct freq_tbl clk_tbl_sata_ref[] = { 1847 { 100000000, P_PLL3, 12, 0, 0 }, 1848 { } 1849}; 1850 1851static struct clk_rcg sata_ref_src = { 1852 .ns_reg = 0x2c08, 1853 .p = { 1854 .pre_div_shift = 3, 1855 .pre_div_width = 4, 1856 }, 1857 .s = { 1858 .src_sel_shift = 0, 1859 .parent_map = gcc_pxo_pll3_sata_map, 1860 }, 1861 .freq_tbl = clk_tbl_sata_ref, 1862 .clkr = { 1863 .enable_reg = 0x2c08, 1864 .enable_mask = BIT(7), 1865 .hw.init = &(struct clk_init_data){ 1866 .name = "sata_ref_src", 1867 .parent_names = gcc_pxo_pll3, 1868 .num_parents = 2, 1869 .ops = &clk_rcg_ops, 1870 .flags = CLK_SET_RATE_GATE, 1871 }, 1872 }, 1873}; 1874 1875static struct clk_branch sata_rxoob_clk = { 1876 .halt_reg = 0x2fdc, 1877 .halt_bit = 20, 1878 .clkr = { 1879 .enable_reg = 0x2c0c, 1880 .enable_mask = BIT(4), 1881 .hw.init = &(struct clk_init_data){ 1882 .name = "sata_rxoob_clk", 1883 .parent_names = (const char *[]){ "sata_ref_src" }, 1884 .num_parents = 1, 1885 .ops = &clk_branch_ops, 1886 .flags = CLK_SET_RATE_PARENT, 1887 }, 1888 }, 1889}; 1890 1891static struct clk_branch sata_pmalive_clk = { 1892 .halt_reg = 0x2fdc, 1893 .halt_bit = 19, 1894 .clkr = { 1895 .enable_reg = 0x2c10, 1896 .enable_mask = BIT(4), 1897 .hw.init = &(struct clk_init_data){ 1898 .name = "sata_pmalive_clk", 1899 .parent_names = (const char *[]){ "sata_ref_src" }, 1900 .num_parents = 1, 1901 .ops = &clk_branch_ops, 1902 .flags = CLK_SET_RATE_PARENT, 1903 }, 1904 }, 1905}; 1906 1907static struct clk_branch sata_phy_ref_clk = { 1908 .halt_reg = 0x2fdc, 1909 .halt_bit = 18, 1910 .clkr = { 1911 .enable_reg = 0x2c14, 1912 .enable_mask = BIT(4), 1913 .hw.init = &(struct clk_init_data){ 1914 .name = "sata_phy_ref_clk", 1915 .parent_names = (const char *[]){ "pxo" }, 1916 .num_parents = 1, 1917 .ops = &clk_branch_ops, 1918 }, 1919 }, 1920}; 1921 1922static struct clk_branch sata_a_clk = { 1923 .halt_reg = 0x2fc0, 1924 .halt_bit = 12, 1925 .clkr = { 1926 .enable_reg = 0x2c20, 1927 .enable_mask = BIT(4), 1928 .hw.init = &(struct clk_init_data){ 1929 .name = "sata_a_clk", 1930 .ops = &clk_branch_ops, 1931 }, 1932 }, 1933}; 1934 1935static struct clk_branch sata_h_clk = { 1936 .halt_reg = 0x2fdc, 1937 .halt_bit = 21, 1938 .clkr = { 1939 .enable_reg = 0x2c00, 1940 .enable_mask = BIT(4), 1941 .hw.init = &(struct clk_init_data){ 1942 .name = "sata_h_clk", 1943 .ops = &clk_branch_ops, 1944 }, 1945 }, 1946}; 1947 1948static struct clk_branch sfab_sata_s_h_clk = { 1949 .halt_reg = 0x2fc4, 1950 .halt_bit = 14, 1951 .clkr = { 1952 .enable_reg = 0x2480, 1953 .enable_mask = BIT(4), 1954 .hw.init = &(struct clk_init_data){ 1955 .name = "sfab_sata_s_h_clk", 1956 .ops = &clk_branch_ops, 1957 }, 1958 }, 1959}; 1960 1961static struct clk_branch sata_phy_cfg_clk = { 1962 .halt_reg = 0x2fcc, 1963 .halt_bit = 14, 1964 .clkr = { 1965 .enable_reg = 0x2c40, 1966 .enable_mask = BIT(4), 1967 .hw.init = &(struct clk_init_data){ 1968 .name = "sata_phy_cfg_clk", 1969 .ops = &clk_branch_ops, 1970 }, 1971 }, 1972}; 1973 1974static const struct freq_tbl clk_tbl_usb30_master[] = { 1975 { 125000000, P_PLL0, 1, 5, 32 }, 1976 { } 1977}; 1978 1979static struct clk_rcg usb30_master_clk_src = { 1980 .ns_reg = 0x3b2c, 1981 .md_reg = 0x3b28, 1982 .mn = { 1983 .mnctr_en_bit = 8, 1984 .mnctr_reset_bit = 7, 1985 .mnctr_mode_shift = 5, 1986 .n_val_shift = 16, 1987 .m_val_shift = 16, 1988 .width = 8, 1989 }, 1990 .p = { 1991 .pre_div_shift = 3, 1992 .pre_div_width = 2, 1993 }, 1994 .s = { 1995 .src_sel_shift = 0, 1996 .parent_map = gcc_pxo_pll8_pll0, 1997 }, 1998 .freq_tbl = clk_tbl_usb30_master, 1999 .clkr = { 2000 .enable_reg = 0x3b2c, 2001 .enable_mask = BIT(11), 2002 .hw.init = &(struct clk_init_data){ 2003 .name = "usb30_master_ref_src", 2004 .parent_names = gcc_pxo_pll8_pll0_map, 2005 .num_parents = 3, 2006 .ops = &clk_rcg_ops, 2007 .flags = CLK_SET_RATE_GATE, 2008 }, 2009 }, 2010}; 2011 2012static struct clk_branch usb30_0_branch_clk = { 2013 .halt_reg = 0x2fc4, 2014 .halt_bit = 22, 2015 .clkr = { 2016 .enable_reg = 0x3b24, 2017 .enable_mask = BIT(4), 2018 .hw.init = &(struct clk_init_data){ 2019 .name = "usb30_0_branch_clk", 2020 .parent_names = (const char *[]){ "usb30_master_ref_src", }, 2021 .num_parents = 1, 2022 .ops = &clk_branch_ops, 2023 .flags = CLK_SET_RATE_PARENT, 2024 }, 2025 }, 2026}; 2027 2028static struct clk_branch usb30_1_branch_clk = { 2029 .halt_reg = 0x2fc4, 2030 .halt_bit = 17, 2031 .clkr = { 2032 .enable_reg = 0x3b34, 2033 .enable_mask = BIT(4), 2034 .hw.init = &(struct clk_init_data){ 2035 .name = "usb30_1_branch_clk", 2036 .parent_names = (const char *[]){ "usb30_master_ref_src", }, 2037 .num_parents = 1, 2038 .ops = &clk_branch_ops, 2039 .flags = CLK_SET_RATE_PARENT, 2040 }, 2041 }, 2042}; 2043 2044static const struct freq_tbl clk_tbl_usb30_utmi[] = { 2045 { 60000000, P_PLL8, 1, 5, 32 }, 2046 { } 2047}; 2048 2049static struct clk_rcg usb30_utmi_clk = { 2050 .ns_reg = 0x3b44, 2051 .md_reg = 0x3b40, 2052 .mn = { 2053 .mnctr_en_bit = 8, 2054 .mnctr_reset_bit = 7, 2055 .mnctr_mode_shift = 5, 2056 .n_val_shift = 16, 2057 .m_val_shift = 16, 2058 .width = 8, 2059 }, 2060 .p = { 2061 .pre_div_shift = 3, 2062 .pre_div_width = 2, 2063 }, 2064 .s = { 2065 .src_sel_shift = 0, 2066 .parent_map = gcc_pxo_pll8_pll0, 2067 }, 2068 .freq_tbl = clk_tbl_usb30_utmi, 2069 .clkr = { 2070 .enable_reg = 0x3b44, 2071 .enable_mask = BIT(11), 2072 .hw.init = &(struct clk_init_data){ 2073 .name = "usb30_utmi_clk", 2074 .parent_names = gcc_pxo_pll8_pll0_map, 2075 .num_parents = 3, 2076 .ops = &clk_rcg_ops, 2077 .flags = CLK_SET_RATE_GATE, 2078 }, 2079 }, 2080}; 2081 2082static struct clk_branch usb30_0_utmi_clk_ctl = { 2083 .halt_reg = 0x2fc4, 2084 .halt_bit = 21, 2085 .clkr = { 2086 .enable_reg = 0x3b48, 2087 .enable_mask = BIT(4), 2088 .hw.init = &(struct clk_init_data){ 2089 .name = "usb30_0_utmi_clk_ctl", 2090 .parent_names = (const char *[]){ "usb30_utmi_clk", }, 2091 .num_parents = 1, 2092 .ops = &clk_branch_ops, 2093 .flags = CLK_SET_RATE_PARENT, 2094 }, 2095 }, 2096}; 2097 2098static struct clk_branch usb30_1_utmi_clk_ctl = { 2099 .halt_reg = 0x2fc4, 2100 .halt_bit = 15, 2101 .clkr = { 2102 .enable_reg = 0x3b4c, 2103 .enable_mask = BIT(4), 2104 .hw.init = &(struct clk_init_data){ 2105 .name = "usb30_1_utmi_clk_ctl", 2106 .parent_names = (const char *[]){ "usb30_utmi_clk", }, 2107 .num_parents = 1, 2108 .ops = &clk_branch_ops, 2109 .flags = CLK_SET_RATE_PARENT, 2110 }, 2111 }, 2112}; 2113 2114static const struct freq_tbl clk_tbl_usb[] = { 2115 { 60000000, P_PLL8, 1, 5, 32 }, 2116 { } 2117}; 2118 2119static struct clk_rcg usb_hs1_xcvr_clk_src = { 2120 .ns_reg = 0x290C, 2121 .md_reg = 0x2908, 2122 .mn = { 2123 .mnctr_en_bit = 8, 2124 .mnctr_reset_bit = 7, 2125 .mnctr_mode_shift = 5, 2126 .n_val_shift = 16, 2127 .m_val_shift = 16, 2128 .width = 8, 2129 }, 2130 .p = { 2131 .pre_div_shift = 3, 2132 .pre_div_width = 2, 2133 }, 2134 .s = { 2135 .src_sel_shift = 0, 2136 .parent_map = gcc_pxo_pll8_pll0, 2137 }, 2138 .freq_tbl = clk_tbl_usb, 2139 .clkr = { 2140 .enable_reg = 0x2968, 2141 .enable_mask = BIT(11), 2142 .hw.init = &(struct clk_init_data){ 2143 .name = "usb_hs1_xcvr_src", 2144 .parent_names = gcc_pxo_pll8_pll0_map, 2145 .num_parents = 3, 2146 .ops = &clk_rcg_ops, 2147 .flags = CLK_SET_RATE_GATE, 2148 }, 2149 }, 2150}; 2151 2152static struct clk_branch usb_hs1_xcvr_clk = { 2153 .halt_reg = 0x2fcc, 2154 .halt_bit = 17, 2155 .clkr = { 2156 .enable_reg = 0x290c, 2157 .enable_mask = BIT(9), 2158 .hw.init = &(struct clk_init_data){ 2159 .name = "usb_hs1_xcvr_clk", 2160 .parent_names = (const char *[]){ "usb_hs1_xcvr_src" }, 2161 .num_parents = 1, 2162 .ops = &clk_branch_ops, 2163 .flags = CLK_SET_RATE_PARENT, 2164 }, 2165 }, 2166}; 2167 2168static struct clk_branch usb_hs1_h_clk = { 2169 .hwcg_reg = 0x2900, 2170 .hwcg_bit = 6, 2171 .halt_reg = 0x2fc8, 2172 .halt_bit = 1, 2173 .clkr = { 2174 .enable_reg = 0x2900, 2175 .enable_mask = BIT(4), 2176 .hw.init = &(struct clk_init_data){ 2177 .name = "usb_hs1_h_clk", 2178 .ops = &clk_branch_ops, 2179 }, 2180 }, 2181}; 2182 2183static struct clk_rcg usb_fs1_xcvr_clk_src = { 2184 .ns_reg = 0x2968, 2185 .md_reg = 0x2964, 2186 .mn = { 2187 .mnctr_en_bit = 8, 2188 .mnctr_reset_bit = 7, 2189 .mnctr_mode_shift = 5, 2190 .n_val_shift = 16, 2191 .m_val_shift = 16, 2192 .width = 8, 2193 }, 2194 .p = { 2195 .pre_div_shift = 3, 2196 .pre_div_width = 2, 2197 }, 2198 .s = { 2199 .src_sel_shift = 0, 2200 .parent_map = gcc_pxo_pll8_pll0, 2201 }, 2202 .freq_tbl = clk_tbl_usb, 2203 .clkr = { 2204 .enable_reg = 0x2968, 2205 .enable_mask = BIT(11), 2206 .hw.init = &(struct clk_init_data){ 2207 .name = "usb_fs1_xcvr_src", 2208 .parent_names = gcc_pxo_pll8_pll0_map, 2209 .num_parents = 3, 2210 .ops = &clk_rcg_ops, 2211 .flags = CLK_SET_RATE_GATE, 2212 }, 2213 }, 2214}; 2215 2216static struct clk_branch usb_fs1_xcvr_clk = { 2217 .halt_reg = 0x2fcc, 2218 .halt_bit = 17, 2219 .clkr = { 2220 .enable_reg = 0x2968, 2221 .enable_mask = BIT(9), 2222 .hw.init = &(struct clk_init_data){ 2223 .name = "usb_fs1_xcvr_clk", 2224 .parent_names = (const char *[]){ "usb_fs1_xcvr_src", }, 2225 .num_parents = 1, 2226 .ops = &clk_branch_ops, 2227 .flags = CLK_SET_RATE_PARENT, 2228 }, 2229 }, 2230}; 2231 2232static struct clk_branch usb_fs1_sys_clk = { 2233 .halt_reg = 0x2fcc, 2234 .halt_bit = 18, 2235 .clkr = { 2236 .enable_reg = 0x296c, 2237 .enable_mask = BIT(4), 2238 .hw.init = &(struct clk_init_data){ 2239 .name = "usb_fs1_sys_clk", 2240 .parent_names = (const char *[]){ "usb_fs1_xcvr_src", }, 2241 .num_parents = 1, 2242 .ops = &clk_branch_ops, 2243 .flags = CLK_SET_RATE_PARENT, 2244 }, 2245 }, 2246}; 2247 2248static struct clk_branch usb_fs1_h_clk = { 2249 .halt_reg = 0x2fcc, 2250 .halt_bit = 19, 2251 .clkr = { 2252 .enable_reg = 0x2960, 2253 .enable_mask = BIT(4), 2254 .hw.init = &(struct clk_init_data){ 2255 .name = "usb_fs1_h_clk", 2256 .ops = &clk_branch_ops, 2257 }, 2258 }, 2259}; 2260 2261static struct clk_branch ebi2_clk = { 2262 .hwcg_reg = 0x3b00, 2263 .hwcg_bit = 6, 2264 .halt_reg = 0x2fcc, 2265 .halt_bit = 1, 2266 .clkr = { 2267 .enable_reg = 0x3b00, 2268 .enable_mask = BIT(4), 2269 .hw.init = &(struct clk_init_data){ 2270 .name = "ebi2_clk", 2271 .ops = &clk_branch_ops, 2272 }, 2273 }, 2274}; 2275 2276static struct clk_branch ebi2_aon_clk = { 2277 .halt_reg = 0x2fcc, 2278 .halt_bit = 0, 2279 .clkr = { 2280 .enable_reg = 0x3b00, 2281 .enable_mask = BIT(8), 2282 .hw.init = &(struct clk_init_data){ 2283 .name = "ebi2_always_on_clk", 2284 .ops = &clk_branch_ops, 2285 }, 2286 }, 2287}; 2288 2289static const struct freq_tbl clk_tbl_gmac[] = { 2290 { 133000000, P_PLL0, 1, 50, 301 }, 2291 { 266000000, P_PLL0, 1, 127, 382 }, 2292 { } 2293}; 2294 2295static struct clk_dyn_rcg gmac_core1_src = { 2296 .ns_reg[0] = 0x3cac, 2297 .ns_reg[1] = 0x3cb0, 2298 .md_reg[0] = 0x3ca4, 2299 .md_reg[1] = 0x3ca8, 2300 .bank_reg = 0x3ca0, 2301 .mn[0] = { 2302 .mnctr_en_bit = 8, 2303 .mnctr_reset_bit = 7, 2304 .mnctr_mode_shift = 5, 2305 .n_val_shift = 16, 2306 .m_val_shift = 16, 2307 .width = 8, 2308 }, 2309 .mn[1] = { 2310 .mnctr_en_bit = 8, 2311 .mnctr_reset_bit = 7, 2312 .mnctr_mode_shift = 5, 2313 .n_val_shift = 16, 2314 .m_val_shift = 16, 2315 .width = 8, 2316 }, 2317 .s[0] = { 2318 .src_sel_shift = 0, 2319 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map, 2320 }, 2321 .s[1] = { 2322 .src_sel_shift = 0, 2323 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map, 2324 }, 2325 .p[0] = { 2326 .pre_div_shift = 3, 2327 .pre_div_width = 2, 2328 }, 2329 .p[1] = { 2330 .pre_div_shift = 3, 2331 .pre_div_width = 2, 2332 }, 2333 .mux_sel_bit = 0, 2334 .freq_tbl = clk_tbl_gmac, 2335 .clkr = { 2336 .enable_reg = 0x3ca0, 2337 .enable_mask = BIT(1), 2338 .hw.init = &(struct clk_init_data){ 2339 .name = "gmac_core1_src", 2340 .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, 2341 .num_parents = 5, 2342 .ops = &clk_dyn_rcg_ops, 2343 }, 2344 }, 2345}; 2346 2347static struct clk_branch gmac_core1_clk = { 2348 .halt_reg = 0x3c20, 2349 .halt_bit = 4, 2350 .hwcg_reg = 0x3cb4, 2351 .hwcg_bit = 6, 2352 .clkr = { 2353 .enable_reg = 0x3cb4, 2354 .enable_mask = BIT(4), 2355 .hw.init = &(struct clk_init_data){ 2356 .name = "gmac_core1_clk", 2357 .parent_names = (const char *[]){ 2358 "gmac_core1_src", 2359 }, 2360 .num_parents = 1, 2361 .ops = &clk_branch_ops, 2362 .flags = CLK_SET_RATE_PARENT, 2363 }, 2364 }, 2365}; 2366 2367static struct clk_dyn_rcg gmac_core2_src = { 2368 .ns_reg[0] = 0x3ccc, 2369 .ns_reg[1] = 0x3cd0, 2370 .md_reg[0] = 0x3cc4, 2371 .md_reg[1] = 0x3cc8, 2372 .bank_reg = 0x3ca0, 2373 .mn[0] = { 2374 .mnctr_en_bit = 8, 2375 .mnctr_reset_bit = 7, 2376 .mnctr_mode_shift = 5, 2377 .n_val_shift = 16, 2378 .m_val_shift = 16, 2379 .width = 8, 2380 }, 2381 .mn[1] = { 2382 .mnctr_en_bit = 8, 2383 .mnctr_reset_bit = 7, 2384 .mnctr_mode_shift = 5, 2385 .n_val_shift = 16, 2386 .m_val_shift = 16, 2387 .width = 8, 2388 }, 2389 .s[0] = { 2390 .src_sel_shift = 0, 2391 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map, 2392 }, 2393 .s[1] = { 2394 .src_sel_shift = 0, 2395 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map, 2396 }, 2397 .p[0] = { 2398 .pre_div_shift = 3, 2399 .pre_div_width = 2, 2400 }, 2401 .p[1] = { 2402 .pre_div_shift = 3, 2403 .pre_div_width = 2, 2404 }, 2405 .mux_sel_bit = 0, 2406 .freq_tbl = clk_tbl_gmac, 2407 .clkr = { 2408 .enable_reg = 0x3cc0, 2409 .enable_mask = BIT(1), 2410 .hw.init = &(struct clk_init_data){ 2411 .name = "gmac_core2_src", 2412 .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, 2413 .num_parents = 5, 2414 .ops = &clk_dyn_rcg_ops, 2415 }, 2416 }, 2417}; 2418 2419static struct clk_branch gmac_core2_clk = { 2420 .halt_reg = 0x3c20, 2421 .halt_bit = 5, 2422 .hwcg_reg = 0x3cd4, 2423 .hwcg_bit = 6, 2424 .clkr = { 2425 .enable_reg = 0x3cd4, 2426 .enable_mask = BIT(4), 2427 .hw.init = &(struct clk_init_data){ 2428 .name = "gmac_core2_clk", 2429 .parent_names = (const char *[]){ 2430 "gmac_core2_src", 2431 }, 2432 .num_parents = 1, 2433 .ops = &clk_branch_ops, 2434 .flags = CLK_SET_RATE_PARENT, 2435 }, 2436 }, 2437}; 2438 2439static struct clk_dyn_rcg gmac_core3_src = { 2440 .ns_reg[0] = 0x3cec, 2441 .ns_reg[1] = 0x3cf0, 2442 .md_reg[0] = 0x3ce4, 2443 .md_reg[1] = 0x3ce8, 2444 .bank_reg = 0x3ce0, 2445 .mn[0] = { 2446 .mnctr_en_bit = 8, 2447 .mnctr_reset_bit = 7, 2448 .mnctr_mode_shift = 5, 2449 .n_val_shift = 16, 2450 .m_val_shift = 16, 2451 .width = 8, 2452 }, 2453 .mn[1] = { 2454 .mnctr_en_bit = 8, 2455 .mnctr_reset_bit = 7, 2456 .mnctr_mode_shift = 5, 2457 .n_val_shift = 16, 2458 .m_val_shift = 16, 2459 .width = 8, 2460 }, 2461 .s[0] = { 2462 .src_sel_shift = 0, 2463 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map, 2464 }, 2465 .s[1] = { 2466 .src_sel_shift = 0, 2467 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map, 2468 }, 2469 .p[0] = { 2470 .pre_div_shift = 3, 2471 .pre_div_width = 2, 2472 }, 2473 .p[1] = { 2474 .pre_div_shift = 3, 2475 .pre_div_width = 2, 2476 }, 2477 .mux_sel_bit = 0, 2478 .freq_tbl = clk_tbl_gmac, 2479 .clkr = { 2480 .enable_reg = 0x3ce0, 2481 .enable_mask = BIT(1), 2482 .hw.init = &(struct clk_init_data){ 2483 .name = "gmac_core3_src", 2484 .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, 2485 .num_parents = 5, 2486 .ops = &clk_dyn_rcg_ops, 2487 }, 2488 }, 2489}; 2490 2491static struct clk_branch gmac_core3_clk = { 2492 .halt_reg = 0x3c20, 2493 .halt_bit = 6, 2494 .hwcg_reg = 0x3cf4, 2495 .hwcg_bit = 6, 2496 .clkr = { 2497 .enable_reg = 0x3cf4, 2498 .enable_mask = BIT(4), 2499 .hw.init = &(struct clk_init_data){ 2500 .name = "gmac_core3_clk", 2501 .parent_names = (const char *[]){ 2502 "gmac_core3_src", 2503 }, 2504 .num_parents = 1, 2505 .ops = &clk_branch_ops, 2506 .flags = CLK_SET_RATE_PARENT, 2507 }, 2508 }, 2509}; 2510 2511static struct clk_dyn_rcg gmac_core4_src = { 2512 .ns_reg[0] = 0x3d0c, 2513 .ns_reg[1] = 0x3d10, 2514 .md_reg[0] = 0x3d04, 2515 .md_reg[1] = 0x3d08, 2516 .bank_reg = 0x3d00, 2517 .mn[0] = { 2518 .mnctr_en_bit = 8, 2519 .mnctr_reset_bit = 7, 2520 .mnctr_mode_shift = 5, 2521 .n_val_shift = 16, 2522 .m_val_shift = 16, 2523 .width = 8, 2524 }, 2525 .mn[1] = { 2526 .mnctr_en_bit = 8, 2527 .mnctr_reset_bit = 7, 2528 .mnctr_mode_shift = 5, 2529 .n_val_shift = 16, 2530 .m_val_shift = 16, 2531 .width = 8, 2532 }, 2533 .s[0] = { 2534 .src_sel_shift = 0, 2535 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map, 2536 }, 2537 .s[1] = { 2538 .src_sel_shift = 0, 2539 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map, 2540 }, 2541 .p[0] = { 2542 .pre_div_shift = 3, 2543 .pre_div_width = 2, 2544 }, 2545 .p[1] = { 2546 .pre_div_shift = 3, 2547 .pre_div_width = 2, 2548 }, 2549 .mux_sel_bit = 0, 2550 .freq_tbl = clk_tbl_gmac, 2551 .clkr = { 2552 .enable_reg = 0x3d00, 2553 .enable_mask = BIT(1), 2554 .hw.init = &(struct clk_init_data){ 2555 .name = "gmac_core4_src", 2556 .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, 2557 .num_parents = 5, 2558 .ops = &clk_dyn_rcg_ops, 2559 }, 2560 }, 2561}; 2562 2563static struct clk_branch gmac_core4_clk = { 2564 .halt_reg = 0x3c20, 2565 .halt_bit = 7, 2566 .hwcg_reg = 0x3d14, 2567 .hwcg_bit = 6, 2568 .clkr = { 2569 .enable_reg = 0x3d14, 2570 .enable_mask = BIT(4), 2571 .hw.init = &(struct clk_init_data){ 2572 .name = "gmac_core4_clk", 2573 .parent_names = (const char *[]){ 2574 "gmac_core4_src", 2575 }, 2576 .num_parents = 1, 2577 .ops = &clk_branch_ops, 2578 .flags = CLK_SET_RATE_PARENT, 2579 }, 2580 }, 2581}; 2582 2583static const struct freq_tbl clk_tbl_nss_tcm[] = { 2584 { 266000000, P_PLL0, 3, 0, 0 }, 2585 { 400000000, P_PLL0, 2, 0, 0 }, 2586 { } 2587}; 2588 2589static struct clk_dyn_rcg nss_tcm_src = { 2590 .ns_reg[0] = 0x3dc4, 2591 .ns_reg[1] = 0x3dc8, 2592 .bank_reg = 0x3dc0, 2593 .s[0] = { 2594 .src_sel_shift = 0, 2595 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map, 2596 }, 2597 .s[1] = { 2598 .src_sel_shift = 0, 2599 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map, 2600 }, 2601 .p[0] = { 2602 .pre_div_shift = 3, 2603 .pre_div_width = 4, 2604 }, 2605 .p[1] = { 2606 .pre_div_shift = 3, 2607 .pre_div_width = 4, 2608 }, 2609 .mux_sel_bit = 0, 2610 .freq_tbl = clk_tbl_nss_tcm, 2611 .clkr = { 2612 .enable_reg = 0x3dc0, 2613 .enable_mask = BIT(1), 2614 .hw.init = &(struct clk_init_data){ 2615 .name = "nss_tcm_src", 2616 .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, 2617 .num_parents = 5, 2618 .ops = &clk_dyn_rcg_ops, 2619 }, 2620 }, 2621}; 2622 2623static struct clk_branch nss_tcm_clk = { 2624 .halt_reg = 0x3c20, 2625 .halt_bit = 14, 2626 .clkr = { 2627 .enable_reg = 0x3dd0, 2628 .enable_mask = BIT(6) | BIT(4), 2629 .hw.init = &(struct clk_init_data){ 2630 .name = "nss_tcm_clk", 2631 .parent_names = (const char *[]){ 2632 "nss_tcm_src", 2633 }, 2634 .num_parents = 1, 2635 .ops = &clk_branch_ops, 2636 .flags = CLK_SET_RATE_PARENT, 2637 }, 2638 }, 2639}; 2640 2641static const struct freq_tbl clk_tbl_nss[] = { 2642 { 110000000, P_PLL18, 1, 1, 5 }, 2643 { 275000000, P_PLL18, 2, 0, 0 }, 2644 { 550000000, P_PLL18, 1, 0, 0 }, 2645 { 733000000, P_PLL18, 1, 0, 0 }, 2646 { } 2647}; 2648 2649static struct clk_dyn_rcg ubi32_core1_src_clk = { 2650 .ns_reg[0] = 0x3d2c, 2651 .ns_reg[1] = 0x3d30, 2652 .md_reg[0] = 0x3d24, 2653 .md_reg[1] = 0x3d28, 2654 .bank_reg = 0x3d20, 2655 .mn[0] = { 2656 .mnctr_en_bit = 8, 2657 .mnctr_reset_bit = 7, 2658 .mnctr_mode_shift = 5, 2659 .n_val_shift = 16, 2660 .m_val_shift = 16, 2661 .width = 8, 2662 }, 2663 .mn[1] = { 2664 .mnctr_en_bit = 8, 2665 .mnctr_reset_bit = 7, 2666 .mnctr_mode_shift = 5, 2667 .n_val_shift = 16, 2668 .m_val_shift = 16, 2669 .width = 8, 2670 }, 2671 .s[0] = { 2672 .src_sel_shift = 0, 2673 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map, 2674 }, 2675 .s[1] = { 2676 .src_sel_shift = 0, 2677 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map, 2678 }, 2679 .p[0] = { 2680 .pre_div_shift = 3, 2681 .pre_div_width = 2, 2682 }, 2683 .p[1] = { 2684 .pre_div_shift = 3, 2685 .pre_div_width = 2, 2686 }, 2687 .mux_sel_bit = 0, 2688 .freq_tbl = clk_tbl_nss, 2689 .clkr = { 2690 .enable_reg = 0x3d20, 2691 .enable_mask = BIT(1), 2692 .hw.init = &(struct clk_init_data){ 2693 .name = "ubi32_core1_src_clk", 2694 .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, 2695 .num_parents = 5, 2696 .ops = &clk_dyn_rcg_ops, 2697 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, 2698 }, 2699 }, 2700}; 2701 2702static struct clk_dyn_rcg ubi32_core2_src_clk = { 2703 .ns_reg[0] = 0x3d4c, 2704 .ns_reg[1] = 0x3d50, 2705 .md_reg[0] = 0x3d44, 2706 .md_reg[1] = 0x3d48, 2707 .bank_reg = 0x3d40, 2708 .mn[0] = { 2709 .mnctr_en_bit = 8, 2710 .mnctr_reset_bit = 7, 2711 .mnctr_mode_shift = 5, 2712 .n_val_shift = 16, 2713 .m_val_shift = 16, 2714 .width = 8, 2715 }, 2716 .mn[1] = { 2717 .mnctr_en_bit = 8, 2718 .mnctr_reset_bit = 7, 2719 .mnctr_mode_shift = 5, 2720 .n_val_shift = 16, 2721 .m_val_shift = 16, 2722 .width = 8, 2723 }, 2724 .s[0] = { 2725 .src_sel_shift = 0, 2726 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map, 2727 }, 2728 .s[1] = { 2729 .src_sel_shift = 0, 2730 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map, 2731 }, 2732 .p[0] = { 2733 .pre_div_shift = 3, 2734 .pre_div_width = 2, 2735 }, 2736 .p[1] = { 2737 .pre_div_shift = 3, 2738 .pre_div_width = 2, 2739 }, 2740 .mux_sel_bit = 0, 2741 .freq_tbl = clk_tbl_nss, 2742 .clkr = { 2743 .enable_reg = 0x3d40, 2744 .enable_mask = BIT(1), 2745 .hw.init = &(struct clk_init_data){ 2746 .name = "ubi32_core2_src_clk", 2747 .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, 2748 .num_parents = 5, 2749 .ops = &clk_dyn_rcg_ops, 2750 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, 2751 }, 2752 }, 2753}; 2754 2755static struct clk_regmap *gcc_ipq806x_clks[] = { 2756 [PLL0] = &pll0.clkr, 2757 [PLL0_VOTE] = &pll0_vote, 2758 [PLL3] = &pll3.clkr, 2759 [PLL4_VOTE] = &pll4_vote, 2760 [PLL8] = &pll8.clkr, 2761 [PLL8_VOTE] = &pll8_vote, 2762 [PLL14] = &pll14.clkr, 2763 [PLL14_VOTE] = &pll14_vote, 2764 [PLL18] = &pll18.clkr, 2765 [GSBI1_UART_SRC] = &gsbi1_uart_src.clkr, 2766 [GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr, 2767 [GSBI2_UART_SRC] = &gsbi2_uart_src.clkr, 2768 [GSBI2_UART_CLK] = &gsbi2_uart_clk.clkr, 2769 [GSBI4_UART_SRC] = &gsbi4_uart_src.clkr, 2770 [GSBI4_UART_CLK] = &gsbi4_uart_clk.clkr, 2771 [GSBI5_UART_SRC] = &gsbi5_uart_src.clkr, 2772 [GSBI5_UART_CLK] = &gsbi5_uart_clk.clkr, 2773 [GSBI6_UART_SRC] = &gsbi6_uart_src.clkr, 2774 [GSBI6_UART_CLK] = &gsbi6_uart_clk.clkr, 2775 [GSBI7_UART_SRC] = &gsbi7_uart_src.clkr, 2776 [GSBI7_UART_CLK] = &gsbi7_uart_clk.clkr, 2777 [GSBI1_QUP_SRC] = &gsbi1_qup_src.clkr, 2778 [GSBI1_QUP_CLK] = &gsbi1_qup_clk.clkr, 2779 [GSBI2_QUP_SRC] = &gsbi2_qup_src.clkr, 2780 [GSBI2_QUP_CLK] = &gsbi2_qup_clk.clkr, 2781 [GSBI4_QUP_SRC] = &gsbi4_qup_src.clkr, 2782 [GSBI4_QUP_CLK] = &gsbi4_qup_clk.clkr, 2783 [GSBI5_QUP_SRC] = &gsbi5_qup_src.clkr, 2784 [GSBI5_QUP_CLK] = &gsbi5_qup_clk.clkr, 2785 [GSBI6_QUP_SRC] = &gsbi6_qup_src.clkr, 2786 [GSBI6_QUP_CLK] = &gsbi6_qup_clk.clkr, 2787 [GSBI7_QUP_SRC] = &gsbi7_qup_src.clkr, 2788 [GSBI7_QUP_CLK] = &gsbi7_qup_clk.clkr, 2789 [GP0_SRC] = &gp0_src.clkr, 2790 [GP0_CLK] = &gp0_clk.clkr, 2791 [GP1_SRC] = &gp1_src.clkr, 2792 [GP1_CLK] = &gp1_clk.clkr, 2793 [GP2_SRC] = &gp2_src.clkr, 2794 [GP2_CLK] = &gp2_clk.clkr, 2795 [PMEM_A_CLK] = &pmem_clk.clkr, 2796 [PRNG_SRC] = &prng_src.clkr, 2797 [PRNG_CLK] = &prng_clk.clkr, 2798 [SDC1_SRC] = &sdc1_src.clkr, 2799 [SDC1_CLK] = &sdc1_clk.clkr, 2800 [SDC3_SRC] = &sdc3_src.clkr, 2801 [SDC3_CLK] = &sdc3_clk.clkr, 2802 [TSIF_REF_SRC] = &tsif_ref_src.clkr, 2803 [TSIF_REF_CLK] = &tsif_ref_clk.clkr, 2804 [DMA_BAM_H_CLK] = &dma_bam_h_clk.clkr, 2805 [GSBI1_H_CLK] = &gsbi1_h_clk.clkr, 2806 [GSBI2_H_CLK] = &gsbi2_h_clk.clkr, 2807 [GSBI4_H_CLK] = &gsbi4_h_clk.clkr, 2808 [GSBI5_H_CLK] = &gsbi5_h_clk.clkr, 2809 [GSBI6_H_CLK] = &gsbi6_h_clk.clkr, 2810 [GSBI7_H_CLK] = &gsbi7_h_clk.clkr, 2811 [TSIF_H_CLK] = &tsif_h_clk.clkr, 2812 [SDC1_H_CLK] = &sdc1_h_clk.clkr, 2813 [SDC3_H_CLK] = &sdc3_h_clk.clkr, 2814 [ADM0_CLK] = &adm0_clk.clkr, 2815 [ADM0_PBUS_CLK] = &adm0_pbus_clk.clkr, 2816 [PCIE_A_CLK] = &pcie_a_clk.clkr, 2817 [PCIE_AUX_CLK] = &pcie_aux_clk.clkr, 2818 [PCIE_H_CLK] = &pcie_h_clk.clkr, 2819 [PCIE_PHY_CLK] = &pcie_phy_clk.clkr, 2820 [SFAB_SATA_S_H_CLK] = &sfab_sata_s_h_clk.clkr, 2821 [PMIC_ARB0_H_CLK] = &pmic_arb0_h_clk.clkr, 2822 [PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr, 2823 [PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr, 2824 [RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr, 2825 [SATA_H_CLK] = &sata_h_clk.clkr, 2826 [SATA_CLK_SRC] = &sata_ref_src.clkr, 2827 [SATA_RXOOB_CLK] = &sata_rxoob_clk.clkr, 2828 [SATA_PMALIVE_CLK] = &sata_pmalive_clk.clkr, 2829 [SATA_PHY_REF_CLK] = &sata_phy_ref_clk.clkr, 2830 [SATA_A_CLK] = &sata_a_clk.clkr, 2831 [SATA_PHY_CFG_CLK] = &sata_phy_cfg_clk.clkr, 2832 [PCIE_ALT_REF_SRC] = &pcie_ref_src.clkr, 2833 [PCIE_ALT_REF_CLK] = &pcie_ref_src_clk.clkr, 2834 [PCIE_1_A_CLK] = &pcie1_a_clk.clkr, 2835 [PCIE_1_AUX_CLK] = &pcie1_aux_clk.clkr, 2836 [PCIE_1_H_CLK] = &pcie1_h_clk.clkr, 2837 [PCIE_1_PHY_CLK] = &pcie1_phy_clk.clkr, 2838 [PCIE_1_ALT_REF_SRC] = &pcie1_ref_src.clkr, 2839 [PCIE_1_ALT_REF_CLK] = &pcie1_ref_src_clk.clkr, 2840 [PCIE_2_A_CLK] = &pcie2_a_clk.clkr, 2841 [PCIE_2_AUX_CLK] = &pcie2_aux_clk.clkr, 2842 [PCIE_2_H_CLK] = &pcie2_h_clk.clkr, 2843 [PCIE_2_PHY_CLK] = &pcie2_phy_clk.clkr, 2844 [PCIE_2_ALT_REF_SRC] = &pcie2_ref_src.clkr, 2845 [PCIE_2_ALT_REF_CLK] = &pcie2_ref_src_clk.clkr, 2846 [USB30_MASTER_SRC] = &usb30_master_clk_src.clkr, 2847 [USB30_0_MASTER_CLK] = &usb30_0_branch_clk.clkr, 2848 [USB30_1_MASTER_CLK] = &usb30_1_branch_clk.clkr, 2849 [USB30_UTMI_SRC] = &usb30_utmi_clk.clkr, 2850 [USB30_0_UTMI_CLK] = &usb30_0_utmi_clk_ctl.clkr, 2851 [USB30_1_UTMI_CLK] = &usb30_1_utmi_clk_ctl.clkr, 2852 [USB_HS1_H_CLK] = &usb_hs1_h_clk.clkr, 2853 [USB_HS1_XCVR_SRC] = &usb_hs1_xcvr_clk_src.clkr, 2854 [USB_HS1_XCVR_CLK] = &usb_hs1_xcvr_clk.clkr, 2855 [USB_FS1_H_CLK] = &usb_fs1_h_clk.clkr, 2856 [USB_FS1_XCVR_SRC] = &usb_fs1_xcvr_clk_src.clkr, 2857 [USB_FS1_XCVR_CLK] = &usb_fs1_xcvr_clk.clkr, 2858 [USB_FS1_SYSTEM_CLK] = &usb_fs1_sys_clk.clkr, 2859 [EBI2_CLK] = &ebi2_clk.clkr, 2860 [EBI2_AON_CLK] = &ebi2_aon_clk.clkr, 2861 [GMAC_CORE1_CLK_SRC] = &gmac_core1_src.clkr, 2862 [GMAC_CORE1_CLK] = &gmac_core1_clk.clkr, 2863 [GMAC_CORE2_CLK_SRC] = &gmac_core2_src.clkr, 2864 [GMAC_CORE2_CLK] = &gmac_core2_clk.clkr, 2865 [GMAC_CORE3_CLK_SRC] = &gmac_core3_src.clkr, 2866 [GMAC_CORE3_CLK] = &gmac_core3_clk.clkr, 2867 [GMAC_CORE4_CLK_SRC] = &gmac_core4_src.clkr, 2868 [GMAC_CORE4_CLK] = &gmac_core4_clk.clkr, 2869 [UBI32_CORE1_CLK_SRC] = &ubi32_core1_src_clk.clkr, 2870 [UBI32_CORE2_CLK_SRC] = &ubi32_core2_src_clk.clkr, 2871 [NSSTCM_CLK_SRC] = &nss_tcm_src.clkr, 2872 [NSSTCM_CLK] = &nss_tcm_clk.clkr, 2873 [PLL9] = &hfpll0.clkr, 2874 [PLL10] = &hfpll1.clkr, 2875 [PLL12] = &hfpll_l2.clkr, 2876}; 2877 2878static const struct qcom_reset_map gcc_ipq806x_resets[] = { 2879 [QDSS_STM_RESET] = { 0x2060, 6 }, 2880 [AFAB_SMPSS_S_RESET] = { 0x20b8, 2 }, 2881 [AFAB_SMPSS_M1_RESET] = { 0x20b8, 1 }, 2882 [AFAB_SMPSS_M0_RESET] = { 0x20b8, 0 }, 2883 [AFAB_EBI1_CH0_RESET] = { 0x20c0, 7 }, 2884 [AFAB_EBI1_CH1_RESET] = { 0x20c4, 7 }, 2885 [SFAB_ADM0_M0_RESET] = { 0x21e0, 7 }, 2886 [SFAB_ADM0_M1_RESET] = { 0x21e4, 7 }, 2887 [SFAB_ADM0_M2_RESET] = { 0x21e8, 7 }, 2888 [ADM0_C2_RESET] = { 0x220c, 4 }, 2889 [ADM0_C1_RESET] = { 0x220c, 3 }, 2890 [ADM0_C0_RESET] = { 0x220c, 2 }, 2891 [ADM0_PBUS_RESET] = { 0x220c, 1 }, 2892 [ADM0_RESET] = { 0x220c, 0 }, 2893 [QDSS_CLKS_SW_RESET] = { 0x2260, 5 }, 2894 [QDSS_POR_RESET] = { 0x2260, 4 }, 2895 [QDSS_TSCTR_RESET] = { 0x2260, 3 }, 2896 [QDSS_HRESET_RESET] = { 0x2260, 2 }, 2897 [QDSS_AXI_RESET] = { 0x2260, 1 }, 2898 [QDSS_DBG_RESET] = { 0x2260, 0 }, 2899 [SFAB_PCIE_M_RESET] = { 0x22d8, 1 }, 2900 [SFAB_PCIE_S_RESET] = { 0x22d8, 0 }, 2901 [PCIE_EXT_RESET] = { 0x22dc, 6 }, 2902 [PCIE_PHY_RESET] = { 0x22dc, 5 }, 2903 [PCIE_PCI_RESET] = { 0x22dc, 4 }, 2904 [PCIE_POR_RESET] = { 0x22dc, 3 }, 2905 [PCIE_HCLK_RESET] = { 0x22dc, 2 }, 2906 [PCIE_ACLK_RESET] = { 0x22dc, 0 }, 2907 [SFAB_LPASS_RESET] = { 0x23a0, 7 }, 2908 [SFAB_AFAB_M_RESET] = { 0x23e0, 7 }, 2909 [AFAB_SFAB_M0_RESET] = { 0x2420, 7 }, 2910 [AFAB_SFAB_M1_RESET] = { 0x2424, 7 }, 2911 [SFAB_SATA_S_RESET] = { 0x2480, 7 }, 2912 [SFAB_DFAB_M_RESET] = { 0x2500, 7 }, 2913 [DFAB_SFAB_M_RESET] = { 0x2520, 7 }, 2914 [DFAB_SWAY0_RESET] = { 0x2540, 7 }, 2915 [DFAB_SWAY1_RESET] = { 0x2544, 7 }, 2916 [DFAB_ARB0_RESET] = { 0x2560, 7 }, 2917 [DFAB_ARB1_RESET] = { 0x2564, 7 }, 2918 [PPSS_PROC_RESET] = { 0x2594, 1 }, 2919 [PPSS_RESET] = { 0x2594, 0 }, 2920 [DMA_BAM_RESET] = { 0x25c0, 7 }, 2921 [SPS_TIC_H_RESET] = { 0x2600, 7 }, 2922 [SFAB_CFPB_M_RESET] = { 0x2680, 7 }, 2923 [SFAB_CFPB_S_RESET] = { 0x26c0, 7 }, 2924 [TSIF_H_RESET] = { 0x2700, 7 }, 2925 [CE1_H_RESET] = { 0x2720, 7 }, 2926 [CE1_CORE_RESET] = { 0x2724, 7 }, 2927 [CE1_SLEEP_RESET] = { 0x2728, 7 }, 2928 [CE2_H_RESET] = { 0x2740, 7 }, 2929 [CE2_CORE_RESET] = { 0x2744, 7 }, 2930 [SFAB_SFPB_M_RESET] = { 0x2780, 7 }, 2931 [SFAB_SFPB_S_RESET] = { 0x27a0, 7 }, 2932 [RPM_PROC_RESET] = { 0x27c0, 7 }, 2933 [PMIC_SSBI2_RESET] = { 0x280c, 12 }, 2934 [SDC1_RESET] = { 0x2830, 0 }, 2935 [SDC2_RESET] = { 0x2850, 0 }, 2936 [SDC3_RESET] = { 0x2870, 0 }, 2937 [SDC4_RESET] = { 0x2890, 0 }, 2938 [USB_HS1_RESET] = { 0x2910, 0 }, 2939 [USB_HSIC_RESET] = { 0x2934, 0 }, 2940 [USB_FS1_XCVR_RESET] = { 0x2974, 1 }, 2941 [USB_FS1_RESET] = { 0x2974, 0 }, 2942 [GSBI1_RESET] = { 0x29dc, 0 }, 2943 [GSBI2_RESET] = { 0x29fc, 0 }, 2944 [GSBI3_RESET] = { 0x2a1c, 0 }, 2945 [GSBI4_RESET] = { 0x2a3c, 0 }, 2946 [GSBI5_RESET] = { 0x2a5c, 0 }, 2947 [GSBI6_RESET] = { 0x2a7c, 0 }, 2948 [GSBI7_RESET] = { 0x2a9c, 0 }, 2949 [SPDM_RESET] = { 0x2b6c, 0 }, 2950 [SEC_CTRL_RESET] = { 0x2b80, 7 }, 2951 [TLMM_H_RESET] = { 0x2ba0, 7 }, 2952 [SFAB_SATA_M_RESET] = { 0x2c18, 0 }, 2953 [SATA_RESET] = { 0x2c1c, 0 }, 2954 [TSSC_RESET] = { 0x2ca0, 7 }, 2955 [PDM_RESET] = { 0x2cc0, 12 }, 2956 [MPM_H_RESET] = { 0x2da0, 7 }, 2957 [MPM_RESET] = { 0x2da4, 0 }, 2958 [SFAB_SMPSS_S_RESET] = { 0x2e00, 7 }, 2959 [PRNG_RESET] = { 0x2e80, 12 }, 2960 [SFAB_CE3_M_RESET] = { 0x36c8, 1 }, 2961 [SFAB_CE3_S_RESET] = { 0x36c8, 0 }, 2962 [CE3_SLEEP_RESET] = { 0x36d0, 7 }, 2963 [PCIE_1_M_RESET] = { 0x3a98, 1 }, 2964 [PCIE_1_S_RESET] = { 0x3a98, 0 }, 2965 [PCIE_1_EXT_RESET] = { 0x3a9c, 6 }, 2966 [PCIE_1_PHY_RESET] = { 0x3a9c, 5 }, 2967 [PCIE_1_PCI_RESET] = { 0x3a9c, 4 }, 2968 [PCIE_1_POR_RESET] = { 0x3a9c, 3 }, 2969 [PCIE_1_HCLK_RESET] = { 0x3a9c, 2 }, 2970 [PCIE_1_ACLK_RESET] = { 0x3a9c, 0 }, 2971 [PCIE_2_M_RESET] = { 0x3ad8, 1 }, 2972 [PCIE_2_S_RESET] = { 0x3ad8, 0 }, 2973 [PCIE_2_EXT_RESET] = { 0x3adc, 6 }, 2974 [PCIE_2_PHY_RESET] = { 0x3adc, 5 }, 2975 [PCIE_2_PCI_RESET] = { 0x3adc, 4 }, 2976 [PCIE_2_POR_RESET] = { 0x3adc, 3 }, 2977 [PCIE_2_HCLK_RESET] = { 0x3adc, 2 }, 2978 [PCIE_2_ACLK_RESET] = { 0x3adc, 0 }, 2979 [SFAB_USB30_S_RESET] = { 0x3b54, 1 }, 2980 [SFAB_USB30_M_RESET] = { 0x3b54, 0 }, 2981 [USB30_0_PORT2_HS_PHY_RESET] = { 0x3b50, 5 }, 2982 [USB30_0_MASTER_RESET] = { 0x3b50, 4 }, 2983 [USB30_0_SLEEP_RESET] = { 0x3b50, 3 }, 2984 [USB30_0_UTMI_PHY_RESET] = { 0x3b50, 2 }, 2985 [USB30_0_POWERON_RESET] = { 0x3b50, 1 }, 2986 [USB30_0_PHY_RESET] = { 0x3b50, 0 }, 2987 [USB30_1_MASTER_RESET] = { 0x3b58, 4 }, 2988 [USB30_1_SLEEP_RESET] = { 0x3b58, 3 }, 2989 [USB30_1_UTMI_PHY_RESET] = { 0x3b58, 2 }, 2990 [USB30_1_POWERON_RESET] = { 0x3b58, 1 }, 2991 [USB30_1_PHY_RESET] = { 0x3b58, 0 }, 2992 [NSSFB0_RESET] = { 0x3b60, 6 }, 2993 [NSSFB1_RESET] = { 0x3b60, 7 }, 2994 [UBI32_CORE1_CLKRST_CLAMP_RESET] = { 0x3d3c, 3}, 2995 [UBI32_CORE1_CLAMP_RESET] = { 0x3d3c, 2 }, 2996 [UBI32_CORE1_AHB_RESET] = { 0x3d3c, 1 }, 2997 [UBI32_CORE1_AXI_RESET] = { 0x3d3c, 0 }, 2998 [UBI32_CORE2_CLKRST_CLAMP_RESET] = { 0x3d5c, 3 }, 2999 [UBI32_CORE2_CLAMP_RESET] = { 0x3d5c, 2 }, 3000 [UBI32_CORE2_AHB_RESET] = { 0x3d5c, 1 }, 3001 [UBI32_CORE2_AXI_RESET] = { 0x3d5c, 0 }, 3002 [GMAC_CORE1_RESET] = { 0x3cbc, 0 }, 3003 [GMAC_CORE2_RESET] = { 0x3cdc, 0 }, 3004 [GMAC_CORE3_RESET] = { 0x3cfc, 0 }, 3005 [GMAC_CORE4_RESET] = { 0x3d1c, 0 }, 3006 [GMAC_AHB_RESET] = { 0x3e24, 0 }, 3007 [NSS_CH0_RST_RX_CLK_N_RESET] = { 0x3b60, 0 }, 3008 [NSS_CH0_RST_TX_CLK_N_RESET] = { 0x3b60, 1 }, 3009 [NSS_CH0_RST_RX_125M_N_RESET] = { 0x3b60, 2 }, 3010 [NSS_CH0_HW_RST_RX_125M_N_RESET] = { 0x3b60, 3 }, 3011 [NSS_CH0_RST_TX_125M_N_RESET] = { 0x3b60, 4 }, 3012 [NSS_CH1_RST_RX_CLK_N_RESET] = { 0x3b60, 5 }, 3013 [NSS_CH1_RST_TX_CLK_N_RESET] = { 0x3b60, 6 }, 3014 [NSS_CH1_RST_RX_125M_N_RESET] = { 0x3b60, 7 }, 3015 [NSS_CH1_HW_RST_RX_125M_N_RESET] = { 0x3b60, 8 }, 3016 [NSS_CH1_RST_TX_125M_N_RESET] = { 0x3b60, 9 }, 3017 [NSS_CH2_RST_RX_CLK_N_RESET] = { 0x3b60, 10 }, 3018 [NSS_CH2_RST_TX_CLK_N_RESET] = { 0x3b60, 11 }, 3019 [NSS_CH2_RST_RX_125M_N_RESET] = { 0x3b60, 12 }, 3020 [NSS_CH2_HW_RST_RX_125M_N_RESET] = { 0x3b60, 13 }, 3021 [NSS_CH2_RST_TX_125M_N_RESET] = { 0x3b60, 14 }, 3022 [NSS_CH3_RST_RX_CLK_N_RESET] = { 0x3b60, 15 }, 3023 [NSS_CH3_RST_TX_CLK_N_RESET] = { 0x3b60, 16 }, 3024 [NSS_CH3_RST_RX_125M_N_RESET] = { 0x3b60, 17 }, 3025 [NSS_CH3_HW_RST_RX_125M_N_RESET] = { 0x3b60, 18 }, 3026 [NSS_CH3_RST_TX_125M_N_RESET] = { 0x3b60, 19 }, 3027 [NSS_RST_RX_250M_125M_N_RESET] = { 0x3b60, 20 }, 3028 [NSS_RST_TX_250M_125M_N_RESET] = { 0x3b60, 21 }, 3029 [NSS_QSGMII_TXPI_RST_N_RESET] = { 0x3b60, 22 }, 3030 [NSS_QSGMII_CDR_RST_N_RESET] = { 0x3b60, 23 }, 3031 [NSS_SGMII2_CDR_RST_N_RESET] = { 0x3b60, 24 }, 3032 [NSS_SGMII3_CDR_RST_N_RESET] = { 0x3b60, 25 }, 3033 [NSS_CAL_PRBS_RST_N_RESET] = { 0x3b60, 26 }, 3034 [NSS_LCKDT_RST_N_RESET] = { 0x3b60, 27 }, 3035 [NSS_SRDS_N_RESET] = { 0x3b60, 28 }, 3036}; 3037 3038static const struct regmap_config gcc_ipq806x_regmap_config = { 3039 .reg_bits = 32, 3040 .reg_stride = 4, 3041 .val_bits = 32, 3042 .max_register = 0x3e40, 3043 .fast_io = true, 3044}; 3045 3046static const struct qcom_cc_desc gcc_ipq806x_desc = { 3047 .config = &gcc_ipq806x_regmap_config, 3048 .clks = gcc_ipq806x_clks, 3049 .num_clks = ARRAY_SIZE(gcc_ipq806x_clks), 3050 .resets = gcc_ipq806x_resets, 3051 .num_resets = ARRAY_SIZE(gcc_ipq806x_resets), 3052}; 3053 3054static const struct of_device_id gcc_ipq806x_match_table[] = { 3055 { .compatible = "qcom,gcc-ipq8064" }, 3056 { } 3057}; 3058MODULE_DEVICE_TABLE(of, gcc_ipq806x_match_table); 3059 3060static int gcc_ipq806x_probe(struct platform_device *pdev) 3061{ 3062 struct device *dev = &pdev->dev; 3063 struct regmap *regmap; 3064 int ret; 3065 3066 ret = qcom_cc_register_board_clk(dev, "cxo_board", "cxo", 25000000); 3067 if (ret) 3068 return ret; 3069 3070 ret = qcom_cc_register_board_clk(dev, "pxo_board", "pxo", 25000000); 3071 if (ret) 3072 return ret; 3073 3074 ret = qcom_cc_probe(pdev, &gcc_ipq806x_desc); 3075 if (ret) 3076 return ret; 3077 3078 regmap = dev_get_regmap(dev, NULL); 3079 if (!regmap) 3080 return -ENODEV; 3081 3082 /* Setup PLL18 static bits */ 3083 regmap_update_bits(regmap, 0x31a4, 0xffffffc0, 0x40000400); 3084 regmap_write(regmap, 0x31b0, 0x3080); 3085 3086 /* Set GMAC footswitch sleep/wakeup values */ 3087 regmap_write(regmap, 0x3cb8, 8); 3088 regmap_write(regmap, 0x3cd8, 8); 3089 regmap_write(regmap, 0x3cf8, 8); 3090 regmap_write(regmap, 0x3d18, 8); 3091 3092 return of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev); 3093} 3094 3095static struct platform_driver gcc_ipq806x_driver = { 3096 .probe = gcc_ipq806x_probe, 3097 .driver = { 3098 .name = "gcc-ipq806x", 3099 .of_match_table = gcc_ipq806x_match_table, 3100 }, 3101}; 3102 3103static int __init gcc_ipq806x_init(void) 3104{ 3105 return platform_driver_register(&gcc_ipq806x_driver); 3106} 3107core_initcall(gcc_ipq806x_init); 3108 3109static void __exit gcc_ipq806x_exit(void) 3110{ 3111 platform_driver_unregister(&gcc_ipq806x_driver); 3112} 3113module_exit(gcc_ipq806x_exit); 3114 3115MODULE_DESCRIPTION("QCOM GCC IPQ806x Driver"); 3116MODULE_LICENSE("GPL v2"); 3117MODULE_ALIAS("platform:gcc-ipq806x"); 3118