1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
4 */
5
6#include <linux/export.h>
7#include <linux/module.h>
8#include <linux/regmap.h>
9#include <linux/platform_device.h>
10#include <linux/clk-provider.h>
11#include <linux/reset-controller.h>
12#include <linux/of.h>
13
14#include "common.h"
15#include "clk-rcg.h"
16#include "clk-regmap.h"
17#include "reset.h"
18#include "gdsc.h"
19
20struct qcom_cc {
21	struct qcom_reset_controller reset;
22	struct clk_regmap **rclks;
23	size_t num_rclks;
24};
25
26const
27struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, unsigned long rate)
28{
29	if (!f)
30		return NULL;
31
32	if (!f->freq)
33		return f;
34
35	for (; f->freq; f++)
36		if (rate <= f->freq)
37			return f;
38
39	/* Default to our fastest rate */
40	return f - 1;
41}
42EXPORT_SYMBOL_GPL(qcom_find_freq);
43
44const struct freq_tbl *qcom_find_freq_floor(const struct freq_tbl *f,
45					    unsigned long rate)
46{
47	const struct freq_tbl *best = NULL;
48
49	for ( ; f->freq; f++) {
50		if (rate >= f->freq)
51			best = f;
52		else
53			break;
54	}
55
56	return best;
57}
58EXPORT_SYMBOL_GPL(qcom_find_freq_floor);
59
60int qcom_find_src_index(struct clk_hw *hw, const struct parent_map *map, u8 src)
61{
62	int i, num_parents = clk_hw_get_num_parents(hw);
63
64	for (i = 0; i < num_parents; i++)
65		if (src == map[i].src)
66			return i;
67
68	return -ENOENT;
69}
70EXPORT_SYMBOL_GPL(qcom_find_src_index);
71
72int qcom_find_cfg_index(struct clk_hw *hw, const struct parent_map *map, u8 cfg)
73{
74	int i, num_parents = clk_hw_get_num_parents(hw);
75
76	for (i = 0; i < num_parents; i++)
77		if (cfg == map[i].cfg)
78			return i;
79
80	return -ENOENT;
81}
82EXPORT_SYMBOL_GPL(qcom_find_cfg_index);
83
84struct regmap *
85qcom_cc_map(struct platform_device *pdev, const struct qcom_cc_desc *desc)
86{
87	void __iomem *base;
88	struct resource *res;
89	struct device *dev = &pdev->dev;
90
91	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
92	base = devm_ioremap_resource(dev, res);
93	if (IS_ERR(base))
94		return ERR_CAST(base);
95
96	return devm_regmap_init_mmio(dev, base, desc->config);
97}
98EXPORT_SYMBOL_GPL(qcom_cc_map);
99
100void
101qcom_pll_set_fsm_mode(struct regmap *map, u32 reg, u8 bias_count, u8 lock_count)
102{
103	u32 val;
104	u32 mask;
105
106	/* De-assert reset to FSM */
107	regmap_update_bits(map, reg, PLL_VOTE_FSM_RESET, 0);
108
109	/* Program bias count and lock count */
110	val = bias_count << PLL_BIAS_COUNT_SHIFT |
111		lock_count << PLL_LOCK_COUNT_SHIFT;
112	mask = PLL_BIAS_COUNT_MASK << PLL_BIAS_COUNT_SHIFT;
113	mask |= PLL_LOCK_COUNT_MASK << PLL_LOCK_COUNT_SHIFT;
114	regmap_update_bits(map, reg, mask, val);
115
116	/* Enable PLL FSM voting */
117	regmap_update_bits(map, reg, PLL_VOTE_FSM_ENA, PLL_VOTE_FSM_ENA);
118}
119EXPORT_SYMBOL_GPL(qcom_pll_set_fsm_mode);
120
121static void qcom_cc_gdsc_unregister(void *data)
122{
123	gdsc_unregister(data);
124}
125
126/*
127 * Backwards compatibility with old DTs. Register a pass-through factor 1/1
128 * clock to translate 'path' clk into 'name' clk and register the 'path'
129 * clk as a fixed rate clock if it isn't present.
130 */
131static int _qcom_cc_register_board_clk(struct device *dev, const char *path,
132				       const char *name, unsigned long rate,
133				       bool add_factor)
134{
135	struct device_node *node = NULL;
136	struct device_node *clocks_node;
137	struct clk_fixed_factor *factor;
138	struct clk_fixed_rate *fixed;
139	struct clk_init_data init_data = { };
140	int ret;
141
142	clocks_node = of_find_node_by_path("/clocks");
143	if (clocks_node) {
144		node = of_get_child_by_name(clocks_node, path);
145		of_node_put(clocks_node);
146	}
147
148	if (!node) {
149		fixed = devm_kzalloc(dev, sizeof(*fixed), GFP_KERNEL);
150		if (!fixed)
151			return -EINVAL;
152
153		fixed->fixed_rate = rate;
154		fixed->hw.init = &init_data;
155
156		init_data.name = path;
157		init_data.ops = &clk_fixed_rate_ops;
158
159		ret = devm_clk_hw_register(dev, &fixed->hw);
160		if (ret)
161			return ret;
162	}
163	of_node_put(node);
164
165	if (add_factor) {
166		factor = devm_kzalloc(dev, sizeof(*factor), GFP_KERNEL);
167		if (!factor)
168			return -EINVAL;
169
170		factor->mult = factor->div = 1;
171		factor->hw.init = &init_data;
172
173		init_data.name = name;
174		init_data.parent_names = &path;
175		init_data.num_parents = 1;
176		init_data.flags = 0;
177		init_data.ops = &clk_fixed_factor_ops;
178
179		ret = devm_clk_hw_register(dev, &factor->hw);
180		if (ret)
181			return ret;
182	}
183
184	return 0;
185}
186
187int qcom_cc_register_board_clk(struct device *dev, const char *path,
188			       const char *name, unsigned long rate)
189{
190	bool add_factor = true;
191
192	/*
193	 * TODO: The RPM clock driver currently does not support the xo clock.
194	 * When xo is added to the RPM clock driver, we should change this
195	 * function to skip registration of xo factor clocks.
196	 */
197
198	return _qcom_cc_register_board_clk(dev, path, name, rate, add_factor);
199}
200EXPORT_SYMBOL_GPL(qcom_cc_register_board_clk);
201
202int qcom_cc_register_sleep_clk(struct device *dev)
203{
204	return _qcom_cc_register_board_clk(dev, "sleep_clk", "sleep_clk_src",
205					   32768, true);
206}
207EXPORT_SYMBOL_GPL(qcom_cc_register_sleep_clk);
208
209/* Drop 'protected-clocks' from the list of clocks to register */
210static void qcom_cc_drop_protected(struct device *dev, struct qcom_cc *cc)
211{
212	struct device_node *np = dev->of_node;
213	struct property *prop;
214	const __be32 *p;
215	u32 i;
216
217	of_property_for_each_u32(np, "protected-clocks", prop, p, i) {
218		if (i >= cc->num_rclks)
219			continue;
220
221		cc->rclks[i] = NULL;
222	}
223}
224
225static struct clk_hw *qcom_cc_clk_hw_get(struct of_phandle_args *clkspec,
226					 void *data)
227{
228	struct qcom_cc *cc = data;
229	unsigned int idx = clkspec->args[0];
230
231	if (idx >= cc->num_rclks) {
232		pr_err("%s: invalid index %u\n", __func__, idx);
233		return ERR_PTR(-EINVAL);
234	}
235
236	return cc->rclks[idx] ? &cc->rclks[idx]->hw : NULL;
237}
238
239int qcom_cc_really_probe(struct platform_device *pdev,
240			 const struct qcom_cc_desc *desc, struct regmap *regmap)
241{
242	int i, ret;
243	struct device *dev = &pdev->dev;
244	struct qcom_reset_controller *reset;
245	struct qcom_cc *cc;
246	struct gdsc_desc *scd;
247	size_t num_clks = desc->num_clks;
248	struct clk_regmap **rclks = desc->clks;
249	size_t num_clk_hws = desc->num_clk_hws;
250	struct clk_hw **clk_hws = desc->clk_hws;
251
252	cc = devm_kzalloc(dev, sizeof(*cc), GFP_KERNEL);
253	if (!cc)
254		return -ENOMEM;
255
256	reset = &cc->reset;
257	reset->rcdev.of_node = dev->of_node;
258	reset->rcdev.ops = &qcom_reset_ops;
259	reset->rcdev.owner = dev->driver->owner;
260	reset->rcdev.nr_resets = desc->num_resets;
261	reset->regmap = regmap;
262	reset->reset_map = desc->resets;
263
264	ret = devm_reset_controller_register(dev, &reset->rcdev);
265	if (ret)
266		return ret;
267
268	if (desc->gdscs && desc->num_gdscs) {
269		scd = devm_kzalloc(dev, sizeof(*scd), GFP_KERNEL);
270		if (!scd)
271			return -ENOMEM;
272		scd->dev = dev;
273		scd->scs = desc->gdscs;
274		scd->num = desc->num_gdscs;
275		ret = gdsc_register(scd, &reset->rcdev, regmap);
276		if (ret)
277			return ret;
278		ret = devm_add_action_or_reset(dev, qcom_cc_gdsc_unregister,
279					       scd);
280		if (ret)
281			return ret;
282	}
283
284	cc->rclks = rclks;
285	cc->num_rclks = num_clks;
286
287	qcom_cc_drop_protected(dev, cc);
288
289	for (i = 0; i < num_clk_hws; i++) {
290		ret = devm_clk_hw_register(dev, clk_hws[i]);
291		if (ret)
292			return ret;
293	}
294
295	for (i = 0; i < num_clks; i++) {
296		if (!rclks[i])
297			continue;
298
299		ret = devm_clk_register_regmap(dev, rclks[i]);
300		if (ret)
301			return ret;
302	}
303
304	ret = devm_of_clk_add_hw_provider(dev, qcom_cc_clk_hw_get, cc);
305	if (ret)
306		return ret;
307
308	return 0;
309}
310EXPORT_SYMBOL_GPL(qcom_cc_really_probe);
311
312int qcom_cc_probe(struct platform_device *pdev, const struct qcom_cc_desc *desc)
313{
314	struct regmap *regmap;
315
316	regmap = qcom_cc_map(pdev, desc);
317	if (IS_ERR(regmap))
318		return PTR_ERR(regmap);
319
320	return qcom_cc_really_probe(pdev, desc, regmap);
321}
322EXPORT_SYMBOL_GPL(qcom_cc_probe);
323
324int qcom_cc_probe_by_index(struct platform_device *pdev, int index,
325			   const struct qcom_cc_desc *desc)
326{
327	struct regmap *regmap;
328	struct resource *res;
329	void __iomem *base;
330
331	res = platform_get_resource(pdev, IORESOURCE_MEM, index);
332	base = devm_ioremap_resource(&pdev->dev, res);
333	if (IS_ERR(base))
334		return -ENOMEM;
335
336	regmap = devm_regmap_init_mmio(&pdev->dev, base, desc->config);
337	if (IS_ERR(regmap))
338		return PTR_ERR(regmap);
339
340	return qcom_cc_really_probe(pdev, desc, regmap);
341}
342EXPORT_SYMBOL_GPL(qcom_cc_probe_by_index);
343
344MODULE_LICENSE("GPL v2");
345