18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0 */ 28c2ecf20Sopenharmony_ci/* 38c2ecf20Sopenharmony_ci * Copyright (c) 2017, Linaro Limited 48c2ecf20Sopenharmony_ci * Author: Georgi Djakov <georgi.djakov@linaro.org> 58c2ecf20Sopenharmony_ci */ 68c2ecf20Sopenharmony_ci 78c2ecf20Sopenharmony_ci#ifndef __QCOM_CLK_REGMAP_MUX_DIV_H__ 88c2ecf20Sopenharmony_ci#define __QCOM_CLK_REGMAP_MUX_DIV_H__ 98c2ecf20Sopenharmony_ci 108c2ecf20Sopenharmony_ci#include <linux/clk-provider.h> 118c2ecf20Sopenharmony_ci#include "clk-regmap.h" 128c2ecf20Sopenharmony_ci 138c2ecf20Sopenharmony_ci/** 148c2ecf20Sopenharmony_ci * struct mux_div_clk - combined mux/divider clock 158c2ecf20Sopenharmony_ci * @reg_offset: offset of the mux/divider register 168c2ecf20Sopenharmony_ci * @hid_width: number of bits in half integer divider 178c2ecf20Sopenharmony_ci * @hid_shift: lowest bit of hid value field 188c2ecf20Sopenharmony_ci * @src_width: number of bits in source select 198c2ecf20Sopenharmony_ci * @src_shift: lowest bit of source select field 208c2ecf20Sopenharmony_ci * @div: the divider raw configuration value 218c2ecf20Sopenharmony_ci * @src: the mux index which will be used if the clock is enabled 228c2ecf20Sopenharmony_ci * @parent_map: map from parent_names index to src_sel field 238c2ecf20Sopenharmony_ci * @clkr: handle between common and hardware-specific interfaces 248c2ecf20Sopenharmony_ci * @pclk: the input PLL clock 258c2ecf20Sopenharmony_ci * @clk_nb: clock notifier for rate changes of the input PLL 268c2ecf20Sopenharmony_ci */ 278c2ecf20Sopenharmony_cistruct clk_regmap_mux_div { 288c2ecf20Sopenharmony_ci u32 reg_offset; 298c2ecf20Sopenharmony_ci u32 hid_width; 308c2ecf20Sopenharmony_ci u32 hid_shift; 318c2ecf20Sopenharmony_ci u32 src_width; 328c2ecf20Sopenharmony_ci u32 src_shift; 338c2ecf20Sopenharmony_ci u32 div; 348c2ecf20Sopenharmony_ci u32 src; 358c2ecf20Sopenharmony_ci const u32 *parent_map; 368c2ecf20Sopenharmony_ci struct clk_regmap clkr; 378c2ecf20Sopenharmony_ci struct clk *pclk; 388c2ecf20Sopenharmony_ci struct notifier_block clk_nb; 398c2ecf20Sopenharmony_ci}; 408c2ecf20Sopenharmony_ci 418c2ecf20Sopenharmony_ciextern const struct clk_ops clk_regmap_mux_div_ops; 428c2ecf20Sopenharmony_ciextern int mux_div_set_src_div(struct clk_regmap_mux_div *md, u32 src, u32 div); 438c2ecf20Sopenharmony_ci 448c2ecf20Sopenharmony_ci#endif 45