1// SPDX-License-Identifier: GPL-2.0
2// Copyright (c) 2018, The Linux Foundation. All rights reserved.
3
4#include <linux/kernel.h>
5#include <linux/module.h>
6#include <linux/init.h>
7#include <linux/io.h>
8#include <linux/delay.h>
9#include <linux/err.h>
10#include <linux/clk-provider.h>
11#include <linux/spinlock.h>
12
13#include <asm/krait-l2-accessors.h>
14
15#include "clk-krait.h"
16
17/* Secondary and primary muxes share the same cp15 register */
18static DEFINE_SPINLOCK(krait_clock_reg_lock);
19
20#define LPL_SHIFT	8
21static void __krait_mux_set_sel(struct krait_mux_clk *mux, int sel)
22{
23	unsigned long flags;
24	u32 regval;
25
26	spin_lock_irqsave(&krait_clock_reg_lock, flags);
27	regval = krait_get_l2_indirect_reg(mux->offset);
28	regval &= ~(mux->mask << mux->shift);
29	regval |= (sel & mux->mask) << mux->shift;
30	if (mux->lpl) {
31		regval &= ~(mux->mask << (mux->shift + LPL_SHIFT));
32		regval |= (sel & mux->mask) << (mux->shift + LPL_SHIFT);
33	}
34	krait_set_l2_indirect_reg(mux->offset, regval);
35
36	/* Wait for switch to complete. */
37	mb();
38	udelay(1);
39
40	/*
41	 * Unlock now to make sure the mux register is not
42	 * modified while switching to the new parent.
43	 */
44	spin_unlock_irqrestore(&krait_clock_reg_lock, flags);
45}
46
47static int krait_mux_set_parent(struct clk_hw *hw, u8 index)
48{
49	struct krait_mux_clk *mux = to_krait_mux_clk(hw);
50	u32 sel;
51
52	sel = clk_mux_index_to_val(mux->parent_map, 0, index);
53	mux->en_mask = sel;
54	/* Don't touch mux if CPU is off as it won't work */
55	if (__clk_is_enabled(hw->clk))
56		__krait_mux_set_sel(mux, sel);
57
58	mux->reparent = true;
59
60	return 0;
61}
62
63static u8 krait_mux_get_parent(struct clk_hw *hw)
64{
65	struct krait_mux_clk *mux = to_krait_mux_clk(hw);
66	u32 sel;
67
68	sel = krait_get_l2_indirect_reg(mux->offset);
69	sel >>= mux->shift;
70	sel &= mux->mask;
71	mux->en_mask = sel;
72
73	return clk_mux_val_to_index(hw, mux->parent_map, 0, sel);
74}
75
76const struct clk_ops krait_mux_clk_ops = {
77	.set_parent = krait_mux_set_parent,
78	.get_parent = krait_mux_get_parent,
79	.determine_rate = __clk_mux_determine_rate_closest,
80};
81EXPORT_SYMBOL_GPL(krait_mux_clk_ops);
82
83/* The divider can divide by 2, 4, 6 and 8. But we only really need div-2. */
84static long krait_div2_round_rate(struct clk_hw *hw, unsigned long rate,
85				  unsigned long *parent_rate)
86{
87	*parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), rate * 2);
88	return DIV_ROUND_UP(*parent_rate, 2);
89}
90
91static int krait_div2_set_rate(struct clk_hw *hw, unsigned long rate,
92			       unsigned long parent_rate)
93{
94	struct krait_div2_clk *d = to_krait_div2_clk(hw);
95	unsigned long flags;
96	u32 val;
97	u32 mask = BIT(d->width) - 1;
98
99	if (d->lpl)
100		mask = mask << (d->shift + LPL_SHIFT) | mask << d->shift;
101	else
102		mask <<= d->shift;
103
104	spin_lock_irqsave(&krait_clock_reg_lock, flags);
105	val = krait_get_l2_indirect_reg(d->offset);
106	val &= ~mask;
107	krait_set_l2_indirect_reg(d->offset, val);
108	spin_unlock_irqrestore(&krait_clock_reg_lock, flags);
109
110	return 0;
111}
112
113static unsigned long
114krait_div2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
115{
116	struct krait_div2_clk *d = to_krait_div2_clk(hw);
117	u32 mask = BIT(d->width) - 1;
118	u32 div;
119
120	div = krait_get_l2_indirect_reg(d->offset);
121	div >>= d->shift;
122	div &= mask;
123	div = (div + 1) * 2;
124
125	return DIV_ROUND_UP(parent_rate, div);
126}
127
128const struct clk_ops krait_div2_clk_ops = {
129	.round_rate = krait_div2_round_rate,
130	.set_rate = krait_div2_set_rate,
131	.recalc_rate = krait_div2_recalc_rate,
132};
133EXPORT_SYMBOL_GPL(krait_div2_clk_ops);
134