1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Marvell PXA3xxx family clocks 4 * 5 * Copyright (C) 2014 Robert Jarzmik 6 * 7 * Heavily inspired from former arch/arm/mach-pxa/pxa3xx.c 8 * 9 * For non-devicetree platforms. Once pxa is fully converted to devicetree, this 10 * should go away. 11 */ 12#include <linux/io.h> 13#include <linux/clk.h> 14#include <linux/clk-provider.h> 15#include <linux/clkdev.h> 16#include <linux/of.h> 17#include <mach/smemc.h> 18#include <mach/pxa3xx-regs.h> 19 20#include <dt-bindings/clock/pxa-clock.h> 21#include "clk-pxa.h" 22 23#define KHz 1000 24#define MHz (1000 * 1000) 25 26enum { 27 PXA_CORE_60Mhz = 0, 28 PXA_CORE_RUN, 29 PXA_CORE_TURBO, 30}; 31 32enum { 33 PXA_BUS_60Mhz = 0, 34 PXA_BUS_HSS, 35}; 36 37/* crystal frequency to HSIO bus frequency multiplier (HSS) */ 38static unsigned char hss_mult[4] = { 8, 12, 16, 24 }; 39 40/* crystal frequency to static memory controller multiplier (SMCFS) */ 41static unsigned int smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, }; 42static unsigned int df_clkdiv[4] = { 1, 2, 4, 1 }; 43 44static const char * const get_freq_khz[] = { 45 "core", "ring_osc_60mhz", "run", "cpll", "system_bus" 46}; 47 48/* 49 * Get the clock frequency as reflected by ACSR and the turbo flag. 50 * We assume these values have been applied via a fcs. 51 * If info is not 0 we also display the current settings. 52 */ 53unsigned int pxa3xx_get_clk_frequency_khz(int info) 54{ 55 struct clk *clk; 56 unsigned long clks[5]; 57 int i; 58 59 for (i = 0; i < 5; i++) { 60 clk = clk_get(NULL, get_freq_khz[i]); 61 if (IS_ERR(clk)) { 62 clks[i] = 0; 63 } else { 64 clks[i] = clk_get_rate(clk); 65 clk_put(clk); 66 } 67 } 68 if (info) { 69 pr_info("RO Mode clock: %ld.%02ldMHz\n", 70 clks[1] / 1000000, (clks[0] % 1000000) / 10000); 71 pr_info("Run Mode clock: %ld.%02ldMHz\n", 72 clks[2] / 1000000, (clks[1] % 1000000) / 10000); 73 pr_info("Turbo Mode clock: %ld.%02ldMHz\n", 74 clks[3] / 1000000, (clks[2] % 1000000) / 10000); 75 pr_info("System bus clock: %ld.%02ldMHz\n", 76 clks[4] / 1000000, (clks[4] % 1000000) / 10000); 77 } 78 return (unsigned int)clks[0] / KHz; 79} 80 81static unsigned long clk_pxa3xx_ac97_get_rate(struct clk_hw *hw, 82 unsigned long parent_rate) 83{ 84 unsigned long ac97_div, rate; 85 86 ac97_div = AC97_DIV; 87 88 /* This may loose precision for some rates but won't for the 89 * standard 24.576MHz. 90 */ 91 rate = parent_rate / 2; 92 rate /= ((ac97_div >> 12) & 0x7fff); 93 rate *= (ac97_div & 0xfff); 94 95 return rate; 96} 97PARENTS(clk_pxa3xx_ac97) = { "spll_624mhz" }; 98RATE_RO_OPS(clk_pxa3xx_ac97, "ac97"); 99 100static unsigned long clk_pxa3xx_smemc_get_rate(struct clk_hw *hw, 101 unsigned long parent_rate) 102{ 103 unsigned long acsr = ACSR; 104 unsigned long memclkcfg = __raw_readl(MEMCLKCFG); 105 106 return (parent_rate / 48) * smcfs_mult[(acsr >> 23) & 0x7] / 107 df_clkdiv[(memclkcfg >> 16) & 0x3]; 108} 109PARENTS(clk_pxa3xx_smemc) = { "spll_624mhz" }; 110RATE_RO_OPS(clk_pxa3xx_smemc, "smemc"); 111 112static bool pxa3xx_is_ring_osc_forced(void) 113{ 114 unsigned long acsr = ACSR; 115 116 return acsr & ACCR_D0CS; 117} 118 119PARENTS(pxa3xx_pbus) = { "ring_osc_60mhz", "spll_624mhz" }; 120PARENTS(pxa3xx_32Khz_bus) = { "osc_32_768khz", "osc_32_768khz" }; 121PARENTS(pxa3xx_13MHz_bus) = { "osc_13mhz", "osc_13mhz" }; 122PARENTS(pxa3xx_ac97_bus) = { "ring_osc_60mhz", "ac97" }; 123PARENTS(pxa3xx_sbus) = { "ring_osc_60mhz", "system_bus" }; 124PARENTS(pxa3xx_smemcbus) = { "ring_osc_60mhz", "smemc" }; 125 126#define CKEN_AB(bit) ((CKEN_ ## bit > 31) ? &CKENB : &CKENA) 127#define PXA3XX_CKEN(dev_id, con_id, parents, mult_lp, div_lp, mult_hp, \ 128 div_hp, bit, is_lp, flags) \ 129 PXA_CKEN(dev_id, con_id, bit, parents, mult_lp, div_lp, \ 130 mult_hp, div_hp, is_lp, CKEN_AB(bit), \ 131 (CKEN_ ## bit % 32), flags) 132#define PXA3XX_PBUS_CKEN(dev_id, con_id, bit, mult_lp, div_lp, \ 133 mult_hp, div_hp, delay) \ 134 PXA3XX_CKEN(dev_id, con_id, pxa3xx_pbus_parents, mult_lp, \ 135 div_lp, mult_hp, div_hp, bit, pxa3xx_is_ring_osc_forced, 0) 136#define PXA3XX_CKEN_1RATE(dev_id, con_id, bit, parents) \ 137 PXA_CKEN_1RATE(dev_id, con_id, bit, parents, \ 138 CKEN_AB(bit), (CKEN_ ## bit % 32), 0) 139 140static struct desc_clk_cken pxa3xx_clocks[] __initdata = { 141 PXA3XX_PBUS_CKEN("pxa2xx-uart.0", NULL, FFUART, 1, 4, 1, 42, 1), 142 PXA3XX_PBUS_CKEN("pxa2xx-uart.1", NULL, BTUART, 1, 4, 1, 42, 1), 143 PXA3XX_PBUS_CKEN("pxa2xx-uart.2", NULL, STUART, 1, 4, 1, 42, 1), 144 PXA3XX_PBUS_CKEN("pxa2xx-i2c.0", NULL, I2C, 2, 5, 1, 19, 0), 145 PXA3XX_PBUS_CKEN("pxa27x-udc", NULL, UDC, 1, 4, 1, 13, 5), 146 PXA3XX_PBUS_CKEN("pxa27x-ohci", NULL, USBH, 1, 4, 1, 13, 0), 147 PXA3XX_PBUS_CKEN("pxa3xx-u2d", NULL, USB2, 1, 4, 1, 13, 0), 148 PXA3XX_PBUS_CKEN("pxa27x-pwm.0", NULL, PWM0, 1, 6, 1, 48, 0), 149 PXA3XX_PBUS_CKEN("pxa27x-pwm.1", NULL, PWM1, 1, 6, 1, 48, 0), 150 PXA3XX_PBUS_CKEN("pxa2xx-mci.0", NULL, MMC1, 1, 4, 1, 24, 0), 151 PXA3XX_PBUS_CKEN("pxa2xx-mci.1", NULL, MMC2, 1, 4, 1, 24, 0), 152 PXA3XX_PBUS_CKEN("pxa2xx-mci.2", NULL, MMC3, 1, 4, 1, 24, 0), 153 154 PXA3XX_CKEN_1RATE("pxa27x-keypad", NULL, KEYPAD, 155 pxa3xx_32Khz_bus_parents), 156 PXA3XX_CKEN_1RATE("pxa3xx-ssp.0", NULL, SSP1, pxa3xx_13MHz_bus_parents), 157 PXA3XX_CKEN_1RATE("pxa3xx-ssp.1", NULL, SSP2, pxa3xx_13MHz_bus_parents), 158 PXA3XX_CKEN_1RATE("pxa3xx-ssp.2", NULL, SSP3, pxa3xx_13MHz_bus_parents), 159 PXA3XX_CKEN_1RATE("pxa3xx-ssp.3", NULL, SSP4, pxa3xx_13MHz_bus_parents), 160 161 PXA3XX_CKEN(NULL, "AC97CLK", pxa3xx_ac97_bus_parents, 1, 4, 1, 1, AC97, 162 pxa3xx_is_ring_osc_forced, 0), 163 PXA3XX_CKEN(NULL, "CAMCLK", pxa3xx_sbus_parents, 1, 2, 1, 1, CAMERA, 164 pxa3xx_is_ring_osc_forced, 0), 165 PXA3XX_CKEN("pxa2xx-fb", NULL, pxa3xx_sbus_parents, 1, 1, 1, 1, LCD, 166 pxa3xx_is_ring_osc_forced, 0), 167 PXA3XX_CKEN("pxa2xx-pcmcia", NULL, pxa3xx_smemcbus_parents, 1, 4, 168 1, 1, SMC, pxa3xx_is_ring_osc_forced, CLK_IGNORE_UNUSED), 169}; 170 171static struct desc_clk_cken pxa300_310_clocks[] __initdata = { 172 173 PXA3XX_PBUS_CKEN("pxa3xx-gcu", NULL, PXA300_GCU, 1, 1, 1, 1, 0), 174 PXA3XX_PBUS_CKEN("pxa3xx-nand", NULL, NAND, 1, 2, 1, 4, 0), 175 PXA3XX_CKEN_1RATE("pxa3xx-gpio", NULL, GPIO, pxa3xx_13MHz_bus_parents), 176}; 177 178static struct desc_clk_cken pxa320_clocks[] __initdata = { 179 PXA3XX_PBUS_CKEN("pxa3xx-nand", NULL, NAND, 1, 2, 1, 6, 0), 180 PXA3XX_PBUS_CKEN("pxa3xx-gcu", NULL, PXA320_GCU, 1, 1, 1, 1, 0), 181 PXA3XX_CKEN_1RATE("pxa3xx-gpio", NULL, GPIO, pxa3xx_13MHz_bus_parents), 182}; 183 184static struct desc_clk_cken pxa93x_clocks[] __initdata = { 185 186 PXA3XX_PBUS_CKEN("pxa3xx-gcu", NULL, PXA300_GCU, 1, 1, 1, 1, 0), 187 PXA3XX_PBUS_CKEN("pxa3xx-nand", NULL, NAND, 1, 2, 1, 4, 0), 188 PXA3XX_CKEN_1RATE("pxa93x-gpio", NULL, GPIO, pxa3xx_13MHz_bus_parents), 189}; 190 191static unsigned long clk_pxa3xx_system_bus_get_rate(struct clk_hw *hw, 192 unsigned long parent_rate) 193{ 194 unsigned long acsr = ACSR; 195 unsigned int hss = (acsr >> 14) & 0x3; 196 197 if (pxa3xx_is_ring_osc_forced()) 198 return parent_rate; 199 return parent_rate / 48 * hss_mult[hss]; 200} 201 202static u8 clk_pxa3xx_system_bus_get_parent(struct clk_hw *hw) 203{ 204 if (pxa3xx_is_ring_osc_forced()) 205 return PXA_BUS_60Mhz; 206 else 207 return PXA_BUS_HSS; 208} 209 210PARENTS(clk_pxa3xx_system_bus) = { "ring_osc_60mhz", "spll_624mhz" }; 211MUX_RO_RATE_RO_OPS(clk_pxa3xx_system_bus, "system_bus"); 212 213static unsigned long clk_pxa3xx_core_get_rate(struct clk_hw *hw, 214 unsigned long parent_rate) 215{ 216 return parent_rate; 217} 218 219static u8 clk_pxa3xx_core_get_parent(struct clk_hw *hw) 220{ 221 unsigned long xclkcfg; 222 unsigned int t; 223 224 if (pxa3xx_is_ring_osc_forced()) 225 return PXA_CORE_60Mhz; 226 227 /* Read XCLKCFG register turbo bit */ 228 __asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg)); 229 t = xclkcfg & 0x1; 230 231 if (t) 232 return PXA_CORE_TURBO; 233 return PXA_CORE_RUN; 234} 235PARENTS(clk_pxa3xx_core) = { "ring_osc_60mhz", "run", "cpll" }; 236MUX_RO_RATE_RO_OPS(clk_pxa3xx_core, "core"); 237 238static unsigned long clk_pxa3xx_run_get_rate(struct clk_hw *hw, 239 unsigned long parent_rate) 240{ 241 unsigned long acsr = ACSR; 242 unsigned int xn = (acsr & ACCR_XN_MASK) >> 8; 243 unsigned int t, xclkcfg; 244 245 /* Read XCLKCFG register turbo bit */ 246 __asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg)); 247 t = xclkcfg & 0x1; 248 249 return t ? (parent_rate / xn) * 2 : parent_rate; 250} 251PARENTS(clk_pxa3xx_run) = { "cpll" }; 252RATE_RO_OPS(clk_pxa3xx_run, "run"); 253 254static unsigned long clk_pxa3xx_cpll_get_rate(struct clk_hw *hw, 255 unsigned long parent_rate) 256{ 257 unsigned long acsr = ACSR; 258 unsigned int xn = (acsr & ACCR_XN_MASK) >> 8; 259 unsigned int xl = acsr & ACCR_XL_MASK; 260 unsigned int t, xclkcfg; 261 262 /* Read XCLKCFG register turbo bit */ 263 __asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg)); 264 t = xclkcfg & 0x1; 265 266 pr_info("RJK: parent_rate=%lu, xl=%u, xn=%u\n", parent_rate, xl, xn); 267 return t ? parent_rate * xl * xn : parent_rate * xl; 268} 269PARENTS(clk_pxa3xx_cpll) = { "osc_13mhz" }; 270RATE_RO_OPS(clk_pxa3xx_cpll, "cpll"); 271 272static void __init pxa3xx_register_core(void) 273{ 274 clk_register_clk_pxa3xx_cpll(); 275 clk_register_clk_pxa3xx_run(); 276 277 clkdev_pxa_register(CLK_CORE, "core", NULL, 278 clk_register_clk_pxa3xx_core()); 279} 280 281static void __init pxa3xx_register_plls(void) 282{ 283 clk_register_fixed_rate(NULL, "osc_13mhz", NULL, 284 CLK_GET_RATE_NOCACHE, 285 13 * MHz); 286 clkdev_pxa_register(CLK_OSC32k768, "osc_32_768khz", NULL, 287 clk_register_fixed_rate(NULL, "osc_32_768khz", NULL, 288 CLK_GET_RATE_NOCACHE, 289 32768)); 290 clk_register_fixed_rate(NULL, "ring_osc_120mhz", NULL, 291 CLK_GET_RATE_NOCACHE, 292 120 * MHz); 293 clk_register_fixed_rate(NULL, "clk_dummy", NULL, 0, 0); 294 clk_register_fixed_factor(NULL, "spll_624mhz", "osc_13mhz", 0, 48, 1); 295 clk_register_fixed_factor(NULL, "ring_osc_60mhz", "ring_osc_120mhz", 296 0, 1, 2); 297} 298 299#define DUMMY_CLK(_con_id, _dev_id, _parent) \ 300 { .con_id = _con_id, .dev_id = _dev_id, .parent = _parent } 301struct dummy_clk { 302 const char *con_id; 303 const char *dev_id; 304 const char *parent; 305}; 306static struct dummy_clk dummy_clks[] __initdata = { 307 DUMMY_CLK(NULL, "pxa93x-gpio", "osc_13mhz"), 308 DUMMY_CLK(NULL, "sa1100-rtc", "osc_32_768khz"), 309 DUMMY_CLK("UARTCLK", "pxa2xx-ir", "STUART"), 310 DUMMY_CLK(NULL, "pxa3xx-pwri2c.1", "osc_13mhz"), 311}; 312 313static void __init pxa3xx_dummy_clocks_init(void) 314{ 315 struct clk *clk; 316 struct dummy_clk *d; 317 const char *name; 318 int i; 319 320 for (i = 0; i < ARRAY_SIZE(dummy_clks); i++) { 321 d = &dummy_clks[i]; 322 name = d->dev_id ? d->dev_id : d->con_id; 323 clk = clk_register_fixed_factor(NULL, name, d->parent, 0, 1, 1); 324 clk_register_clkdev(clk, d->con_id, d->dev_id); 325 } 326} 327 328static void __init pxa3xx_base_clocks_init(void) 329{ 330 struct clk *clk; 331 332 pxa3xx_register_plls(); 333 pxa3xx_register_core(); 334 clk_register_clk_pxa3xx_system_bus(); 335 clk_register_clk_pxa3xx_ac97(); 336 clk_register_clk_pxa3xx_smemc(); 337 clk = clk_register_gate(NULL, "CLK_POUT", 338 "osc_13mhz", 0, OSCC, 11, 0, NULL); 339 clk_register_clkdev(clk, "CLK_POUT", NULL); 340 clkdev_pxa_register(CLK_OSTIMER, "OSTIMER0", NULL, 341 clk_register_fixed_factor(NULL, "os-timer0", 342 "osc_13mhz", 0, 1, 4)); 343} 344 345int __init pxa3xx_clocks_init(void) 346{ 347 int ret; 348 349 pxa3xx_base_clocks_init(); 350 pxa3xx_dummy_clocks_init(); 351 ret = clk_pxa_cken_init(pxa3xx_clocks, ARRAY_SIZE(pxa3xx_clocks)); 352 if (ret) 353 return ret; 354 if (cpu_is_pxa320()) 355 return clk_pxa_cken_init(pxa320_clocks, 356 ARRAY_SIZE(pxa320_clocks)); 357 if (cpu_is_pxa300() || cpu_is_pxa310()) 358 return clk_pxa_cken_init(pxa300_310_clocks, 359 ARRAY_SIZE(pxa300_310_clocks)); 360 return clk_pxa_cken_init(pxa93x_clocks, ARRAY_SIZE(pxa93x_clocks)); 361} 362 363static void __init pxa3xx_dt_clocks_init(struct device_node *np) 364{ 365 pxa3xx_clocks_init(); 366 clk_pxa_dt_common_init(np); 367} 368CLK_OF_DECLARE(pxa_clks, "marvell,pxa300-clocks", pxa3xx_dt_clocks_init); 369