1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (c) 2018 MediaTek Inc.
4 * Author: Owen Chen <owen.chen@mediatek.com>
5 */
6
7#ifndef __DRV_CLK_MTK_MUX_H
8#define __DRV_CLK_MTK_MUX_H
9
10#include <linux/clk-provider.h>
11
12struct mtk_clk_mux {
13	struct clk_hw hw;
14	struct regmap *regmap;
15	const struct mtk_mux *data;
16	spinlock_t *lock;
17};
18
19struct mtk_mux {
20	int id;
21	const char *name;
22	const char * const *parent_names;
23	unsigned int flags;
24
25	u32 mux_ofs;
26	u32 set_ofs;
27	u32 clr_ofs;
28	u32 upd_ofs;
29
30	u8 mux_shift;
31	u8 mux_width;
32	u8 gate_shift;
33	s8 upd_shift;
34
35	const struct clk_ops *ops;
36
37	signed char num_parents;
38};
39
40extern const struct clk_ops mtk_mux_ops;
41extern const struct clk_ops mtk_mux_clr_set_upd_ops;
42extern const struct clk_ops mtk_mux_gate_ops;
43extern const struct clk_ops mtk_mux_gate_clr_set_upd_ops;
44
45#define GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs,		\
46			_mux_set_ofs, _mux_clr_ofs, _shift, _width,	\
47			_gate, _upd_ofs, _upd, _flags, _ops) {		\
48		.id = _id,						\
49		.name = _name,						\
50		.mux_ofs = _mux_ofs,					\
51		.set_ofs = _mux_set_ofs,				\
52		.clr_ofs = _mux_clr_ofs,				\
53		.upd_ofs = _upd_ofs,					\
54		.mux_shift = _shift,					\
55		.mux_width = _width,					\
56		.gate_shift = _gate,					\
57		.upd_shift = _upd,					\
58		.parent_names = _parents,				\
59		.num_parents = ARRAY_SIZE(_parents),			\
60		.flags = _flags,					\
61		.ops = &_ops,						\
62	}
63
64#define MUX_GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs,	\
65			_mux_set_ofs, _mux_clr_ofs, _shift, _width,	\
66			_gate, _upd_ofs, _upd, _flags)			\
67		GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs,	\
68			_mux_set_ofs, _mux_clr_ofs, _shift, _width,	\
69			_gate, _upd_ofs, _upd, _flags,			\
70			mtk_mux_gate_clr_set_upd_ops)
71
72#define MUX_GATE_CLR_SET_UPD(_id, _name, _parents, _mux_ofs,		\
73			_mux_set_ofs, _mux_clr_ofs, _shift, _width,	\
74			_gate, _upd_ofs, _upd)				\
75		MUX_GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents,	\
76			_mux_ofs, _mux_set_ofs, _mux_clr_ofs, _shift,	\
77			_width, _gate, _upd_ofs, _upd,			\
78			CLK_SET_RATE_PARENT)
79
80struct clk *mtk_clk_register_mux(const struct mtk_mux *mux,
81				 struct regmap *regmap,
82				 spinlock_t *lock);
83
84int mtk_clk_register_muxes(const struct mtk_mux *muxes,
85			   int num, struct device_node *node,
86			   spinlock_t *lock,
87			   struct clk_onecell_data *clk_data);
88
89#endif /* __DRV_CLK_MTK_MUX_H */
90