18c2ecf20Sopenharmony_ci// SPDX-License-Identifier: GPL-2.0
28c2ecf20Sopenharmony_ci/*
38c2ecf20Sopenharmony_ci * Copyright (c) 2019 MediaTek Inc.
48c2ecf20Sopenharmony_ci * Author: James Liao <jamesjj.liao@mediatek.com>
58c2ecf20Sopenharmony_ci *         Fabien Parent <fparent@baylibre.com>
68c2ecf20Sopenharmony_ci */
78c2ecf20Sopenharmony_ci
88c2ecf20Sopenharmony_ci#include <linux/clk-provider.h>
98c2ecf20Sopenharmony_ci#include <linux/of.h>
108c2ecf20Sopenharmony_ci#include <linux/of_address.h>
118c2ecf20Sopenharmony_ci#include <linux/of_device.h>
128c2ecf20Sopenharmony_ci#include <linux/platform_device.h>
138c2ecf20Sopenharmony_ci
148c2ecf20Sopenharmony_ci#include "clk-mtk.h"
158c2ecf20Sopenharmony_ci#include "clk-gate.h"
168c2ecf20Sopenharmony_ci
178c2ecf20Sopenharmony_ci#include <dt-bindings/clock/mt8516-clk.h>
188c2ecf20Sopenharmony_ci
198c2ecf20Sopenharmony_cistatic const struct mtk_gate_regs aud_cg_regs = {
208c2ecf20Sopenharmony_ci	.set_ofs = 0x0,
218c2ecf20Sopenharmony_ci	.clr_ofs = 0x0,
228c2ecf20Sopenharmony_ci	.sta_ofs = 0x0,
238c2ecf20Sopenharmony_ci};
248c2ecf20Sopenharmony_ci
258c2ecf20Sopenharmony_ci#define GATE_AUD(_id, _name, _parent, _shift) {	\
268c2ecf20Sopenharmony_ci		.id = _id,			\
278c2ecf20Sopenharmony_ci		.name = _name,			\
288c2ecf20Sopenharmony_ci		.parent_name = _parent,		\
298c2ecf20Sopenharmony_ci		.regs = &aud_cg_regs,		\
308c2ecf20Sopenharmony_ci		.shift = _shift,		\
318c2ecf20Sopenharmony_ci		.ops = &mtk_clk_gate_ops_no_setclr,		\
328c2ecf20Sopenharmony_ci	}
338c2ecf20Sopenharmony_ci
348c2ecf20Sopenharmony_cistatic const struct mtk_gate aud_clks[] __initconst = {
358c2ecf20Sopenharmony_ci	GATE_AUD(CLK_AUD_AFE, "aud_afe", "clk26m_ck", 2),
368c2ecf20Sopenharmony_ci	GATE_AUD(CLK_AUD_I2S, "aud_i2s", "i2s_infra_bck", 6),
378c2ecf20Sopenharmony_ci	GATE_AUD(CLK_AUD_22M, "aud_22m", "rg_aud_engen1", 8),
388c2ecf20Sopenharmony_ci	GATE_AUD(CLK_AUD_24M, "aud_24m", "rg_aud_engen2", 9),
398c2ecf20Sopenharmony_ci	GATE_AUD(CLK_AUD_INTDIR, "aud_intdir", "rg_aud_spdif_in", 15),
408c2ecf20Sopenharmony_ci	GATE_AUD(CLK_AUD_APLL2_TUNER, "aud_apll2_tuner", "rg_aud_engen2", 18),
418c2ecf20Sopenharmony_ci	GATE_AUD(CLK_AUD_APLL_TUNER, "aud_apll_tuner", "rg_aud_engen1", 19),
428c2ecf20Sopenharmony_ci	GATE_AUD(CLK_AUD_HDMI, "aud_hdmi", "apll12_div4", 20),
438c2ecf20Sopenharmony_ci	GATE_AUD(CLK_AUD_SPDF, "aud_spdf", "apll12_div6", 21),
448c2ecf20Sopenharmony_ci	GATE_AUD(CLK_AUD_ADC, "aud_adc", "aud_afe", 24),
458c2ecf20Sopenharmony_ci	GATE_AUD(CLK_AUD_DAC, "aud_dac", "aud_afe", 25),
468c2ecf20Sopenharmony_ci	GATE_AUD(CLK_AUD_DAC_PREDIS, "aud_dac_predis", "aud_afe", 26),
478c2ecf20Sopenharmony_ci	GATE_AUD(CLK_AUD_TML, "aud_tml", "aud_afe", 27),
488c2ecf20Sopenharmony_ci};
498c2ecf20Sopenharmony_ci
508c2ecf20Sopenharmony_cistatic void __init mtk_audsys_init(struct device_node *node)
518c2ecf20Sopenharmony_ci{
528c2ecf20Sopenharmony_ci	struct clk_onecell_data *clk_data;
538c2ecf20Sopenharmony_ci	int r;
548c2ecf20Sopenharmony_ci
558c2ecf20Sopenharmony_ci	clk_data = mtk_alloc_clk_data(CLK_AUD_NR_CLK);
568c2ecf20Sopenharmony_ci
578c2ecf20Sopenharmony_ci	mtk_clk_register_gates(node, aud_clks, ARRAY_SIZE(aud_clks), clk_data);
588c2ecf20Sopenharmony_ci
598c2ecf20Sopenharmony_ci	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
608c2ecf20Sopenharmony_ci	if (r)
618c2ecf20Sopenharmony_ci		pr_err("%s(): could not register clock provider: %d\n",
628c2ecf20Sopenharmony_ci			__func__, r);
638c2ecf20Sopenharmony_ci
648c2ecf20Sopenharmony_ci}
658c2ecf20Sopenharmony_ciCLK_OF_DECLARE(mtk_audsys, "mediatek,mt8516-audsys", mtk_audsys_init);
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