1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2014 MediaTek Inc. 4 * Author: James Liao <jamesjj.liao@mediatek.com> 5 */ 6 7#include <linux/clk.h> 8#include <linux/of.h> 9#include <linux/of_address.h> 10 11#include "clk-mtk.h" 12#include "clk-gate.h" 13#include "clk-cpumux.h" 14 15#include <dt-bindings/clock/mt8173-clk.h> 16 17/* 18 * For some clocks, we don't care what their actual rates are. And these 19 * clocks may change their rate on different products or different scenarios. 20 * So we model these clocks' rate as 0, to denote it's not an actual rate. 21 */ 22#define DUMMY_RATE 0 23 24static DEFINE_SPINLOCK(mt8173_clk_lock); 25 26static const struct mtk_fixed_clk fixed_clks[] __initconst = { 27 FIXED_CLK(CLK_TOP_CLKPH_MCK_O, "clkph_mck_o", "clk26m", DUMMY_RATE), 28 FIXED_CLK(CLK_TOP_USB_SYSPLL_125M, "usb_syspll_125m", "clk26m", 125 * MHZ), 29 FIXED_CLK(CLK_TOP_DSI0_DIG, "dsi0_dig", "clk26m", DUMMY_RATE), 30 FIXED_CLK(CLK_TOP_DSI1_DIG, "dsi1_dig", "clk26m", DUMMY_RATE), 31 FIXED_CLK(CLK_TOP_LVDS_PXL, "lvds_pxl", "lvdspll", DUMMY_RATE), 32 FIXED_CLK(CLK_TOP_LVDS_CTS, "lvds_cts", "lvdspll", DUMMY_RATE), 33}; 34 35static const struct mtk_fixed_factor top_divs[] __initconst = { 36 FACTOR(CLK_TOP_ARMCA7PLL_754M, "armca7pll_754m", "armca7pll", 1, 2), 37 FACTOR(CLK_TOP_ARMCA7PLL_502M, "armca7pll_502m", "armca7pll", 1, 3), 38 39 FACTOR(CLK_TOP_MAIN_H546M, "main_h546m", "mainpll", 1, 2), 40 FACTOR(CLK_TOP_MAIN_H364M, "main_h364m", "mainpll", 1, 3), 41 FACTOR(CLK_TOP_MAIN_H218P4M, "main_h218p4m", "mainpll", 1, 5), 42 FACTOR(CLK_TOP_MAIN_H156M, "main_h156m", "mainpll", 1, 7), 43 44 FACTOR(CLK_TOP_TVDPLL_445P5M, "tvdpll_445p5m", "tvdpll", 1, 4), 45 FACTOR(CLK_TOP_TVDPLL_594M, "tvdpll_594m", "tvdpll", 1, 3), 46 47 FACTOR(CLK_TOP_UNIV_624M, "univ_624m", "univpll", 1, 2), 48 FACTOR(CLK_TOP_UNIV_416M, "univ_416m", "univpll", 1, 3), 49 FACTOR(CLK_TOP_UNIV_249P6M, "univ_249p6m", "univpll", 1, 5), 50 FACTOR(CLK_TOP_UNIV_178P3M, "univ_178p3m", "univpll", 1, 7), 51 FACTOR(CLK_TOP_UNIV_48M, "univ_48m", "univpll", 1, 26), 52 53 FACTOR(CLK_TOP_CLKRTC_EXT, "clkrtc_ext", "clk32k", 1, 1), 54 FACTOR(CLK_TOP_CLKRTC_INT, "clkrtc_int", "clk26m", 1, 793), 55 FACTOR(CLK_TOP_FPC, "fpc_ck", "clk26m", 1, 1), 56 57 FACTOR(CLK_TOP_HDMITXPLL_D2, "hdmitxpll_d2", "hdmitx_dig_cts", 1, 2), 58 FACTOR(CLK_TOP_HDMITXPLL_D3, "hdmitxpll_d3", "hdmitx_dig_cts", 1, 3), 59 60 FACTOR(CLK_TOP_ARMCA7PLL_D2, "armca7pll_d2", "armca7pll_754m", 1, 1), 61 FACTOR(CLK_TOP_ARMCA7PLL_D3, "armca7pll_d3", "armca7pll_502m", 1, 1), 62 63 FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, 1), 64 FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1, 1), 65 66 FACTOR(CLK_TOP_DMPLL, "dmpll_ck", "clkph_mck_o", 1, 1), 67 FACTOR(CLK_TOP_DMPLL_D2, "dmpll_d2", "clkph_mck_o", 1, 2), 68 FACTOR(CLK_TOP_DMPLL_D4, "dmpll_d4", "clkph_mck_o", 1, 4), 69 FACTOR(CLK_TOP_DMPLL_D8, "dmpll_d8", "clkph_mck_o", 1, 8), 70 FACTOR(CLK_TOP_DMPLL_D16, "dmpll_d16", "clkph_mck_o", 1, 16), 71 72 FACTOR(CLK_TOP_LVDSPLL_D2, "lvdspll_d2", "lvdspll", 1, 2), 73 FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", "lvdspll", 1, 4), 74 FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", "lvdspll", 1, 8), 75 76 FACTOR(CLK_TOP_MMPLL, "mmpll_ck", "mmpll", 1, 1), 77 FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2), 78 79 FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1, 1), 80 FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2), 81 FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 4), 82 FACTOR(CLK_TOP_MSDCPLL2, "msdcpll2_ck", "msdcpll2", 1, 1), 83 FACTOR(CLK_TOP_MSDCPLL2_D2, "msdcpll2_d2", "msdcpll2", 1, 2), 84 FACTOR(CLK_TOP_MSDCPLL2_D4, "msdcpll2_d4", "msdcpll2", 1, 4), 85 86 FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "main_h546m", 1, 1), 87 FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "main_h546m", 1, 2), 88 FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "main_h546m", 1, 4), 89 FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "main_h546m", 1, 8), 90 FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "main_h546m", 1, 16), 91 FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "main_h364m", 1, 1), 92 FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "main_h364m", 1, 2), 93 FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "main_h364m", 1, 4), 94 FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "main_h218p4m", 1, 1), 95 FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "main_h218p4m", 1, 2), 96 FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "main_h218p4m", 1, 4), 97 FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "main_h156m", 1, 1), 98 FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "main_h156m", 1, 2), 99 FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "main_h156m", 1, 4), 100 101 FACTOR(CLK_TOP_TVDPLL, "tvdpll_ck", "tvdpll_594m", 1, 1), 102 FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_594m", 1, 2), 103 FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll_594m", 1, 4), 104 FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll_594m", 1, 8), 105 FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll_594m", 1, 16), 106 107 FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univ_624m", 1, 1), 108 FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univ_624m", 1, 2), 109 FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univ_624m", 1, 4), 110 FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univ_624m", 1, 8), 111 FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univ_416m", 1, 1), 112 FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univ_416m", 1, 2), 113 FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univ_416m", 1, 4), 114 FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univ_416m", 1, 8), 115 FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univ_249p6m", 1, 1), 116 FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univ_249p6m", 1, 2), 117 FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univ_249p6m", 1, 4), 118 FACTOR(CLK_TOP_UNIVPLL3_D8, "univpll3_d8", "univ_249p6m", 1, 8), 119 FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univ_178p3m", 1, 1), 120 FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univ_48m", 1, 1), 121 FACTOR(CLK_TOP_UNIVPLL_D52, "univpll_d52", "univ_48m", 1, 2), 122 123 FACTOR(CLK_TOP_VCODECPLL, "vcodecpll_ck", "vcodecpll", 1, 3), 124 FACTOR(CLK_TOP_VCODECPLL_370P5, "vcodecpll_370p5", "vcodecpll", 1, 4), 125 126 FACTOR(CLK_TOP_VENCPLL, "vencpll_ck", "vencpll", 1, 1), 127 FACTOR(CLK_TOP_VENCPLL_D2, "vencpll_d2", "vencpll", 1, 2), 128 FACTOR(CLK_TOP_VENCPLL_D4, "vencpll_d4", "vencpll", 1, 4), 129}; 130 131static const char * const axi_parents[] __initconst = { 132 "clk26m", 133 "syspll1_d2", 134 "syspll_d5", 135 "syspll1_d4", 136 "univpll_d5", 137 "univpll2_d2", 138 "dmpll_d2", 139 "dmpll_d4" 140}; 141 142static const char * const mem_parents[] __initconst = { 143 "clk26m", 144 "dmpll_ck" 145}; 146 147static const char * const ddrphycfg_parents[] __initconst = { 148 "clk26m", 149 "syspll1_d8" 150}; 151 152static const char * const mm_parents[] __initconst = { 153 "clk26m", 154 "vencpll_d2", 155 "main_h364m", 156 "syspll1_d2", 157 "syspll_d5", 158 "syspll1_d4", 159 "univpll1_d2", 160 "univpll2_d2", 161 "dmpll_d2" 162}; 163 164static const char * const pwm_parents[] __initconst = { 165 "clk26m", 166 "univpll2_d4", 167 "univpll3_d2", 168 "univpll1_d4" 169}; 170 171static const char * const vdec_parents[] __initconst = { 172 "clk26m", 173 "vcodecpll_ck", 174 "tvdpll_445p5m", 175 "univpll_d3", 176 "vencpll_d2", 177 "syspll_d3", 178 "univpll1_d2", 179 "mmpll_d2", 180 "dmpll_d2", 181 "dmpll_d4" 182}; 183 184static const char * const venc_parents[] __initconst = { 185 "clk26m", 186 "vcodecpll_ck", 187 "tvdpll_445p5m", 188 "univpll_d3", 189 "vencpll_d2", 190 "syspll_d3", 191 "univpll1_d2", 192 "univpll2_d2", 193 "dmpll_d2", 194 "dmpll_d4" 195}; 196 197static const char * const mfg_parents[] __initconst = { 198 "clk26m", 199 "mmpll_ck", 200 "dmpll_ck", 201 "clk26m", 202 "clk26m", 203 "clk26m", 204 "clk26m", 205 "clk26m", 206 "clk26m", 207 "syspll_d3", 208 "syspll1_d2", 209 "syspll_d5", 210 "univpll_d3", 211 "univpll1_d2", 212 "univpll_d5", 213 "univpll2_d2" 214}; 215 216static const char * const camtg_parents[] __initconst = { 217 "clk26m", 218 "univpll_d26", 219 "univpll2_d2", 220 "syspll3_d2", 221 "syspll3_d4", 222 "univpll1_d4" 223}; 224 225static const char * const uart_parents[] __initconst = { 226 "clk26m", 227 "univpll2_d8" 228}; 229 230static const char * const spi_parents[] __initconst = { 231 "clk26m", 232 "syspll3_d2", 233 "syspll1_d4", 234 "syspll4_d2", 235 "univpll3_d2", 236 "univpll2_d4", 237 "univpll1_d8" 238}; 239 240static const char * const usb20_parents[] __initconst = { 241 "clk26m", 242 "univpll1_d8", 243 "univpll3_d4" 244}; 245 246static const char * const usb30_parents[] __initconst = { 247 "clk26m", 248 "univpll3_d2", 249 "usb_syspll_125m", 250 "univpll2_d4" 251}; 252 253static const char * const msdc50_0_h_parents[] __initconst = { 254 "clk26m", 255 "syspll1_d2", 256 "syspll2_d2", 257 "syspll4_d2", 258 "univpll_d5", 259 "univpll1_d4" 260}; 261 262static const char * const msdc50_0_parents[] __initconst = { 263 "clk26m", 264 "msdcpll_ck", 265 "msdcpll_d2", 266 "univpll1_d4", 267 "syspll2_d2", 268 "syspll_d7", 269 "msdcpll_d4", 270 "vencpll_d4", 271 "tvdpll_ck", 272 "univpll_d2", 273 "univpll1_d2", 274 "mmpll_ck", 275 "msdcpll2_ck", 276 "msdcpll2_d2", 277 "msdcpll2_d4" 278}; 279 280static const char * const msdc30_1_parents[] __initconst = { 281 "clk26m", 282 "univpll2_d2", 283 "msdcpll_d4", 284 "univpll1_d4", 285 "syspll2_d2", 286 "syspll_d7", 287 "univpll_d7", 288 "vencpll_d4" 289}; 290 291static const char * const msdc30_2_parents[] __initconst = { 292 "clk26m", 293 "univpll2_d2", 294 "msdcpll_d4", 295 "univpll1_d4", 296 "syspll2_d2", 297 "syspll_d7", 298 "univpll_d7", 299 "vencpll_d2" 300}; 301 302static const char * const msdc30_3_parents[] __initconst = { 303 "clk26m", 304 "msdcpll2_ck", 305 "msdcpll2_d2", 306 "univpll2_d2", 307 "msdcpll2_d4", 308 "msdcpll_d4", 309 "univpll1_d4", 310 "syspll2_d2", 311 "syspll_d7", 312 "univpll_d7", 313 "vencpll_d4", 314 "msdcpll_ck", 315 "msdcpll_d2", 316 "msdcpll_d4" 317}; 318 319static const char * const audio_parents[] __initconst = { 320 "clk26m", 321 "syspll3_d4", 322 "syspll4_d4", 323 "syspll1_d16" 324}; 325 326static const char * const aud_intbus_parents[] __initconst = { 327 "clk26m", 328 "syspll1_d4", 329 "syspll4_d2", 330 "univpll3_d2", 331 "univpll2_d8", 332 "dmpll_d4", 333 "dmpll_d8" 334}; 335 336static const char * const pmicspi_parents[] __initconst = { 337 "clk26m", 338 "syspll1_d8", 339 "syspll3_d4", 340 "syspll1_d16", 341 "univpll3_d4", 342 "univpll_d26", 343 "dmpll_d8", 344 "dmpll_d16" 345}; 346 347static const char * const scp_parents[] __initconst = { 348 "clk26m", 349 "syspll1_d2", 350 "univpll_d5", 351 "syspll_d5", 352 "dmpll_d2", 353 "dmpll_d4" 354}; 355 356static const char * const atb_parents[] __initconst = { 357 "clk26m", 358 "syspll1_d2", 359 "univpll_d5", 360 "dmpll_d2" 361}; 362 363static const char * const venc_lt_parents[] __initconst = { 364 "clk26m", 365 "univpll_d3", 366 "vcodecpll_ck", 367 "tvdpll_445p5m", 368 "vencpll_d2", 369 "syspll_d3", 370 "univpll1_d2", 371 "univpll2_d2", 372 "syspll1_d2", 373 "univpll_d5", 374 "vcodecpll_370p5", 375 "dmpll_ck" 376}; 377 378static const char * const dpi0_parents[] __initconst = { 379 "clk26m", 380 "tvdpll_d2", 381 "tvdpll_d4", 382 "clk26m", 383 "clk26m", 384 "tvdpll_d8", 385 "tvdpll_d16" 386}; 387 388static const char * const irda_parents[] __initconst = { 389 "clk26m", 390 "univpll2_d4", 391 "syspll2_d4" 392}; 393 394static const char * const cci400_parents[] __initconst = { 395 "clk26m", 396 "vencpll_ck", 397 "armca7pll_754m", 398 "armca7pll_502m", 399 "univpll_d2", 400 "syspll_d2", 401 "msdcpll_ck", 402 "dmpll_ck" 403}; 404 405static const char * const aud_1_parents[] __initconst = { 406 "clk26m", 407 "apll1_ck", 408 "univpll2_d4", 409 "univpll2_d8" 410}; 411 412static const char * const aud_2_parents[] __initconst = { 413 "clk26m", 414 "apll2_ck", 415 "univpll2_d4", 416 "univpll2_d8" 417}; 418 419static const char * const mem_mfg_in_parents[] __initconst = { 420 "clk26m", 421 "mmpll_ck", 422 "dmpll_ck", 423 "clk26m" 424}; 425 426static const char * const axi_mfg_in_parents[] __initconst = { 427 "clk26m", 428 "axi_sel", 429 "dmpll_d2" 430}; 431 432static const char * const scam_parents[] __initconst = { 433 "clk26m", 434 "syspll3_d2", 435 "univpll2_d4", 436 "dmpll_d4" 437}; 438 439static const char * const spinfi_ifr_parents[] __initconst = { 440 "clk26m", 441 "univpll2_d8", 442 "univpll3_d4", 443 "syspll4_d2", 444 "univpll2_d4", 445 "univpll3_d2", 446 "syspll1_d4", 447 "univpll1_d4" 448}; 449 450static const char * const hdmi_parents[] __initconst = { 451 "clk26m", 452 "hdmitx_dig_cts", 453 "hdmitxpll_d2", 454 "hdmitxpll_d3" 455}; 456 457static const char * const dpilvds_parents[] __initconst = { 458 "clk26m", 459 "lvdspll", 460 "lvdspll_d2", 461 "lvdspll_d4", 462 "lvdspll_d8", 463 "fpc_ck" 464}; 465 466static const char * const msdc50_2_h_parents[] __initconst = { 467 "clk26m", 468 "syspll1_d2", 469 "syspll2_d2", 470 "syspll4_d2", 471 "univpll_d5", 472 "univpll1_d4" 473}; 474 475static const char * const hdcp_parents[] __initconst = { 476 "clk26m", 477 "syspll4_d2", 478 "syspll3_d4", 479 "univpll2_d4" 480}; 481 482static const char * const hdcp_24m_parents[] __initconst = { 483 "clk26m", 484 "univpll_d26", 485 "univpll_d52", 486 "univpll2_d8" 487}; 488 489static const char * const rtc_parents[] __initconst = { 490 "clkrtc_int", 491 "clkrtc_ext", 492 "clk26m", 493 "univpll3_d8" 494}; 495 496static const char * const i2s0_m_ck_parents[] __initconst = { 497 "apll1_div1", 498 "apll2_div1" 499}; 500 501static const char * const i2s1_m_ck_parents[] __initconst = { 502 "apll1_div2", 503 "apll2_div2" 504}; 505 506static const char * const i2s2_m_ck_parents[] __initconst = { 507 "apll1_div3", 508 "apll2_div3" 509}; 510 511static const char * const i2s3_m_ck_parents[] __initconst = { 512 "apll1_div4", 513 "apll2_div4" 514}; 515 516static const char * const i2s3_b_ck_parents[] __initconst = { 517 "apll1_div5", 518 "apll2_div5" 519}; 520 521static const char * const ca53_parents[] __initconst = { 522 "clk26m", 523 "armca7pll", 524 "mainpll", 525 "univpll" 526}; 527 528static const char * const ca72_parents[] __initconst = { 529 "clk26m", 530 "armca15pll", 531 "mainpll", 532 "univpll" 533}; 534 535static const struct mtk_composite cpu_muxes[] __initconst = { 536 MUX(CLK_INFRA_CA53SEL, "infra_ca53_sel", ca53_parents, 0x0000, 0, 2), 537 MUX(CLK_INFRA_CA72SEL, "infra_ca72_sel", ca72_parents, 0x0000, 2, 2), 538}; 539 540static const struct mtk_composite top_muxes[] __initconst = { 541 /* CLK_CFG_0 */ 542 MUX(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 0x0040, 0, 3), 543 MUX(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x0040, 8, 1), 544 MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents, 0x0040, 16, 1, 23), 545 MUX_GATE(CLK_TOP_MM_SEL, "mm_sel", mm_parents, 0x0040, 24, 4, 31), 546 /* CLK_CFG_1 */ 547 MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x0050, 0, 2, 7), 548 MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents, 0x0050, 8, 4, 15), 549 MUX_GATE(CLK_TOP_VENC_SEL, "venc_sel", venc_parents, 0x0050, 16, 4, 23), 550 MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, 0x0050, 24, 4, 31), 551 /* CLK_CFG_2 */ 552 MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_parents, 0x0060, 0, 3, 7), 553 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x0060, 8, 1, 15), 554 MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x0060, 16, 3, 23), 555 MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel", usb20_parents, 0x0060, 24, 2, 31), 556 /* CLK_CFG_3 */ 557 MUX_GATE(CLK_TOP_USB30_SEL, "usb30_sel", usb30_parents, 0x0070, 0, 2, 7), 558 MUX_GATE(CLK_TOP_MSDC50_0_H_SEL, "msdc50_0_h_sel", msdc50_0_h_parents, 0x0070, 8, 3, 15), 559 MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", msdc50_0_parents, 0x0070, 16, 4, 23), 560 MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_1_parents, 0x0070, 24, 3, 31), 561 /* CLK_CFG_4 */ 562 MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", msdc30_2_parents, 0x0080, 0, 3, 7), 563 MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel", msdc30_3_parents, 0x0080, 8, 4, 15), 564 MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents, 0x0080, 16, 2, 23), 565 MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents, 0x0080, 24, 3, 31), 566 /* CLK_CFG_5 */ 567 MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents, 0x0090, 0, 3, 7 /* 7:5 */), 568 MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", scp_parents, 0x0090, 8, 3, 15), 569 MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel", atb_parents, 0x0090, 16, 2, 23), 570 MUX_GATE(CLK_TOP_VENC_LT_SEL, "venclt_sel", venc_lt_parents, 0x0090, 24, 4, 31), 571 /* CLK_CFG_6 */ 572 /* 573 * The dpi0_sel clock should not propagate rate changes to its parent 574 * clock so the dpi driver can have full control over PLL and divider. 575 */ 576 MUX_GATE_FLAGS(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_parents, 0x00a0, 0, 3, 7, 0), 577 MUX_GATE(CLK_TOP_IRDA_SEL, "irda_sel", irda_parents, 0x00a0, 8, 2, 15), 578 MUX_GATE(CLK_TOP_CCI400_SEL, "cci400_sel", cci400_parents, 0x00a0, 16, 3, 23), 579 MUX_GATE(CLK_TOP_AUD_1_SEL, "aud_1_sel", aud_1_parents, 0x00a0, 24, 2, 31), 580 /* CLK_CFG_7 */ 581 MUX_GATE(CLK_TOP_AUD_2_SEL, "aud_2_sel", aud_2_parents, 0x00b0, 0, 2, 7), 582 MUX_GATE(CLK_TOP_MEM_MFG_IN_SEL, "mem_mfg_in_sel", mem_mfg_in_parents, 0x00b0, 8, 2, 15), 583 MUX_GATE(CLK_TOP_AXI_MFG_IN_SEL, "axi_mfg_in_sel", axi_mfg_in_parents, 0x00b0, 16, 2, 23), 584 MUX_GATE(CLK_TOP_SCAM_SEL, "scam_sel", scam_parents, 0x00b0, 24, 2, 31), 585 /* CLK_CFG_12 */ 586 MUX_GATE(CLK_TOP_SPINFI_IFR_SEL, "spinfi_ifr_sel", spinfi_ifr_parents, 0x00c0, 0, 3, 7), 587 MUX_GATE(CLK_TOP_HDMI_SEL, "hdmi_sel", hdmi_parents, 0x00c0, 8, 2, 15), 588 MUX_GATE(CLK_TOP_DPILVDS_SEL, "dpilvds_sel", dpilvds_parents, 0x00c0, 24, 3, 31), 589 /* CLK_CFG_13 */ 590 MUX_GATE(CLK_TOP_MSDC50_2_H_SEL, "msdc50_2_h_sel", msdc50_2_h_parents, 0x00d0, 0, 3, 7), 591 MUX_GATE(CLK_TOP_HDCP_SEL, "hdcp_sel", hdcp_parents, 0x00d0, 8, 2, 15), 592 MUX_GATE(CLK_TOP_HDCP_24M_SEL, "hdcp_24m_sel", hdcp_24m_parents, 0x00d0, 16, 2, 23), 593 MUX(CLK_TOP_RTC_SEL, "rtc_sel", rtc_parents, 0x00d0, 24, 2), 594 595 DIV_GATE(CLK_TOP_APLL1_DIV0, "apll1_div0", "aud_1_sel", 0x12c, 8, 0x120, 4, 24), 596 DIV_GATE(CLK_TOP_APLL1_DIV1, "apll1_div1", "aud_1_sel", 0x12c, 9, 0x124, 8, 0), 597 DIV_GATE(CLK_TOP_APLL1_DIV2, "apll1_div2", "aud_1_sel", 0x12c, 10, 0x124, 8, 8), 598 DIV_GATE(CLK_TOP_APLL1_DIV3, "apll1_div3", "aud_1_sel", 0x12c, 11, 0x124, 8, 16), 599 DIV_GATE(CLK_TOP_APLL1_DIV4, "apll1_div4", "aud_1_sel", 0x12c, 12, 0x124, 8, 24), 600 DIV_GATE(CLK_TOP_APLL1_DIV5, "apll1_div5", "apll1_div4", 0x12c, 13, 0x12c, 4, 0), 601 602 DIV_GATE(CLK_TOP_APLL2_DIV0, "apll2_div0", "aud_2_sel", 0x12c, 16, 0x120, 4, 28), 603 DIV_GATE(CLK_TOP_APLL2_DIV1, "apll2_div1", "aud_2_sel", 0x12c, 17, 0x128, 8, 0), 604 DIV_GATE(CLK_TOP_APLL2_DIV2, "apll2_div2", "aud_2_sel", 0x12c, 18, 0x128, 8, 8), 605 DIV_GATE(CLK_TOP_APLL2_DIV3, "apll2_div3", "aud_2_sel", 0x12c, 19, 0x128, 8, 16), 606 DIV_GATE(CLK_TOP_APLL2_DIV4, "apll2_div4", "aud_2_sel", 0x12c, 20, 0x128, 8, 24), 607 DIV_GATE(CLK_TOP_APLL2_DIV5, "apll2_div5", "apll2_div4", 0x12c, 21, 0x12c, 4, 4), 608 609 MUX(CLK_TOP_I2S0_M_SEL, "i2s0_m_ck_sel", i2s0_m_ck_parents, 0x120, 4, 1), 610 MUX(CLK_TOP_I2S1_M_SEL, "i2s1_m_ck_sel", i2s1_m_ck_parents, 0x120, 5, 1), 611 MUX(CLK_TOP_I2S2_M_SEL, "i2s2_m_ck_sel", i2s2_m_ck_parents, 0x120, 6, 1), 612 MUX(CLK_TOP_I2S3_M_SEL, "i2s3_m_ck_sel", i2s3_m_ck_parents, 0x120, 7, 1), 613 MUX(CLK_TOP_I2S3_B_SEL, "i2s3_b_ck_sel", i2s3_b_ck_parents, 0x120, 8, 1), 614}; 615 616static const struct mtk_gate_regs infra_cg_regs __initconst = { 617 .set_ofs = 0x0040, 618 .clr_ofs = 0x0044, 619 .sta_ofs = 0x0048, 620}; 621 622#define GATE_ICG(_id, _name, _parent, _shift) { \ 623 .id = _id, \ 624 .name = _name, \ 625 .parent_name = _parent, \ 626 .regs = &infra_cg_regs, \ 627 .shift = _shift, \ 628 .ops = &mtk_clk_gate_ops_setclr, \ 629 } 630 631static const struct mtk_gate infra_clks[] __initconst = { 632 GATE_ICG(CLK_INFRA_DBGCLK, "infra_dbgclk", "axi_sel", 0), 633 GATE_ICG(CLK_INFRA_SMI, "infra_smi", "mm_sel", 1), 634 GATE_ICG(CLK_INFRA_AUDIO, "infra_audio", "aud_intbus_sel", 5), 635 GATE_ICG(CLK_INFRA_GCE, "infra_gce", "axi_sel", 6), 636 GATE_ICG(CLK_INFRA_L2C_SRAM, "infra_l2c_sram", "axi_sel", 7), 637 GATE_ICG(CLK_INFRA_M4U, "infra_m4u", "mem_sel", 8), 638 GATE_ICG(CLK_INFRA_CPUM, "infra_cpum", "cpum_ck", 15), 639 GATE_ICG(CLK_INFRA_KP, "infra_kp", "axi_sel", 16), 640 GATE_ICG(CLK_INFRA_CEC, "infra_cec", "clk26m", 18), 641 GATE_ICG(CLK_INFRA_PMICSPI, "infra_pmicspi", "pmicspi_sel", 22), 642 GATE_ICG(CLK_INFRA_PMICWRAP, "infra_pmicwrap", "axi_sel", 23), 643}; 644 645static const struct mtk_fixed_factor infra_divs[] __initconst = { 646 FACTOR(CLK_INFRA_CLK_13M, "clk13m", "clk26m", 1, 2), 647}; 648 649static const struct mtk_gate_regs peri0_cg_regs __initconst = { 650 .set_ofs = 0x0008, 651 .clr_ofs = 0x0010, 652 .sta_ofs = 0x0018, 653}; 654 655static const struct mtk_gate_regs peri1_cg_regs __initconst = { 656 .set_ofs = 0x000c, 657 .clr_ofs = 0x0014, 658 .sta_ofs = 0x001c, 659}; 660 661#define GATE_PERI0(_id, _name, _parent, _shift) { \ 662 .id = _id, \ 663 .name = _name, \ 664 .parent_name = _parent, \ 665 .regs = &peri0_cg_regs, \ 666 .shift = _shift, \ 667 .ops = &mtk_clk_gate_ops_setclr, \ 668 } 669 670#define GATE_PERI1(_id, _name, _parent, _shift) { \ 671 .id = _id, \ 672 .name = _name, \ 673 .parent_name = _parent, \ 674 .regs = &peri1_cg_regs, \ 675 .shift = _shift, \ 676 .ops = &mtk_clk_gate_ops_setclr, \ 677 } 678 679static const struct mtk_gate peri_gates[] __initconst = { 680 /* PERI0 */ 681 GATE_PERI0(CLK_PERI_NFI, "peri_nfi", "axi_sel", 0), 682 GATE_PERI0(CLK_PERI_THERM, "peri_therm", "axi_sel", 1), 683 GATE_PERI0(CLK_PERI_PWM1, "peri_pwm1", "axi_sel", 2), 684 GATE_PERI0(CLK_PERI_PWM2, "peri_pwm2", "axi_sel", 3), 685 GATE_PERI0(CLK_PERI_PWM3, "peri_pwm3", "axi_sel", 4), 686 GATE_PERI0(CLK_PERI_PWM4, "peri_pwm4", "axi_sel", 5), 687 GATE_PERI0(CLK_PERI_PWM5, "peri_pwm5", "axi_sel", 6), 688 GATE_PERI0(CLK_PERI_PWM6, "peri_pwm6", "axi_sel", 7), 689 GATE_PERI0(CLK_PERI_PWM7, "peri_pwm7", "axi_sel", 8), 690 GATE_PERI0(CLK_PERI_PWM, "peri_pwm", "axi_sel", 9), 691 GATE_PERI0(CLK_PERI_USB0, "peri_usb0", "usb20_sel", 10), 692 GATE_PERI0(CLK_PERI_USB1, "peri_usb1", "usb20_sel", 11), 693 GATE_PERI0(CLK_PERI_AP_DMA, "peri_ap_dma", "axi_sel", 12), 694 GATE_PERI0(CLK_PERI_MSDC30_0, "peri_msdc30_0", "msdc50_0_sel", 13), 695 GATE_PERI0(CLK_PERI_MSDC30_1, "peri_msdc30_1", "msdc30_1_sel", 14), 696 GATE_PERI0(CLK_PERI_MSDC30_2, "peri_msdc30_2", "msdc30_2_sel", 15), 697 GATE_PERI0(CLK_PERI_MSDC30_3, "peri_msdc30_3", "msdc30_3_sel", 16), 698 GATE_PERI0(CLK_PERI_NLI_ARB, "peri_nli_arb", "axi_sel", 17), 699 GATE_PERI0(CLK_PERI_IRDA, "peri_irda", "irda_sel", 18), 700 GATE_PERI0(CLK_PERI_UART0, "peri_uart0", "axi_sel", 19), 701 GATE_PERI0(CLK_PERI_UART1, "peri_uart1", "axi_sel", 20), 702 GATE_PERI0(CLK_PERI_UART2, "peri_uart2", "axi_sel", 21), 703 GATE_PERI0(CLK_PERI_UART3, "peri_uart3", "axi_sel", 22), 704 GATE_PERI0(CLK_PERI_I2C0, "peri_i2c0", "axi_sel", 23), 705 GATE_PERI0(CLK_PERI_I2C1, "peri_i2c1", "axi_sel", 24), 706 GATE_PERI0(CLK_PERI_I2C2, "peri_i2c2", "axi_sel", 25), 707 GATE_PERI0(CLK_PERI_I2C3, "peri_i2c3", "axi_sel", 26), 708 GATE_PERI0(CLK_PERI_I2C4, "peri_i2c4", "axi_sel", 27), 709 GATE_PERI0(CLK_PERI_AUXADC, "peri_auxadc", "clk26m", 28), 710 GATE_PERI0(CLK_PERI_SPI0, "peri_spi0", "spi_sel", 29), 711 GATE_PERI0(CLK_PERI_I2C5, "peri_i2c5", "axi_sel", 30), 712 GATE_PERI0(CLK_PERI_NFIECC, "peri_nfiecc", "axi_sel", 31), 713 /* PERI1 */ 714 GATE_PERI1(CLK_PERI_SPI, "peri_spi", "spi_sel", 0), 715 GATE_PERI1(CLK_PERI_IRRX, "peri_irrx", "spi_sel", 1), 716 GATE_PERI1(CLK_PERI_I2C6, "peri_i2c6", "axi_sel", 2), 717}; 718 719static const char * const uart_ck_sel_parents[] __initconst = { 720 "clk26m", 721 "uart_sel", 722}; 723 724static const struct mtk_composite peri_clks[] __initconst = { 725 MUX(CLK_PERI_UART0_SEL, "uart0_ck_sel", uart_ck_sel_parents, 0x40c, 0, 1), 726 MUX(CLK_PERI_UART1_SEL, "uart1_ck_sel", uart_ck_sel_parents, 0x40c, 1, 1), 727 MUX(CLK_PERI_UART2_SEL, "uart2_ck_sel", uart_ck_sel_parents, 0x40c, 2, 1), 728 MUX(CLK_PERI_UART3_SEL, "uart3_ck_sel", uart_ck_sel_parents, 0x40c, 3, 1), 729}; 730 731static const struct mtk_gate_regs cg_regs_4_8_0 __initconst = { 732 .set_ofs = 0x0004, 733 .clr_ofs = 0x0008, 734 .sta_ofs = 0x0000, 735}; 736 737#define GATE_IMG(_id, _name, _parent, _shift) { \ 738 .id = _id, \ 739 .name = _name, \ 740 .parent_name = _parent, \ 741 .regs = &cg_regs_4_8_0, \ 742 .shift = _shift, \ 743 .ops = &mtk_clk_gate_ops_setclr, \ 744 } 745 746static const struct mtk_gate img_clks[] __initconst = { 747 GATE_IMG(CLK_IMG_LARB2_SMI, "img_larb2_smi", "mm_sel", 0), 748 GATE_IMG(CLK_IMG_CAM_SMI, "img_cam_smi", "mm_sel", 5), 749 GATE_IMG(CLK_IMG_CAM_CAM, "img_cam_cam", "mm_sel", 6), 750 GATE_IMG(CLK_IMG_SEN_TG, "img_sen_tg", "camtg_sel", 7), 751 GATE_IMG(CLK_IMG_SEN_CAM, "img_sen_cam", "mm_sel", 8), 752 GATE_IMG(CLK_IMG_CAM_SV, "img_cam_sv", "mm_sel", 9), 753 GATE_IMG(CLK_IMG_FD, "img_fd", "mm_sel", 11), 754}; 755 756static const struct mtk_gate_regs vdec0_cg_regs __initconst = { 757 .set_ofs = 0x0000, 758 .clr_ofs = 0x0004, 759 .sta_ofs = 0x0000, 760}; 761 762static const struct mtk_gate_regs vdec1_cg_regs __initconst = { 763 .set_ofs = 0x0008, 764 .clr_ofs = 0x000c, 765 .sta_ofs = 0x0008, 766}; 767 768#define GATE_VDEC0(_id, _name, _parent, _shift) { \ 769 .id = _id, \ 770 .name = _name, \ 771 .parent_name = _parent, \ 772 .regs = &vdec0_cg_regs, \ 773 .shift = _shift, \ 774 .ops = &mtk_clk_gate_ops_setclr_inv, \ 775 } 776 777#define GATE_VDEC1(_id, _name, _parent, _shift) { \ 778 .id = _id, \ 779 .name = _name, \ 780 .parent_name = _parent, \ 781 .regs = &vdec1_cg_regs, \ 782 .shift = _shift, \ 783 .ops = &mtk_clk_gate_ops_setclr_inv, \ 784 } 785 786static const struct mtk_gate vdec_clks[] __initconst = { 787 GATE_VDEC0(CLK_VDEC_CKEN, "vdec_cken", "vdec_sel", 0), 788 GATE_VDEC1(CLK_VDEC_LARB_CKEN, "vdec_larb_cken", "mm_sel", 0), 789}; 790 791#define GATE_VENC(_id, _name, _parent, _shift) { \ 792 .id = _id, \ 793 .name = _name, \ 794 .parent_name = _parent, \ 795 .regs = &cg_regs_4_8_0, \ 796 .shift = _shift, \ 797 .ops = &mtk_clk_gate_ops_setclr_inv, \ 798 } 799 800static const struct mtk_gate venc_clks[] __initconst = { 801 GATE_VENC(CLK_VENC_CKE0, "venc_cke0", "mm_sel", 0), 802 GATE_VENC(CLK_VENC_CKE1, "venc_cke1", "venc_sel", 4), 803 GATE_VENC(CLK_VENC_CKE2, "venc_cke2", "venc_sel", 8), 804 GATE_VENC(CLK_VENC_CKE3, "venc_cke3", "venc_sel", 12), 805}; 806 807#define GATE_VENCLT(_id, _name, _parent, _shift) { \ 808 .id = _id, \ 809 .name = _name, \ 810 .parent_name = _parent, \ 811 .regs = &cg_regs_4_8_0, \ 812 .shift = _shift, \ 813 .ops = &mtk_clk_gate_ops_setclr_inv, \ 814 } 815 816static const struct mtk_gate venclt_clks[] __initconst = { 817 GATE_VENCLT(CLK_VENCLT_CKE0, "venclt_cke0", "mm_sel", 0), 818 GATE_VENCLT(CLK_VENCLT_CKE1, "venclt_cke1", "venclt_sel", 4), 819}; 820 821static struct clk_onecell_data *mt8173_top_clk_data __initdata; 822static struct clk_onecell_data *mt8173_pll_clk_data __initdata; 823 824static void __init mtk_clk_enable_critical(void) 825{ 826 if (!mt8173_top_clk_data || !mt8173_pll_clk_data) 827 return; 828 829 clk_prepare_enable(mt8173_pll_clk_data->clks[CLK_APMIXED_ARMCA15PLL]); 830 clk_prepare_enable(mt8173_pll_clk_data->clks[CLK_APMIXED_ARMCA7PLL]); 831 clk_prepare_enable(mt8173_top_clk_data->clks[CLK_TOP_MEM_SEL]); 832 clk_prepare_enable(mt8173_top_clk_data->clks[CLK_TOP_DDRPHYCFG_SEL]); 833 clk_prepare_enable(mt8173_top_clk_data->clks[CLK_TOP_CCI400_SEL]); 834 clk_prepare_enable(mt8173_top_clk_data->clks[CLK_TOP_RTC_SEL]); 835} 836 837static void __init mtk_topckgen_init(struct device_node *node) 838{ 839 struct clk_onecell_data *clk_data; 840 void __iomem *base; 841 int r; 842 843 base = of_iomap(node, 0); 844 if (!base) { 845 pr_err("%s(): ioremap failed\n", __func__); 846 return; 847 } 848 849 mt8173_top_clk_data = clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK); 850 851 mtk_clk_register_fixed_clks(fixed_clks, ARRAY_SIZE(fixed_clks), clk_data); 852 mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); 853 mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base, 854 &mt8173_clk_lock, clk_data); 855 856 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 857 if (r) 858 pr_err("%s(): could not register clock provider: %d\n", 859 __func__, r); 860 861 mtk_clk_enable_critical(); 862} 863CLK_OF_DECLARE(mtk_topckgen, "mediatek,mt8173-topckgen", mtk_topckgen_init); 864 865static void __init mtk_infrasys_init(struct device_node *node) 866{ 867 struct clk_onecell_data *clk_data; 868 int r; 869 870 clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK); 871 872 mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), 873 clk_data); 874 mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data); 875 876 mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes), 877 clk_data); 878 879 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 880 if (r) 881 pr_err("%s(): could not register clock provider: %d\n", 882 __func__, r); 883 884 mtk_register_reset_controller(node, 2, 0x30); 885} 886CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt8173-infracfg", mtk_infrasys_init); 887 888static void __init mtk_pericfg_init(struct device_node *node) 889{ 890 struct clk_onecell_data *clk_data; 891 int r; 892 void __iomem *base; 893 894 base = of_iomap(node, 0); 895 if (!base) { 896 pr_err("%s(): ioremap failed\n", __func__); 897 return; 898 } 899 900 clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK); 901 902 mtk_clk_register_gates(node, peri_gates, ARRAY_SIZE(peri_gates), 903 clk_data); 904 mtk_clk_register_composites(peri_clks, ARRAY_SIZE(peri_clks), base, 905 &mt8173_clk_lock, clk_data); 906 907 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 908 if (r) 909 pr_err("%s(): could not register clock provider: %d\n", 910 __func__, r); 911 912 mtk_register_reset_controller(node, 2, 0); 913} 914CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt8173-pericfg", mtk_pericfg_init); 915 916struct mtk_clk_usb { 917 int id; 918 const char *name; 919 const char *parent; 920 u32 reg_ofs; 921}; 922 923#define APMIXED_USB(_id, _name, _parent, _reg_ofs) { \ 924 .id = _id, \ 925 .name = _name, \ 926 .parent = _parent, \ 927 .reg_ofs = _reg_ofs, \ 928 } 929 930static const struct mtk_clk_usb apmixed_usb[] __initconst = { 931 APMIXED_USB(CLK_APMIXED_REF2USB_TX, "ref2usb_tx", "clk26m", 0x8), 932}; 933 934#define MT8173_PLL_FMAX (3000UL * MHZ) 935 936#define CON0_MT8173_RST_BAR BIT(24) 937 938#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ 939 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \ 940 _pcw_shift, _div_table) { \ 941 .id = _id, \ 942 .name = _name, \ 943 .reg = _reg, \ 944 .pwr_reg = _pwr_reg, \ 945 .en_mask = _en_mask, \ 946 .flags = _flags, \ 947 .rst_bar_mask = CON0_MT8173_RST_BAR, \ 948 .fmax = MT8173_PLL_FMAX, \ 949 .pcwbits = _pcwbits, \ 950 .pd_reg = _pd_reg, \ 951 .pd_shift = _pd_shift, \ 952 .tuner_reg = _tuner_reg, \ 953 .pcw_reg = _pcw_reg, \ 954 .pcw_shift = _pcw_shift, \ 955 .div_table = _div_table, \ 956 } 957 958#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ 959 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \ 960 _pcw_shift) \ 961 PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ 962 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \ 963 NULL) 964 965static const struct mtk_pll_div_table mmpll_div_table[] = { 966 { .div = 0, .freq = MT8173_PLL_FMAX }, 967 { .div = 1, .freq = 1000000000 }, 968 { .div = 2, .freq = 702000000 }, 969 { .div = 3, .freq = 253500000 }, 970 { .div = 4, .freq = 126750000 }, 971 { } /* sentinel */ 972}; 973 974static const struct mtk_pll_data plls[] = { 975 PLL(CLK_APMIXED_ARMCA15PLL, "armca15pll", 0x200, 0x20c, 0x00000001, 0, 21, 0x204, 24, 0x0, 0x204, 0), 976 PLL(CLK_APMIXED_ARMCA7PLL, "armca7pll", 0x210, 0x21c, 0x00000001, 0, 21, 0x214, 24, 0x0, 0x214, 0), 977 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x220, 0x22c, 0xf0000101, HAVE_RST_BAR, 21, 0x220, 4, 0x0, 0x224, 0), 978 PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x230, 0x23c, 0xfe000001, HAVE_RST_BAR, 7, 0x230, 4, 0x0, 0x234, 14), 979 PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x240, 0x24c, 0x00000001, 0, 21, 0x244, 24, 0x0, 0x244, 0, mmpll_div_table), 980 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x250, 0x25c, 0x00000001, 0, 21, 0x250, 4, 0x0, 0x254, 0), 981 PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x260, 0x26c, 0x00000001, 0, 21, 0x260, 4, 0x0, 0x264, 0), 982 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x270, 0x27c, 0x00000001, 0, 21, 0x270, 4, 0x0, 0x274, 0), 983 PLL(CLK_APMIXED_MPLL, "mpll", 0x280, 0x28c, 0x00000001, 0, 21, 0x280, 4, 0x0, 0x284, 0), 984 PLL(CLK_APMIXED_VCODECPLL, "vcodecpll", 0x290, 0x29c, 0x00000001, 0, 21, 0x290, 4, 0x0, 0x294, 0), 985 PLL(CLK_APMIXED_APLL1, "apll1", 0x2a0, 0x2b0, 0x00000001, 0, 31, 0x2a0, 4, 0x2a4, 0x2a4, 0), 986 PLL(CLK_APMIXED_APLL2, "apll2", 0x2b4, 0x2c4, 0x00000001, 0, 31, 0x2b4, 4, 0x2b8, 0x2b8, 0), 987 PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x2d0, 0x2dc, 0x00000001, 0, 21, 0x2d0, 4, 0x0, 0x2d4, 0), 988 PLL(CLK_APMIXED_MSDCPLL2, "msdcpll2", 0x2f0, 0x2fc, 0x00000001, 0, 21, 0x2f0, 4, 0x0, 0x2f4, 0), 989}; 990 991static void __init mtk_apmixedsys_init(struct device_node *node) 992{ 993 struct clk_onecell_data *clk_data; 994 void __iomem *base; 995 struct clk *clk; 996 int r, i; 997 998 base = of_iomap(node, 0); 999 if (!base) { 1000 pr_err("%s(): ioremap failed\n", __func__); 1001 return; 1002 } 1003 1004 mt8173_pll_clk_data = clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK); 1005 if (!clk_data) { 1006 iounmap(base); 1007 return; 1008 } 1009 1010 mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); 1011 1012 for (i = 0; i < ARRAY_SIZE(apmixed_usb); i++) { 1013 const struct mtk_clk_usb *cku = &apmixed_usb[i]; 1014 1015 clk = mtk_clk_register_ref2usb_tx(cku->name, cku->parent, 1016 base + cku->reg_ofs); 1017 1018 if (IS_ERR(clk)) { 1019 pr_err("Failed to register clk %s: %ld\n", cku->name, 1020 PTR_ERR(clk)); 1021 continue; 1022 } 1023 1024 clk_data->clks[cku->id] = clk; 1025 } 1026 1027 clk = clk_register_divider(NULL, "hdmi_ref", "tvdpll_594m", 0, 1028 base + 0x40, 16, 3, CLK_DIVIDER_POWER_OF_TWO, 1029 NULL); 1030 clk_data->clks[CLK_APMIXED_HDMI_REF] = clk; 1031 1032 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 1033 if (r) 1034 pr_err("%s(): could not register clock provider: %d\n", 1035 __func__, r); 1036 1037 mtk_clk_enable_critical(); 1038} 1039CLK_OF_DECLARE(mtk_apmixedsys, "mediatek,mt8173-apmixedsys", 1040 mtk_apmixedsys_init); 1041 1042static void __init mtk_imgsys_init(struct device_node *node) 1043{ 1044 struct clk_onecell_data *clk_data; 1045 int r; 1046 1047 clk_data = mtk_alloc_clk_data(CLK_IMG_NR_CLK); 1048 1049 mtk_clk_register_gates(node, img_clks, ARRAY_SIZE(img_clks), 1050 clk_data); 1051 1052 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 1053 1054 if (r) 1055 pr_err("%s(): could not register clock provider: %d\n", 1056 __func__, r); 1057} 1058CLK_OF_DECLARE(mtk_imgsys, "mediatek,mt8173-imgsys", mtk_imgsys_init); 1059 1060static void __init mtk_vdecsys_init(struct device_node *node) 1061{ 1062 struct clk_onecell_data *clk_data; 1063 int r; 1064 1065 clk_data = mtk_alloc_clk_data(CLK_VDEC_NR_CLK); 1066 1067 mtk_clk_register_gates(node, vdec_clks, ARRAY_SIZE(vdec_clks), 1068 clk_data); 1069 1070 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 1071 if (r) 1072 pr_err("%s(): could not register clock provider: %d\n", 1073 __func__, r); 1074} 1075CLK_OF_DECLARE(mtk_vdecsys, "mediatek,mt8173-vdecsys", mtk_vdecsys_init); 1076 1077static void __init mtk_vencsys_init(struct device_node *node) 1078{ 1079 struct clk_onecell_data *clk_data; 1080 int r; 1081 1082 clk_data = mtk_alloc_clk_data(CLK_VENC_NR_CLK); 1083 1084 mtk_clk_register_gates(node, venc_clks, ARRAY_SIZE(venc_clks), 1085 clk_data); 1086 1087 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 1088 if (r) 1089 pr_err("%s(): could not register clock provider: %d\n", 1090 __func__, r); 1091} 1092CLK_OF_DECLARE(mtk_vencsys, "mediatek,mt8173-vencsys", mtk_vencsys_init); 1093 1094static void __init mtk_vencltsys_init(struct device_node *node) 1095{ 1096 struct clk_onecell_data *clk_data; 1097 int r; 1098 1099 clk_data = mtk_alloc_clk_data(CLK_VENCLT_NR_CLK); 1100 1101 mtk_clk_register_gates(node, venclt_clks, ARRAY_SIZE(venclt_clks), 1102 clk_data); 1103 1104 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 1105 if (r) 1106 pr_err("%s(): could not register clock provider: %d\n", 1107 __func__, r); 1108} 1109CLK_OF_DECLARE(mtk_vencltsys, "mediatek,mt8173-vencltsys", mtk_vencltsys_init); 1110