1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2014 MediaTek Inc. 4 * Author: James Liao <jamesjj.liao@mediatek.com> 5 */ 6 7#include <linux/clk-provider.h> 8#include <linux/of_device.h> 9#include <linux/platform_device.h> 10 11#include "clk-gate.h" 12#include "clk-mtk.h" 13 14#include <dt-bindings/clock/mt8173-clk.h> 15 16static const struct mtk_gate_regs mm0_cg_regs = { 17 .set_ofs = 0x0104, 18 .clr_ofs = 0x0108, 19 .sta_ofs = 0x0100, 20}; 21 22static const struct mtk_gate_regs mm1_cg_regs = { 23 .set_ofs = 0x0114, 24 .clr_ofs = 0x0118, 25 .sta_ofs = 0x0110, 26}; 27 28#define GATE_MM0(_id, _name, _parent, _shift) { \ 29 .id = _id, \ 30 .name = _name, \ 31 .parent_name = _parent, \ 32 .regs = &mm0_cg_regs, \ 33 .shift = _shift, \ 34 .ops = &mtk_clk_gate_ops_setclr, \ 35 } 36 37#define GATE_MM1(_id, _name, _parent, _shift) { \ 38 .id = _id, \ 39 .name = _name, \ 40 .parent_name = _parent, \ 41 .regs = &mm1_cg_regs, \ 42 .shift = _shift, \ 43 .ops = &mtk_clk_gate_ops_setclr, \ 44 } 45 46static const struct mtk_gate mt8173_mm_clks[] = { 47 /* MM0 */ 48 GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "mm_sel", 0), 49 GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1), 50 GATE_MM0(CLK_MM_CAM_MDP, "mm_cam_mdp", "mm_sel", 2), 51 GATE_MM0(CLK_MM_MDP_RDMA0, "mm_mdp_rdma0", "mm_sel", 3), 52 GATE_MM0(CLK_MM_MDP_RDMA1, "mm_mdp_rdma1", "mm_sel", 4), 53 GATE_MM0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_sel", 5), 54 GATE_MM0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 6), 55 GATE_MM0(CLK_MM_MDP_RSZ2, "mm_mdp_rsz2", "mm_sel", 7), 56 GATE_MM0(CLK_MM_MDP_TDSHP0, "mm_mdp_tdshp0", "mm_sel", 8), 57 GATE_MM0(CLK_MM_MDP_TDSHP1, "mm_mdp_tdshp1", "mm_sel", 9), 58 GATE_MM0(CLK_MM_MDP_WDMA, "mm_mdp_wdma", "mm_sel", 11), 59 GATE_MM0(CLK_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_sel", 12), 60 GATE_MM0(CLK_MM_MDP_WROT1, "mm_mdp_wrot1", "mm_sel", 13), 61 GATE_MM0(CLK_MM_FAKE_ENG, "mm_fake_eng", "mm_sel", 14), 62 GATE_MM0(CLK_MM_MUTEX_32K, "mm_mutex_32k", "rtc_sel", 15), 63 GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "mm_sel", 16), 64 GATE_MM0(CLK_MM_DISP_OVL1, "mm_disp_ovl1", "mm_sel", 17), 65 GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_sel", 18), 66 GATE_MM0(CLK_MM_DISP_RDMA1, "mm_disp_rdma1", "mm_sel", 19), 67 GATE_MM0(CLK_MM_DISP_RDMA2, "mm_disp_rdma2", "mm_sel", 20), 68 GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_sel", 21), 69 GATE_MM0(CLK_MM_DISP_WDMA1, "mm_disp_wdma1", "mm_sel", 22), 70 GATE_MM0(CLK_MM_DISP_COLOR0, "mm_disp_color0", "mm_sel", 23), 71 GATE_MM0(CLK_MM_DISP_COLOR1, "mm_disp_color1", "mm_sel", 24), 72 GATE_MM0(CLK_MM_DISP_AAL, "mm_disp_aal", "mm_sel", 25), 73 GATE_MM0(CLK_MM_DISP_GAMMA, "mm_disp_gamma", "mm_sel", 26), 74 GATE_MM0(CLK_MM_DISP_UFOE, "mm_disp_ufoe", "mm_sel", 27), 75 GATE_MM0(CLK_MM_DISP_SPLIT0, "mm_disp_split0", "mm_sel", 28), 76 GATE_MM0(CLK_MM_DISP_SPLIT1, "mm_disp_split1", "mm_sel", 29), 77 GATE_MM0(CLK_MM_DISP_MERGE, "mm_disp_merge", "mm_sel", 30), 78 GATE_MM0(CLK_MM_DISP_OD, "mm_disp_od", "mm_sel", 31), 79 /* MM1 */ 80 GATE_MM1(CLK_MM_DISP_PWM0MM, "mm_disp_pwm0mm", "mm_sel", 0), 81 GATE_MM1(CLK_MM_DISP_PWM026M, "mm_disp_pwm026m", "pwm_sel", 1), 82 GATE_MM1(CLK_MM_DISP_PWM1MM, "mm_disp_pwm1mm", "mm_sel", 2), 83 GATE_MM1(CLK_MM_DISP_PWM126M, "mm_disp_pwm126m", "pwm_sel", 3), 84 GATE_MM1(CLK_MM_DSI0_ENGINE, "mm_dsi0_engine", "mm_sel", 4), 85 GATE_MM1(CLK_MM_DSI0_DIGITAL, "mm_dsi0_digital", "dsi0_dig", 5), 86 GATE_MM1(CLK_MM_DSI1_ENGINE, "mm_dsi1_engine", "mm_sel", 6), 87 GATE_MM1(CLK_MM_DSI1_DIGITAL, "mm_dsi1_digital", "dsi1_dig", 7), 88 GATE_MM1(CLK_MM_DPI_PIXEL, "mm_dpi_pixel", "dpi0_sel", 8), 89 GATE_MM1(CLK_MM_DPI_ENGINE, "mm_dpi_engine", "mm_sel", 9), 90 GATE_MM1(CLK_MM_DPI1_PIXEL, "mm_dpi1_pixel", "lvds_pxl", 10), 91 GATE_MM1(CLK_MM_DPI1_ENGINE, "mm_dpi1_engine", "mm_sel", 11), 92 GATE_MM1(CLK_MM_HDMI_PIXEL, "mm_hdmi_pixel", "dpi0_sel", 12), 93 GATE_MM1(CLK_MM_HDMI_PLLCK, "mm_hdmi_pllck", "hdmi_sel", 13), 94 GATE_MM1(CLK_MM_HDMI_AUDIO, "mm_hdmi_audio", "apll1", 14), 95 GATE_MM1(CLK_MM_HDMI_SPDIF, "mm_hdmi_spdif", "apll2", 15), 96 GATE_MM1(CLK_MM_LVDS_PIXEL, "mm_lvds_pixel", "lvds_pxl", 16), 97 GATE_MM1(CLK_MM_LVDS_CTS, "mm_lvds_cts", "lvds_cts", 17), 98 GATE_MM1(CLK_MM_SMI_LARB4, "mm_smi_larb4", "mm_sel", 18), 99 GATE_MM1(CLK_MM_HDMI_HDCP, "mm_hdmi_hdcp", "hdcp_sel", 19), 100 GATE_MM1(CLK_MM_HDMI_HDCP24M, "mm_hdmi_hdcp24m", "hdcp_24m_sel", 20), 101}; 102 103struct clk_mt8173_mm_driver_data { 104 const struct mtk_gate *gates_clk; 105 int gates_num; 106}; 107 108static const struct clk_mt8173_mm_driver_data mt8173_mmsys_driver_data = { 109 .gates_clk = mt8173_mm_clks, 110 .gates_num = ARRAY_SIZE(mt8173_mm_clks), 111}; 112 113static int clk_mt8173_mm_probe(struct platform_device *pdev) 114{ 115 struct device *dev = &pdev->dev; 116 struct device_node *node = dev->parent->of_node; 117 const struct clk_mt8173_mm_driver_data *data; 118 struct clk_onecell_data *clk_data; 119 int ret; 120 121 clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK); 122 if (!clk_data) 123 return -ENOMEM; 124 125 data = &mt8173_mmsys_driver_data; 126 127 ret = mtk_clk_register_gates(node, data->gates_clk, data->gates_num, 128 clk_data); 129 if (ret) 130 return ret; 131 132 ret = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 133 if (ret) 134 return ret; 135 136 return 0; 137} 138 139static struct platform_driver clk_mt8173_mm_drv = { 140 .driver = { 141 .name = "clk-mt8173-mm", 142 }, 143 .probe = clk_mt8173_mm_probe, 144}; 145 146builtin_platform_driver(clk_mt8173_mm_drv); 147