1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (c) 2020 MediaTek Inc. 4 * Copyright (c) 2020 BayLibre, SAS 5 * Author: James Liao <jamesjj.liao@mediatek.com> 6 * Fabien Parent <fparent@baylibre.com> 7 */ 8 9#include <linux/delay.h> 10#include <linux/of.h> 11#include <linux/of_address.h> 12#include <linux/slab.h> 13#include <linux/mfd/syscon.h> 14 15#include "clk-mtk.h" 16#include "clk-gate.h" 17 18#include <dt-bindings/clock/mt8167-clk.h> 19 20static DEFINE_SPINLOCK(mt8167_clk_lock); 21 22static const struct mtk_fixed_clk fixed_clks[] __initconst = { 23 FIXED_CLK(CLK_TOP_CLK_NULL, "clk_null", NULL, 0), 24 FIXED_CLK(CLK_TOP_I2S_INFRA_BCK, "i2s_infra_bck", "clk_null", 26000000), 25 FIXED_CLK(CLK_TOP_MEMPLL, "mempll", "clk26m", 800000000), 26 FIXED_CLK(CLK_TOP_DSI0_LNTC_DSICK, "dsi0_lntc_dsick", "clk26m", 75000000), 27 FIXED_CLK(CLK_TOP_VPLL_DPIX, "vpll_dpix", "clk26m", 75000000), 28 FIXED_CLK(CLK_TOP_LVDSTX_CLKDIG_CTS, "lvdstx_dig_cts", "clk26m", 52500000), 29}; 30 31static const struct mtk_fixed_factor top_divs[] __initconst = { 32 FACTOR(CLK_TOP_DMPLL, "dmpll_ck", "mempll", 1, 1), 33 FACTOR(CLK_TOP_MAINPLL_D2, "mainpll_d2", "mainpll", 1, 2), 34 FACTOR(CLK_TOP_MAINPLL_D4, "mainpll_d4", "mainpll", 1, 4), 35 FACTOR(CLK_TOP_MAINPLL_D8, "mainpll_d8", "mainpll", 1, 8), 36 FACTOR(CLK_TOP_MAINPLL_D16, "mainpll_d16", "mainpll", 1, 16), 37 FACTOR(CLK_TOP_MAINPLL_D11, "mainpll_d11", "mainpll", 1, 11), 38 FACTOR(CLK_TOP_MAINPLL_D22, "mainpll_d22", "mainpll", 1, 22), 39 FACTOR(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3), 40 FACTOR(CLK_TOP_MAINPLL_D6, "mainpll_d6", "mainpll", 1, 6), 41 FACTOR(CLK_TOP_MAINPLL_D12, "mainpll_d12", "mainpll", 1, 12), 42 FACTOR(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1, 5), 43 FACTOR(CLK_TOP_MAINPLL_D10, "mainpll_d10", "mainpll", 1, 10), 44 FACTOR(CLK_TOP_MAINPLL_D20, "mainpll_d20", "mainpll", 1, 20), 45 FACTOR(CLK_TOP_MAINPLL_D40, "mainpll_d40", "mainpll", 1, 40), 46 FACTOR(CLK_TOP_MAINPLL_D7, "mainpll_d7", "mainpll", 1, 7), 47 FACTOR(CLK_TOP_MAINPLL_D14, "mainpll_d14", "mainpll", 1, 14), 48 FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2), 49 FACTOR(CLK_TOP_UNIVPLL_D4, "univpll_d4", "univpll", 1, 4), 50 FACTOR(CLK_TOP_UNIVPLL_D8, "univpll_d8", "univpll", 1, 8), 51 FACTOR(CLK_TOP_UNIVPLL_D16, "univpll_d16", "univpll", 1, 16), 52 FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3), 53 FACTOR(CLK_TOP_UNIVPLL_D6, "univpll_d6", "univpll", 1, 6), 54 FACTOR(CLK_TOP_UNIVPLL_D12, "univpll_d12", "univpll", 1, 12), 55 FACTOR(CLK_TOP_UNIVPLL_D24, "univpll_d24", "univpll", 1, 24), 56 FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5), 57 FACTOR(CLK_TOP_UNIVPLL_D20, "univpll_d20", "univpll", 1, 20), 58 FACTOR(CLK_TOP_MMPLL380M, "mmpll380m", "mmpll", 1, 1), 59 FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2), 60 FACTOR(CLK_TOP_MMPLL_200M, "mmpll_200m", "mmpll", 1, 3), 61 FACTOR(CLK_TOP_LVDSPLL, "lvdspll_ck", "lvdspll", 1, 1), 62 FACTOR(CLK_TOP_LVDSPLL_D2, "lvdspll_d2", "lvdspll", 1, 2), 63 FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", "lvdspll", 1, 4), 64 FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", "lvdspll", 1, 8), 65 FACTOR(CLK_TOP_USB_PHY48M, "usb_phy48m_ck", "univpll", 1, 26), 66 FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, 1), 67 FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1_ck", 1, 2), 68 FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "rg_apll1_d2_en", 1, 2), 69 FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "rg_apll1_d4_en", 1, 2), 70 FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1, 1), 71 FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2_ck", 1, 2), 72 FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "rg_apll2_d2_en", 1, 2), 73 FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "rg_apll2_d4_en", 1, 2), 74 FACTOR(CLK_TOP_CLK26M, "clk26m_ck", "clk26m", 1, 1), 75 FACTOR(CLK_TOP_CLK26M_D2, "clk26m_d2", "clk26m", 1, 2), 76 FACTOR(CLK_TOP_MIPI_26M, "mipi_26m", "clk26m", 1, 1), 77 FACTOR(CLK_TOP_TVDPLL, "tvdpll_ck", "tvdpll", 1, 1), 78 FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1, 2), 79 FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll_ck", 1, 4), 80 FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll_ck", 1, 8), 81 FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll_ck", 1, 16), 82 FACTOR(CLK_TOP_AHB_INFRA_D2, "ahb_infra_d2", "ahb_infra_sel", 1, 2), 83 FACTOR(CLK_TOP_NFI1X, "nfi1x_ck", "nfi2x_pad_sel", 1, 2), 84 FACTOR(CLK_TOP_ETH_D2, "eth_d2_ck", "eth_sel", 1, 2), 85}; 86 87static const char * const uart0_parents[] __initconst = { 88 "clk26m_ck", 89 "univpll_d24" 90}; 91 92static const char * const gfmux_emi1x_parents[] __initconst = { 93 "clk26m_ck", 94 "dmpll_ck" 95}; 96 97static const char * const emi_ddrphy_parents[] __initconst = { 98 "gfmux_emi1x_sel", 99 "gfmux_emi1x_sel" 100}; 101 102static const char * const ahb_infra_parents[] __initconst = { 103 "clk_null", 104 "clk26m_ck", 105 "mainpll_d11", 106 "clk_null", 107 "mainpll_d12", 108 "clk_null", 109 "clk_null", 110 "clk_null", 111 "clk_null", 112 "clk_null", 113 "clk_null", 114 "clk_null", 115 "mainpll_d10" 116}; 117 118static const char * const csw_mux_mfg_parents[] __initconst = { 119 "clk_null", 120 "clk_null", 121 "univpll_d3", 122 "univpll_d2", 123 "clk26m_ck", 124 "mainpll_d4", 125 "univpll_d24", 126 "mmpll380m" 127}; 128 129static const char * const msdc0_parents[] __initconst = { 130 "clk26m_ck", 131 "univpll_d6", 132 "mainpll_d8", 133 "univpll_d8", 134 "mainpll_d16", 135 "mmpll_200m", 136 "mainpll_d12", 137 "mmpll_d2" 138}; 139 140static const char * const camtg_mm_parents[] __initconst = { 141 "clk_null", 142 "clk26m_ck", 143 "usb_phy48m_ck", 144 "clk_null", 145 "univpll_d6" 146}; 147 148static const char * const pwm_mm_parents[] __initconst = { 149 "clk26m_ck", 150 "univpll_d12" 151}; 152 153static const char * const uart1_parents[] __initconst = { 154 "clk26m_ck", 155 "univpll_d24" 156}; 157 158static const char * const msdc1_parents[] __initconst = { 159 "clk26m_ck", 160 "univpll_d6", 161 "mainpll_d8", 162 "univpll_d8", 163 "mainpll_d16", 164 "mmpll_200m", 165 "mainpll_d12", 166 "mmpll_d2" 167}; 168 169static const char * const spm_52m_parents[] __initconst = { 170 "clk26m_ck", 171 "univpll_d24" 172}; 173 174static const char * const pmicspi_parents[] __initconst = { 175 "univpll_d20", 176 "usb_phy48m_ck", 177 "univpll_d16", 178 "clk26m_ck" 179}; 180 181static const char * const qaxi_aud26m_parents[] __initconst = { 182 "clk26m_ck", 183 "ahb_infra_sel" 184}; 185 186static const char * const aud_intbus_parents[] __initconst = { 187 "clk_null", 188 "clk26m_ck", 189 "mainpll_d22", 190 "clk_null", 191 "mainpll_d11" 192}; 193 194static const char * const nfi2x_pad_parents[] __initconst = { 195 "clk_null", 196 "clk_null", 197 "clk_null", 198 "clk_null", 199 "clk_null", 200 "clk_null", 201 "clk_null", 202 "clk_null", 203 "clk26m_ck", 204 "clk_null", 205 "clk_null", 206 "clk_null", 207 "clk_null", 208 "clk_null", 209 "clk_null", 210 "clk_null", 211 "clk_null", 212 "mainpll_d12", 213 "mainpll_d8", 214 "clk_null", 215 "mainpll_d6", 216 "clk_null", 217 "clk_null", 218 "clk_null", 219 "clk_null", 220 "clk_null", 221 "clk_null", 222 "clk_null", 223 "clk_null", 224 "clk_null", 225 "clk_null", 226 "clk_null", 227 "mainpll_d4", 228 "clk_null", 229 "clk_null", 230 "clk_null", 231 "clk_null", 232 "clk_null", 233 "clk_null", 234 "clk_null", 235 "clk_null", 236 "clk_null", 237 "clk_null", 238 "clk_null", 239 "clk_null", 240 "clk_null", 241 "clk_null", 242 "clk_null", 243 "clk_null", 244 "clk_null", 245 "clk_null", 246 "clk_null", 247 "clk_null", 248 "clk_null", 249 "clk_null", 250 "clk_null", 251 "clk_null", 252 "clk_null", 253 "clk_null", 254 "clk_null", 255 "clk_null", 256 "clk_null", 257 "clk_null", 258 "clk_null", 259 "clk_null", 260 "clk_null", 261 "clk_null", 262 "clk_null", 263 "clk_null", 264 "clk_null", 265 "clk_null", 266 "clk_null", 267 "clk_null", 268 "clk_null", 269 "clk_null", 270 "clk_null", 271 "clk_null", 272 "clk_null", 273 "clk_null", 274 "clk_null", 275 "clk_null", 276 "mainpll_d10", 277 "mainpll_d7", 278 "clk_null", 279 "mainpll_d5" 280}; 281 282static const char * const nfi1x_pad_parents[] __initconst = { 283 "ahb_infra_sel", 284 "nfi1x_ck" 285}; 286 287static const char * const mfg_mm_parents[] __initconst = { 288 "clk_null", 289 "clk_null", 290 "clk_null", 291 "clk_null", 292 "clk_null", 293 "clk_null", 294 "clk_null", 295 "clk_null", 296 "csw_mux_mfg_sel", 297 "clk_null", 298 "clk_null", 299 "clk_null", 300 "clk_null", 301 "clk_null", 302 "clk_null", 303 "clk_null", 304 "mainpll_d3", 305 "clk_null", 306 "clk_null", 307 "clk_null", 308 "clk_null", 309 "clk_null", 310 "clk_null", 311 "clk_null", 312 "clk_null", 313 "clk_null", 314 "clk_null", 315 "clk_null", 316 "clk_null", 317 "clk_null", 318 "clk_null", 319 "clk_null", 320 "clk_null", 321 "mainpll_d5", 322 "mainpll_d7", 323 "clk_null", 324 "mainpll_d14" 325}; 326 327static const char * const ddrphycfg_parents[] __initconst = { 328 "clk26m_ck", 329 "mainpll_d16" 330}; 331 332static const char * const smi_mm_parents[] __initconst = { 333 "clk26m_ck", 334 "clk_null", 335 "clk_null", 336 "clk_null", 337 "clk_null", 338 "clk_null", 339 "clk_null", 340 "clk_null", 341 "clk_null", 342 "univpll_d4", 343 "mainpll_d7", 344 "clk_null", 345 "mainpll_d14" 346}; 347 348static const char * const usb_78m_parents[] __initconst = { 349 "clk_null", 350 "clk26m_ck", 351 "univpll_d16", 352 "clk_null", 353 "mainpll_d20" 354}; 355 356static const char * const scam_mm_parents[] __initconst = { 357 "clk_null", 358 "clk26m_ck", 359 "mainpll_d14", 360 "clk_null", 361 "mainpll_d12" 362}; 363 364static const char * const spinor_parents[] __initconst = { 365 "clk26m_d2", 366 "clk26m_ck", 367 "mainpll_d40", 368 "univpll_d24", 369 "univpll_d20", 370 "mainpll_d20", 371 "mainpll_d16", 372 "univpll_d12" 373}; 374 375static const char * const msdc2_parents[] __initconst = { 376 "clk26m_ck", 377 "univpll_d6", 378 "mainpll_d8", 379 "univpll_d8", 380 "mainpll_d16", 381 "mmpll_200m", 382 "mainpll_d12", 383 "mmpll_d2" 384}; 385 386static const char * const eth_parents[] __initconst = { 387 "clk26m_ck", 388 "mainpll_d40", 389 "univpll_d24", 390 "univpll_d20", 391 "mainpll_d20" 392}; 393 394static const char * const vdec_mm_parents[] __initconst = { 395 "clk26m_ck", 396 "univpll_d4", 397 "mainpll_d4", 398 "univpll_d5", 399 "univpll_d6", 400 "mainpll_d6" 401}; 402 403static const char * const dpi0_mm_parents[] __initconst = { 404 "clk26m_ck", 405 "lvdspll_ck", 406 "lvdspll_d2", 407 "lvdspll_d4", 408 "lvdspll_d8" 409}; 410 411static const char * const dpi1_mm_parents[] __initconst = { 412 "clk26m_ck", 413 "tvdpll_d2", 414 "tvdpll_d4", 415 "tvdpll_d8", 416 "tvdpll_d16" 417}; 418 419static const char * const axi_mfg_in_parents[] __initconst = { 420 "clk26m_ck", 421 "mainpll_d11", 422 "univpll_d24", 423 "mmpll380m" 424}; 425 426static const char * const slow_mfg_parents[] __initconst = { 427 "clk26m_ck", 428 "univpll_d12", 429 "univpll_d24" 430}; 431 432static const char * const aud1_parents[] __initconst = { 433 "clk26m_ck", 434 "apll1_ck" 435}; 436 437static const char * const aud2_parents[] __initconst = { 438 "clk26m_ck", 439 "apll2_ck" 440}; 441 442static const char * const aud_engen1_parents[] __initconst = { 443 "clk26m_ck", 444 "rg_apll1_d2_en", 445 "rg_apll1_d4_en", 446 "rg_apll1_d8_en" 447}; 448 449static const char * const aud_engen2_parents[] __initconst = { 450 "clk26m_ck", 451 "rg_apll2_d2_en", 452 "rg_apll2_d4_en", 453 "rg_apll2_d8_en" 454}; 455 456static const char * const i2c_parents[] __initconst = { 457 "clk26m_ck", 458 "univpll_d20", 459 "univpll_d16", 460 "univpll_d12" 461}; 462 463static const char * const aud_i2s0_m_parents[] __initconst = { 464 "rg_aud1", 465 "rg_aud2" 466}; 467 468static const char * const pwm_parents[] __initconst = { 469 "clk26m_ck", 470 "univpll_d12" 471}; 472 473static const char * const spi_parents[] __initconst = { 474 "clk26m_ck", 475 "univpll_d12", 476 "univpll_d8", 477 "univpll_d6" 478}; 479 480static const char * const aud_spdifin_parents[] __initconst = { 481 "clk26m_ck", 482 "univpll_d2" 483}; 484 485static const char * const uart2_parents[] __initconst = { 486 "clk26m_ck", 487 "univpll_d24" 488}; 489 490static const char * const bsi_parents[] __initconst = { 491 "clk26m_ck", 492 "mainpll_d10", 493 "mainpll_d12", 494 "mainpll_d20" 495}; 496 497static const char * const dbg_atclk_parents[] __initconst = { 498 "clk_null", 499 "clk26m_ck", 500 "mainpll_d5", 501 "clk_null", 502 "univpll_d5" 503}; 504 505static const char * const csw_nfiecc_parents[] __initconst = { 506 "clk_null", 507 "mainpll_d7", 508 "mainpll_d6", 509 "clk_null", 510 "mainpll_d5" 511}; 512 513static const char * const nfiecc_parents[] __initconst = { 514 "clk_null", 515 "nfi2x_pad_sel", 516 "mainpll_d4", 517 "clk_null", 518 "csw_nfiecc_sel" 519}; 520 521static struct mtk_composite top_muxes[] __initdata = { 522 /* CLK_MUX_SEL0 */ 523 MUX(CLK_TOP_UART0_SEL, "uart0_sel", uart0_parents, 524 0x000, 0, 1), 525 MUX(CLK_TOP_GFMUX_EMI1X_SEL, "gfmux_emi1x_sel", gfmux_emi1x_parents, 526 0x000, 1, 1), 527 MUX(CLK_TOP_EMI_DDRPHY_SEL, "emi_ddrphy_sel", emi_ddrphy_parents, 528 0x000, 2, 1), 529 MUX(CLK_TOP_AHB_INFRA_SEL, "ahb_infra_sel", ahb_infra_parents, 530 0x000, 4, 4), 531 MUX(CLK_TOP_CSW_MUX_MFG_SEL, "csw_mux_mfg_sel", csw_mux_mfg_parents, 532 0x000, 8, 3), 533 MUX(CLK_TOP_MSDC0_SEL, "msdc0_sel", msdc0_parents, 534 0x000, 11, 3), 535 MUX(CLK_TOP_CAMTG_MM_SEL, "camtg_mm_sel", camtg_mm_parents, 536 0x000, 15, 3), 537 MUX(CLK_TOP_PWM_MM_SEL, "pwm_mm_sel", pwm_mm_parents, 538 0x000, 18, 1), 539 MUX(CLK_TOP_UART1_SEL, "uart1_sel", uart1_parents, 540 0x000, 19, 1), 541 MUX(CLK_TOP_MSDC1_SEL, "msdc1_sel", msdc1_parents, 542 0x000, 20, 3), 543 MUX(CLK_TOP_SPM_52M_SEL, "spm_52m_sel", spm_52m_parents, 544 0x000, 23, 1), 545 MUX(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents, 546 0x000, 24, 2), 547 MUX(CLK_TOP_QAXI_AUD26M_SEL, "qaxi_aud26m_sel", qaxi_aud26m_parents, 548 0x000, 26, 1), 549 MUX(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents, 550 0x000, 27, 3), 551 /* CLK_MUX_SEL1 */ 552 MUX(CLK_TOP_NFI2X_PAD_SEL, "nfi2x_pad_sel", nfi2x_pad_parents, 553 0x004, 0, 7), 554 MUX(CLK_TOP_NFI1X_PAD_SEL, "nfi1x_pad_sel", nfi1x_pad_parents, 555 0x004, 7, 1), 556 MUX(CLK_TOP_MFG_MM_SEL, "mfg_mm_sel", mfg_mm_parents, 557 0x004, 8, 6), 558 MUX(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents, 559 0x004, 15, 1), 560 MUX(CLK_TOP_SMI_MM_SEL, "smi_mm_sel", smi_mm_parents, 561 0x004, 16, 4), 562 MUX(CLK_TOP_USB_78M_SEL, "usb_78m_sel", usb_78m_parents, 563 0x004, 20, 3), 564 MUX(CLK_TOP_SCAM_MM_SEL, "scam_mm_sel", scam_mm_parents, 565 0x004, 23, 3), 566 /* CLK_MUX_SEL8 */ 567 MUX(CLK_TOP_SPINOR_SEL, "spinor_sel", spinor_parents, 568 0x040, 0, 3), 569 MUX(CLK_TOP_MSDC2_SEL, "msdc2_sel", msdc2_parents, 570 0x040, 3, 3), 571 MUX(CLK_TOP_ETH_SEL, "eth_sel", eth_parents, 572 0x040, 6, 3), 573 MUX(CLK_TOP_VDEC_MM_SEL, "vdec_mm_sel", vdec_mm_parents, 574 0x040, 9, 3), 575 MUX(CLK_TOP_DPI0_MM_SEL, "dpi0_mm_sel", dpi0_mm_parents, 576 0x040, 12, 3), 577 MUX(CLK_TOP_DPI1_MM_SEL, "dpi1_mm_sel", dpi1_mm_parents, 578 0x040, 15, 3), 579 MUX(CLK_TOP_AXI_MFG_IN_SEL, "axi_mfg_in_sel", axi_mfg_in_parents, 580 0x040, 18, 2), 581 MUX(CLK_TOP_SLOW_MFG_SEL, "slow_mfg_sel", slow_mfg_parents, 582 0x040, 20, 2), 583 MUX(CLK_TOP_AUD1_SEL, "aud1_sel", aud1_parents, 584 0x040, 22, 1), 585 MUX(CLK_TOP_AUD2_SEL, "aud2_sel", aud2_parents, 586 0x040, 23, 1), 587 MUX(CLK_TOP_AUD_ENGEN1_SEL, "aud_engen1_sel", aud_engen1_parents, 588 0x040, 24, 2), 589 MUX(CLK_TOP_AUD_ENGEN2_SEL, "aud_engen2_sel", aud_engen2_parents, 590 0x040, 26, 2), 591 MUX(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 592 0x040, 28, 2), 593 /* CLK_SEL_9 */ 594 MUX(CLK_TOP_AUD_I2S0_M_SEL, "aud_i2s0_m_sel", aud_i2s0_m_parents, 595 0x044, 12, 1), 596 MUX(CLK_TOP_AUD_I2S1_M_SEL, "aud_i2s1_m_sel", aud_i2s0_m_parents, 597 0x044, 13, 1), 598 MUX(CLK_TOP_AUD_I2S2_M_SEL, "aud_i2s2_m_sel", aud_i2s0_m_parents, 599 0x044, 14, 1), 600 MUX(CLK_TOP_AUD_I2S3_M_SEL, "aud_i2s3_m_sel", aud_i2s0_m_parents, 601 0x044, 15, 1), 602 MUX(CLK_TOP_AUD_I2S4_M_SEL, "aud_i2s4_m_sel", aud_i2s0_m_parents, 603 0x044, 16, 1), 604 MUX(CLK_TOP_AUD_I2S5_M_SEL, "aud_i2s5_m_sel", aud_i2s0_m_parents, 605 0x044, 17, 1), 606 MUX(CLK_TOP_AUD_SPDIF_B_SEL, "aud_spdif_b_sel", aud_i2s0_m_parents, 607 0x044, 18, 1), 608 /* CLK_MUX_SEL13 */ 609 MUX(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 610 0x07c, 0, 1), 611 MUX(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 612 0x07c, 1, 2), 613 MUX(CLK_TOP_AUD_SPDIFIN_SEL, "aud_spdifin_sel", aud_spdifin_parents, 614 0x07c, 3, 1), 615 MUX(CLK_TOP_UART2_SEL, "uart2_sel", uart2_parents, 616 0x07c, 4, 1), 617 MUX(CLK_TOP_BSI_SEL, "bsi_sel", bsi_parents, 618 0x07c, 5, 2), 619 MUX(CLK_TOP_DBG_ATCLK_SEL, "dbg_atclk_sel", dbg_atclk_parents, 620 0x07c, 7, 3), 621 MUX(CLK_TOP_CSW_NFIECC_SEL, "csw_nfiecc_sel", csw_nfiecc_parents, 622 0x07c, 10, 3), 623 MUX(CLK_TOP_NFIECC_SEL, "nfiecc_sel", nfiecc_parents, 624 0x07c, 13, 3), 625}; 626 627static const char * const ifr_mux1_parents[] __initconst = { 628 "clk26m_ck", 629 "armpll", 630 "univpll", 631 "mainpll_d2" 632}; 633 634static const char * const ifr_eth_25m_parents[] __initconst = { 635 "eth_d2_ck", 636 "rg_eth" 637}; 638 639static const char * const ifr_i2c0_parents[] __initconst = { 640 "ahb_infra_d2", 641 "rg_i2c" 642}; 643 644static const struct mtk_composite ifr_muxes[] __initconst = { 645 MUX(CLK_IFR_MUX1_SEL, "ifr_mux1_sel", ifr_mux1_parents, 0x000, 646 2, 2), 647 MUX(CLK_IFR_ETH_25M_SEL, "ifr_eth_25m_sel", ifr_eth_25m_parents, 0x080, 648 0, 1), 649 MUX(CLK_IFR_I2C0_SEL, "ifr_i2c0_sel", ifr_i2c0_parents, 0x080, 650 1, 1), 651 MUX(CLK_IFR_I2C1_SEL, "ifr_i2c1_sel", ifr_i2c0_parents, 0x080, 652 2, 1), 653 MUX(CLK_IFR_I2C2_SEL, "ifr_i2c2_sel", ifr_i2c0_parents, 0x080, 654 3, 1), 655}; 656 657#define DIV_ADJ(_id, _name, _parent, _reg, _shift, _width) { \ 658 .id = _id, \ 659 .name = _name, \ 660 .parent_name = _parent, \ 661 .div_reg = _reg, \ 662 .div_shift = _shift, \ 663 .div_width = _width, \ 664} 665 666static const struct mtk_clk_divider top_adj_divs[] = { 667 DIV_ADJ(CLK_TOP_APLL12_CK_DIV0, "apll12_ck_div0", "aud_i2s0_m_sel", 668 0x0048, 0, 8), 669 DIV_ADJ(CLK_TOP_APLL12_CK_DIV1, "apll12_ck_div1", "aud_i2s1_m_sel", 670 0x0048, 8, 8), 671 DIV_ADJ(CLK_TOP_APLL12_CK_DIV2, "apll12_ck_div2", "aud_i2s2_m_sel", 672 0x0048, 16, 8), 673 DIV_ADJ(CLK_TOP_APLL12_CK_DIV3, "apll12_ck_div3", "aud_i2s3_m_sel", 674 0x0048, 24, 8), 675 DIV_ADJ(CLK_TOP_APLL12_CK_DIV4, "apll12_ck_div4", "aud_i2s4_m_sel", 676 0x004c, 0, 8), 677 DIV_ADJ(CLK_TOP_APLL12_CK_DIV4B, "apll12_ck_div4b", "apll12_div4", 678 0x004c, 8, 8), 679 DIV_ADJ(CLK_TOP_APLL12_CK_DIV5, "apll12_ck_div5", "aud_i2s5_m_sel", 680 0x004c, 16, 8), 681 DIV_ADJ(CLK_TOP_APLL12_CK_DIV5B, "apll12_ck_div5b", "apll12_div5", 682 0x004c, 24, 8), 683 DIV_ADJ(CLK_TOP_APLL12_CK_DIV6, "apll12_ck_div6", "aud_spdif_b_sel", 684 0x0078, 0, 8), 685}; 686 687#define DIV_ADJ_FLAG(_id, _name, _parent, _reg, _shift, _width, _flag) { \ 688 .id = _id, \ 689 .name = _name, \ 690 .parent_name = _parent, \ 691 .div_reg = _reg, \ 692 .div_shift = _shift, \ 693 .div_width = _width, \ 694 .clk_divider_flags = _flag, \ 695} 696 697static const struct mtk_clk_divider apmixed_adj_divs[] = { 698 DIV_ADJ_FLAG(CLK_APMIXED_HDMI_REF, "hdmi_ref", "tvdpll", 699 0x1c4, 24, 3, CLK_DIVIDER_POWER_OF_TWO), 700}; 701 702static const struct mtk_gate_regs top0_cg_regs = { 703 .set_ofs = 0x50, 704 .clr_ofs = 0x80, 705 .sta_ofs = 0x20, 706}; 707 708static const struct mtk_gate_regs top1_cg_regs = { 709 .set_ofs = 0x54, 710 .clr_ofs = 0x84, 711 .sta_ofs = 0x24, 712}; 713 714static const struct mtk_gate_regs top2_cg_regs = { 715 .set_ofs = 0x6c, 716 .clr_ofs = 0x9c, 717 .sta_ofs = 0x3c, 718}; 719 720static const struct mtk_gate_regs top3_cg_regs = { 721 .set_ofs = 0xa0, 722 .clr_ofs = 0xb0, 723 .sta_ofs = 0x70, 724}; 725 726static const struct mtk_gate_regs top4_cg_regs = { 727 .set_ofs = 0xa4, 728 .clr_ofs = 0xb4, 729 .sta_ofs = 0x74, 730}; 731 732static const struct mtk_gate_regs top5_cg_regs = { 733 .set_ofs = 0x44, 734 .clr_ofs = 0x44, 735 .sta_ofs = 0x44, 736}; 737 738#define GATE_TOP0(_id, _name, _parent, _shift) { \ 739 .id = _id, \ 740 .name = _name, \ 741 .parent_name = _parent, \ 742 .regs = &top0_cg_regs, \ 743 .shift = _shift, \ 744 .ops = &mtk_clk_gate_ops_setclr, \ 745 } 746 747#define GATE_TOP0_I(_id, _name, _parent, _shift) { \ 748 .id = _id, \ 749 .name = _name, \ 750 .parent_name = _parent, \ 751 .regs = &top0_cg_regs, \ 752 .shift = _shift, \ 753 .ops = &mtk_clk_gate_ops_setclr_inv, \ 754 } 755 756#define GATE_TOP1(_id, _name, _parent, _shift) { \ 757 .id = _id, \ 758 .name = _name, \ 759 .parent_name = _parent, \ 760 .regs = &top1_cg_regs, \ 761 .shift = _shift, \ 762 .ops = &mtk_clk_gate_ops_setclr, \ 763 } 764 765#define GATE_TOP2(_id, _name, _parent, _shift) { \ 766 .id = _id, \ 767 .name = _name, \ 768 .parent_name = _parent, \ 769 .regs = &top2_cg_regs, \ 770 .shift = _shift, \ 771 .ops = &mtk_clk_gate_ops_setclr, \ 772 } 773 774#define GATE_TOP2_I(_id, _name, _parent, _shift) { \ 775 .id = _id, \ 776 .name = _name, \ 777 .parent_name = _parent, \ 778 .regs = &top2_cg_regs, \ 779 .shift = _shift, \ 780 .ops = &mtk_clk_gate_ops_setclr_inv, \ 781 } 782 783#define GATE_TOP3(_id, _name, _parent, _shift) { \ 784 .id = _id, \ 785 .name = _name, \ 786 .parent_name = _parent, \ 787 .regs = &top3_cg_regs, \ 788 .shift = _shift, \ 789 .ops = &mtk_clk_gate_ops_setclr, \ 790 } 791 792#define GATE_TOP4_I(_id, _name, _parent, _shift) { \ 793 .id = _id, \ 794 .name = _name, \ 795 .parent_name = _parent, \ 796 .regs = &top4_cg_regs, \ 797 .shift = _shift, \ 798 .ops = &mtk_clk_gate_ops_setclr_inv, \ 799 } 800 801#define GATE_TOP5(_id, _name, _parent, _shift) { \ 802 .id = _id, \ 803 .name = _name, \ 804 .parent_name = _parent, \ 805 .regs = &top5_cg_regs, \ 806 .shift = _shift, \ 807 .ops = &mtk_clk_gate_ops_no_setclr, \ 808 } 809 810static const struct mtk_gate top_clks[] __initconst = { 811 /* TOP0 */ 812 GATE_TOP0(CLK_TOP_PWM_MM, "pwm_mm", "pwm_mm_sel", 0), 813 GATE_TOP0(CLK_TOP_CAM_MM, "cam_mm", "camtg_mm_sel", 1), 814 GATE_TOP0(CLK_TOP_MFG_MM, "mfg_mm", "mfg_mm_sel", 2), 815 GATE_TOP0(CLK_TOP_SPM_52M, "spm_52m", "spm_52m_sel", 3), 816 GATE_TOP0_I(CLK_TOP_MIPI_26M_DBG, "mipi_26m_dbg", "mipi_26m", 4), 817 GATE_TOP0(CLK_TOP_SCAM_MM, "scam_mm", "scam_mm_sel", 5), 818 GATE_TOP0(CLK_TOP_SMI_MM, "smi_mm", "smi_mm_sel", 9), 819 /* TOP1 */ 820 GATE_TOP1(CLK_TOP_THEM, "them", "ahb_infra_sel", 1), 821 GATE_TOP1(CLK_TOP_APDMA, "apdma", "ahb_infra_sel", 2), 822 GATE_TOP1(CLK_TOP_I2C0, "i2c0", "ifr_i2c0_sel", 3), 823 GATE_TOP1(CLK_TOP_I2C1, "i2c1", "ifr_i2c1_sel", 4), 824 GATE_TOP1(CLK_TOP_AUXADC1, "auxadc1", "ahb_infra_sel", 5), 825 GATE_TOP1(CLK_TOP_NFI, "nfi", "nfi1x_pad_sel", 6), 826 GATE_TOP1(CLK_TOP_NFIECC, "nfiecc", "rg_nfiecc", 7), 827 GATE_TOP1(CLK_TOP_DEBUGSYS, "debugsys", "rg_dbg_atclk", 8), 828 GATE_TOP1(CLK_TOP_PWM, "pwm", "ahb_infra_sel", 9), 829 GATE_TOP1(CLK_TOP_UART0, "uart0", "uart0_sel", 10), 830 GATE_TOP1(CLK_TOP_UART1, "uart1", "uart1_sel", 11), 831 GATE_TOP1(CLK_TOP_BTIF, "btif", "ahb_infra_sel", 12), 832 GATE_TOP1(CLK_TOP_USB, "usb", "usb_78m", 13), 833 GATE_TOP1(CLK_TOP_FLASHIF_26M, "flashif_26m", "clk26m_ck", 14), 834 GATE_TOP1(CLK_TOP_AUXADC2, "auxadc2", "ahb_infra_sel", 15), 835 GATE_TOP1(CLK_TOP_I2C2, "i2c2", "ifr_i2c2_sel", 16), 836 GATE_TOP1(CLK_TOP_MSDC0, "msdc0", "msdc0_sel", 17), 837 GATE_TOP1(CLK_TOP_MSDC1, "msdc1", "msdc1_sel", 18), 838 GATE_TOP1(CLK_TOP_NFI2X, "nfi2x", "nfi2x_pad_sel", 19), 839 GATE_TOP1(CLK_TOP_PMICWRAP_AP, "pwrap_ap", "clk26m_ck", 20), 840 GATE_TOP1(CLK_TOP_SEJ, "sej", "ahb_infra_sel", 21), 841 GATE_TOP1(CLK_TOP_MEMSLP_DLYER, "memslp_dlyer", "clk26m_ck", 22), 842 GATE_TOP1(CLK_TOP_SPI, "spi", "spi_sel", 23), 843 GATE_TOP1(CLK_TOP_APXGPT, "apxgpt", "clk26m_ck", 24), 844 GATE_TOP1(CLK_TOP_AUDIO, "audio", "clk26m_ck", 25), 845 GATE_TOP1(CLK_TOP_PMICWRAP_MD, "pwrap_md", "clk26m_ck", 27), 846 GATE_TOP1(CLK_TOP_PMICWRAP_CONN, "pwrap_conn", "clk26m_ck", 28), 847 GATE_TOP1(CLK_TOP_PMICWRAP_26M, "pwrap_26m", "clk26m_ck", 29), 848 GATE_TOP1(CLK_TOP_AUX_ADC, "aux_adc", "clk26m_ck", 30), 849 GATE_TOP1(CLK_TOP_AUX_TP, "aux_tp", "clk26m_ck", 31), 850 /* TOP2 */ 851 GATE_TOP2(CLK_TOP_MSDC2, "msdc2", "ahb_infra_sel", 0), 852 GATE_TOP2(CLK_TOP_RBIST, "rbist", "univpll_d12", 1), 853 GATE_TOP2(CLK_TOP_NFI_BUS, "nfi_bus", "ahb_infra_sel", 2), 854 GATE_TOP2(CLK_TOP_GCE, "gce", "ahb_infra_sel", 4), 855 GATE_TOP2(CLK_TOP_TRNG, "trng", "ahb_infra_sel", 5), 856 GATE_TOP2(CLK_TOP_SEJ_13M, "sej_13m", "clk26m_ck", 6), 857 GATE_TOP2(CLK_TOP_AES, "aes", "ahb_infra_sel", 7), 858 GATE_TOP2(CLK_TOP_PWM_B, "pwm_b", "rg_pwm_infra", 8), 859 GATE_TOP2(CLK_TOP_PWM1_FB, "pwm1_fb", "rg_pwm_infra", 9), 860 GATE_TOP2(CLK_TOP_PWM2_FB, "pwm2_fb", "rg_pwm_infra", 10), 861 GATE_TOP2(CLK_TOP_PWM3_FB, "pwm3_fb", "rg_pwm_infra", 11), 862 GATE_TOP2(CLK_TOP_PWM4_FB, "pwm4_fb", "rg_pwm_infra", 12), 863 GATE_TOP2(CLK_TOP_PWM5_FB, "pwm5_fb", "rg_pwm_infra", 13), 864 GATE_TOP2(CLK_TOP_USB_1P, "usb_1p", "usb_78m", 14), 865 GATE_TOP2(CLK_TOP_FLASHIF_FREERUN, "flashif_freerun", "ahb_infra_sel", 866 15), 867 GATE_TOP2(CLK_TOP_26M_HDMI_SIFM, "hdmi_sifm_26m", "clk26m_ck", 16), 868 GATE_TOP2(CLK_TOP_26M_CEC, "cec_26m", "clk26m_ck", 17), 869 GATE_TOP2(CLK_TOP_32K_CEC, "cec_32k", "clk32k", 18), 870 GATE_TOP2(CLK_TOP_66M_ETH, "eth_66m", "ahb_infra_d2", 19), 871 GATE_TOP2(CLK_TOP_133M_ETH, "eth_133m", "ahb_infra_sel", 20), 872 GATE_TOP2(CLK_TOP_FETH_25M, "feth_25m", "ifr_eth_25m_sel", 21), 873 GATE_TOP2(CLK_TOP_FETH_50M, "feth_50m", "rg_eth", 22), 874 GATE_TOP2(CLK_TOP_FLASHIF_AXI, "flashif_axi", "ahb_infra_sel", 23), 875 GATE_TOP2(CLK_TOP_USBIF, "usbif", "ahb_infra_sel", 24), 876 GATE_TOP2(CLK_TOP_UART2, "uart2", "rg_uart2", 25), 877 GATE_TOP2(CLK_TOP_BSI, "bsi", "ahb_infra_sel", 26), 878 GATE_TOP2(CLK_TOP_GCPU_B, "gcpu_b", "ahb_infra_sel", 27), 879 GATE_TOP2_I(CLK_TOP_MSDC0_INFRA, "msdc0_infra", "msdc0", 28), 880 GATE_TOP2_I(CLK_TOP_MSDC1_INFRA, "msdc1_infra", "msdc1", 29), 881 GATE_TOP2_I(CLK_TOP_MSDC2_INFRA, "msdc2_infra", "rg_msdc2", 30), 882 GATE_TOP2(CLK_TOP_USB_78M, "usb_78m", "usb_78m_sel", 31), 883 /* TOP3 */ 884 GATE_TOP3(CLK_TOP_RG_SPINOR, "rg_spinor", "spinor_sel", 0), 885 GATE_TOP3(CLK_TOP_RG_MSDC2, "rg_msdc2", "msdc2_sel", 1), 886 GATE_TOP3(CLK_TOP_RG_ETH, "rg_eth", "eth_sel", 2), 887 GATE_TOP3(CLK_TOP_RG_VDEC, "rg_vdec", "vdec_mm_sel", 3), 888 GATE_TOP3(CLK_TOP_RG_FDPI0, "rg_fdpi0", "dpi0_mm_sel", 4), 889 GATE_TOP3(CLK_TOP_RG_FDPI1, "rg_fdpi1", "dpi1_mm_sel", 5), 890 GATE_TOP3(CLK_TOP_RG_AXI_MFG, "rg_axi_mfg", "axi_mfg_in_sel", 6), 891 GATE_TOP3(CLK_TOP_RG_SLOW_MFG, "rg_slow_mfg", "slow_mfg_sel", 7), 892 GATE_TOP3(CLK_TOP_RG_AUD1, "rg_aud1", "aud1_sel", 8), 893 GATE_TOP3(CLK_TOP_RG_AUD2, "rg_aud2", "aud2_sel", 9), 894 GATE_TOP3(CLK_TOP_RG_AUD_ENGEN1, "rg_aud_engen1", "aud_engen1_sel", 10), 895 GATE_TOP3(CLK_TOP_RG_AUD_ENGEN2, "rg_aud_engen2", "aud_engen2_sel", 11), 896 GATE_TOP3(CLK_TOP_RG_I2C, "rg_i2c", "i2c_sel", 12), 897 GATE_TOP3(CLK_TOP_RG_PWM_INFRA, "rg_pwm_infra", "pwm_sel", 13), 898 GATE_TOP3(CLK_TOP_RG_AUD_SPDIF_IN, "rg_aud_spdif_in", "aud_spdifin_sel", 899 14), 900 GATE_TOP3(CLK_TOP_RG_UART2, "rg_uart2", "uart2_sel", 15), 901 GATE_TOP3(CLK_TOP_RG_BSI, "rg_bsi", "bsi_sel", 16), 902 GATE_TOP3(CLK_TOP_RG_DBG_ATCLK, "rg_dbg_atclk", "dbg_atclk_sel", 17), 903 GATE_TOP3(CLK_TOP_RG_NFIECC, "rg_nfiecc", "nfiecc_sel", 18), 904 /* TOP4 */ 905 GATE_TOP4_I(CLK_TOP_RG_APLL1_D2_EN, "rg_apll1_d2_en", "apll1_d2", 8), 906 GATE_TOP4_I(CLK_TOP_RG_APLL1_D4_EN, "rg_apll1_d4_en", "apll1_d4", 9), 907 GATE_TOP4_I(CLK_TOP_RG_APLL1_D8_EN, "rg_apll1_d8_en", "apll1_d8", 10), 908 GATE_TOP4_I(CLK_TOP_RG_APLL2_D2_EN, "rg_apll2_d2_en", "apll2_d2", 11), 909 GATE_TOP4_I(CLK_TOP_RG_APLL2_D4_EN, "rg_apll2_d4_en", "apll2_d4", 12), 910 GATE_TOP4_I(CLK_TOP_RG_APLL2_D8_EN, "rg_apll2_d8_en", "apll2_d8", 13), 911 /* TOP5 */ 912 GATE_TOP5(CLK_TOP_APLL12_DIV0, "apll12_div0", "apll12_ck_div0", 0), 913 GATE_TOP5(CLK_TOP_APLL12_DIV1, "apll12_div1", "apll12_ck_div1", 1), 914 GATE_TOP5(CLK_TOP_APLL12_DIV2, "apll12_div2", "apll12_ck_div2", 2), 915 GATE_TOP5(CLK_TOP_APLL12_DIV3, "apll12_div3", "apll12_ck_div3", 3), 916 GATE_TOP5(CLK_TOP_APLL12_DIV4, "apll12_div4", "apll12_ck_div4", 4), 917 GATE_TOP5(CLK_TOP_APLL12_DIV4B, "apll12_div4b", "apll12_ck_div4b", 5), 918 GATE_TOP5(CLK_TOP_APLL12_DIV5, "apll12_div5", "apll12_ck_div5", 6), 919 GATE_TOP5(CLK_TOP_APLL12_DIV5B, "apll12_div5b", "apll12_ck_div5b", 7), 920 GATE_TOP5(CLK_TOP_APLL12_DIV6, "apll12_div6", "apll12_ck_div6", 8), 921}; 922 923static void __init mtk_topckgen_init(struct device_node *node) 924{ 925 struct clk_onecell_data *clk_data; 926 int r; 927 void __iomem *base; 928 929 base = of_iomap(node, 0); 930 if (!base) { 931 pr_err("%s(): ioremap failed\n", __func__); 932 return; 933 } 934 935 clk_data = mtk_alloc_clk_data(MT8167_CLK_TOP_NR_CLK); 936 937 mtk_clk_register_fixed_clks(fixed_clks, ARRAY_SIZE(fixed_clks), 938 clk_data); 939 mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), clk_data); 940 941 mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); 942 mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base, 943 &mt8167_clk_lock, clk_data); 944 mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), 945 base, &mt8167_clk_lock, clk_data); 946 947 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 948 if (r) 949 pr_err("%s(): could not register clock provider: %d\n", 950 __func__, r); 951} 952CLK_OF_DECLARE(mtk_topckgen, "mediatek,mt8167-topckgen", mtk_topckgen_init); 953 954static void __init mtk_infracfg_init(struct device_node *node) 955{ 956 struct clk_onecell_data *clk_data; 957 int r; 958 void __iomem *base; 959 960 base = of_iomap(node, 0); 961 if (!base) { 962 pr_err("%s(): ioremap failed\n", __func__); 963 return; 964 } 965 966 clk_data = mtk_alloc_clk_data(CLK_IFR_NR_CLK); 967 968 mtk_clk_register_composites(ifr_muxes, ARRAY_SIZE(ifr_muxes), base, 969 &mt8167_clk_lock, clk_data); 970 971 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 972 if (r) 973 pr_err("%s(): could not register clock provider: %d\n", 974 __func__, r); 975} 976CLK_OF_DECLARE(mtk_infracfg, "mediatek,mt8167-infracfg", mtk_infracfg_init); 977 978#define MT8167_PLL_FMAX (2500UL * MHZ) 979 980#define CON0_MT8167_RST_BAR BIT(27) 981 982#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ 983 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \ 984 _pcw_shift, _div_table) { \ 985 .id = _id, \ 986 .name = _name, \ 987 .reg = _reg, \ 988 .pwr_reg = _pwr_reg, \ 989 .en_mask = _en_mask, \ 990 .flags = _flags, \ 991 .rst_bar_mask = CON0_MT8167_RST_BAR, \ 992 .fmax = MT8167_PLL_FMAX, \ 993 .pcwbits = _pcwbits, \ 994 .pd_reg = _pd_reg, \ 995 .pd_shift = _pd_shift, \ 996 .tuner_reg = _tuner_reg, \ 997 .pcw_reg = _pcw_reg, \ 998 .pcw_shift = _pcw_shift, \ 999 .div_table = _div_table, \ 1000 } 1001 1002#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ 1003 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \ 1004 _pcw_shift) \ 1005 PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ 1006 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \ 1007 NULL) 1008 1009static const struct mtk_pll_div_table mmpll_div_table[] = { 1010 { .div = 0, .freq = MT8167_PLL_FMAX }, 1011 { .div = 1, .freq = 1000000000 }, 1012 { .div = 2, .freq = 604500000 }, 1013 { .div = 3, .freq = 253500000 }, 1014 { .div = 4, .freq = 126750000 }, 1015 { } /* sentinel */ 1016}; 1017 1018static const struct mtk_pll_data plls[] = { 1019 PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0100, 0x0110, 0x00000001, 0, 1020 21, 0x0104, 24, 0, 0x0104, 0), 1021 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0120, 0x0130, 0x00000001, 1022 HAVE_RST_BAR, 21, 0x0124, 24, 0, 0x0124, 0), 1023 PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0140, 0x0150, 0x30000001, 1024 HAVE_RST_BAR, 7, 0x0144, 24, 0, 0x0144, 0), 1025 PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0160, 0x0170, 0x00000001, 0, 1026 21, 0x0164, 24, 0, 0x0164, 0, mmpll_div_table), 1027 PLL(CLK_APMIXED_APLL1, "apll1", 0x0180, 0x0190, 0x00000001, 0, 1028 31, 0x0180, 1, 0x0194, 0x0184, 0), 1029 PLL(CLK_APMIXED_APLL2, "apll2", 0x01A0, 0x01B0, 0x00000001, 0, 1030 31, 0x01A0, 1, 0x01B4, 0x01A4, 0), 1031 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x01C0, 0x01D0, 0x00000001, 0, 1032 21, 0x01C4, 24, 0, 0x01C4, 0), 1033 PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x01E0, 0x01F0, 0x00000001, 0, 1034 21, 0x01E4, 24, 0, 0x01E4, 0), 1035}; 1036 1037static void __init mtk_apmixedsys_init(struct device_node *node) 1038{ 1039 struct clk_onecell_data *clk_data; 1040 void __iomem *base; 1041 int r; 1042 1043 base = of_iomap(node, 0); 1044 if (!base) { 1045 pr_err("%s(): ioremap failed\n", __func__); 1046 return; 1047 } 1048 1049 clk_data = mtk_alloc_clk_data(MT8167_CLK_APMIXED_NR_CLK); 1050 1051 mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); 1052 mtk_clk_register_dividers(apmixed_adj_divs, ARRAY_SIZE(apmixed_adj_divs), 1053 base, &mt8167_clk_lock, clk_data); 1054 1055 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 1056 if (r) 1057 pr_err("%s(): could not register clock provider: %d\n", 1058 __func__, r); 1059 1060} 1061CLK_OF_DECLARE(mtk_apmixedsys, "mediatek,mt8167-apmixedsys", 1062 mtk_apmixedsys_init); 1063