1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2020 MediaTek Inc.
4 * Copyright (c) 2020 BayLibre, SAS
5 * Author: James Liao <jamesjj.liao@mediatek.com>
6 *         Fabien Parent <fparent@baylibre.com>
7 */
8
9#include <linux/clk-provider.h>
10#include <linux/of.h>
11#include <linux/of_address.h>
12#include <linux/of_device.h>
13#include <linux/platform_device.h>
14
15#include "clk-mtk.h"
16#include "clk-gate.h"
17
18#include <dt-bindings/clock/mt8167-clk.h>
19
20static const struct mtk_gate_regs vdec0_cg_regs = {
21	.set_ofs = 0x0,
22	.clr_ofs = 0x4,
23	.sta_ofs = 0x0,
24};
25
26static const struct mtk_gate_regs vdec1_cg_regs = {
27	.set_ofs = 0x8,
28	.clr_ofs = 0xc,
29	.sta_ofs = 0x8,
30};
31
32#define GATE_VDEC0_I(_id, _name, _parent, _shift) {	\
33		.id = _id,				\
34		.name = _name,				\
35		.parent_name = _parent,			\
36		.regs = &vdec0_cg_regs,			\
37		.shift = _shift,			\
38		.ops = &mtk_clk_gate_ops_setclr_inv,	\
39	}
40
41#define GATE_VDEC1_I(_id, _name, _parent, _shift) {	\
42		.id = _id,				\
43		.name = _name,				\
44		.parent_name = _parent,			\
45		.regs = &vdec1_cg_regs,			\
46		.shift = _shift,			\
47		.ops = &mtk_clk_gate_ops_setclr_inv,	\
48	}
49
50static const struct mtk_gate vdec_clks[] __initconst = {
51	/* VDEC0 */
52	GATE_VDEC0_I(CLK_VDEC_CKEN, "vdec_cken", "rg_vdec", 0),
53	/* VDEC1 */
54	GATE_VDEC1_I(CLK_VDEC_LARB1_CKEN, "vdec_larb1_cken", "smi_mm", 0),
55};
56
57static void __init mtk_vdecsys_init(struct device_node *node)
58{
59	struct clk_onecell_data *clk_data;
60	int r;
61
62	clk_data = mtk_alloc_clk_data(CLK_VDEC_NR_CLK);
63
64	mtk_clk_register_gates(node, vdec_clks, ARRAY_SIZE(vdec_clks), clk_data);
65
66	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
67
68	if (r)
69		pr_err("%s(): could not register clock provider: %d\n",
70			__func__, r);
71
72}
73CLK_OF_DECLARE(mtk_vdecsys, "mediatek,mt8167-vdecsys", mtk_vdecsys_init);
74