1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2018 MediaTek Inc. 4 * Author: Wenzhen Yu <Wenzhen Yu@mediatek.com> 5 * Ryder Lee <ryder.lee@mediatek.com> 6 */ 7 8#include <linux/clk.h> 9#include <linux/clk-provider.h> 10#include <linux/of.h> 11#include <linux/of_address.h> 12#include <linux/of_device.h> 13#include <linux/platform_device.h> 14 15#include "clk-mtk.h" 16#include "clk-gate.h" 17#include "clk-cpumux.h" 18 19#include <dt-bindings/clock/mt7629-clk.h> 20 21#define MT7629_PLL_FMAX (2500UL * MHZ) 22#define CON0_MT7629_RST_BAR BIT(24) 23 24#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ 25 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \ 26 _pcw_shift, _div_table, _parent_name) { \ 27 .id = _id, \ 28 .name = _name, \ 29 .reg = _reg, \ 30 .pwr_reg = _pwr_reg, \ 31 .en_mask = _en_mask, \ 32 .flags = _flags, \ 33 .rst_bar_mask = CON0_MT7629_RST_BAR, \ 34 .fmax = MT7629_PLL_FMAX, \ 35 .pcwbits = _pcwbits, \ 36 .pd_reg = _pd_reg, \ 37 .pd_shift = _pd_shift, \ 38 .tuner_reg = _tuner_reg, \ 39 .pcw_reg = _pcw_reg, \ 40 .pcw_shift = _pcw_shift, \ 41 .div_table = _div_table, \ 42 .parent_name = _parent_name, \ 43 } 44 45#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ 46 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \ 47 _pcw_shift) \ 48 PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ 49 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \ 50 NULL, "clk20m") 51 52#define GATE_APMIXED(_id, _name, _parent, _shift) { \ 53 .id = _id, \ 54 .name = _name, \ 55 .parent_name = _parent, \ 56 .regs = &apmixed_cg_regs, \ 57 .shift = _shift, \ 58 .ops = &mtk_clk_gate_ops_no_setclr_inv, \ 59 } 60 61#define GATE_INFRA(_id, _name, _parent, _shift) { \ 62 .id = _id, \ 63 .name = _name, \ 64 .parent_name = _parent, \ 65 .regs = &infra_cg_regs, \ 66 .shift = _shift, \ 67 .ops = &mtk_clk_gate_ops_setclr, \ 68 } 69 70#define GATE_PERI0(_id, _name, _parent, _shift) { \ 71 .id = _id, \ 72 .name = _name, \ 73 .parent_name = _parent, \ 74 .regs = &peri0_cg_regs, \ 75 .shift = _shift, \ 76 .ops = &mtk_clk_gate_ops_setclr, \ 77 } 78 79#define GATE_PERI1(_id, _name, _parent, _shift) { \ 80 .id = _id, \ 81 .name = _name, \ 82 .parent_name = _parent, \ 83 .regs = &peri1_cg_regs, \ 84 .shift = _shift, \ 85 .ops = &mtk_clk_gate_ops_setclr, \ 86 } 87 88static DEFINE_SPINLOCK(mt7629_clk_lock); 89 90static const char * const axi_parents[] = { 91 "clkxtal", 92 "syspll1_d2", 93 "syspll_d5", 94 "syspll1_d4", 95 "univpll_d5", 96 "univpll2_d2", 97 "univpll_d7", 98 "dmpll_ck" 99}; 100 101static const char * const mem_parents[] = { 102 "clkxtal", 103 "dmpll_ck" 104}; 105 106static const char * const ddrphycfg_parents[] = { 107 "clkxtal", 108 "syspll1_d8" 109}; 110 111static const char * const eth_parents[] = { 112 "clkxtal", 113 "syspll1_d2", 114 "univpll1_d2", 115 "syspll1_d4", 116 "univpll_d5", 117 "sgmiipll_d2", 118 "univpll_d7", 119 "dmpll_ck" 120}; 121 122static const char * const pwm_parents[] = { 123 "clkxtal", 124 "univpll2_d4" 125}; 126 127static const char * const f10m_ref_parents[] = { 128 "clkxtal", 129 "sgmiipll_d2" 130}; 131 132static const char * const nfi_infra_parents[] = { 133 "clkxtal", 134 "clkxtal", 135 "clkxtal", 136 "clkxtal", 137 "clkxtal", 138 "clkxtal", 139 "univpll2_d8", 140 "univpll3_d4", 141 "syspll1_d8", 142 "univpll1_d8", 143 "syspll4_d2", 144 "syspll2_d4", 145 "univpll2_d4", 146 "univpll3_d2", 147 "syspll1_d4", 148 "syspll_d7" 149}; 150 151static const char * const flash_parents[] = { 152 "clkxtal", 153 "univpll_d80_d4", 154 "syspll2_d8", 155 "syspll3_d4", 156 "univpll3_d4", 157 "univpll1_d8", 158 "syspll2_d4", 159 "univpll2_d4" 160}; 161 162static const char * const uart_parents[] = { 163 "clkxtal", 164 "univpll2_d8" 165}; 166 167static const char * const spi0_parents[] = { 168 "clkxtal", 169 "syspll3_d2", 170 "clkxtal", 171 "syspll2_d4", 172 "syspll4_d2", 173 "univpll2_d4", 174 "univpll1_d8", 175 "clkxtal" 176}; 177 178static const char * const spi1_parents[] = { 179 "clkxtal", 180 "syspll3_d2", 181 "clkxtal", 182 "syspll4_d4", 183 "syspll4_d2", 184 "univpll2_d4", 185 "univpll1_d8", 186 "clkxtal" 187}; 188 189static const char * const msdc30_0_parents[] = { 190 "clkxtal", 191 "univpll2_d16", 192 "univ48m" 193}; 194 195static const char * const msdc30_1_parents[] = { 196 "clkxtal", 197 "univpll2_d16", 198 "univ48m", 199 "syspll2_d4", 200 "univpll2_d4", 201 "syspll_d7", 202 "syspll2_d2", 203 "univpll2_d2" 204}; 205 206static const char * const ap2wbmcu_parents[] = { 207 "clkxtal", 208 "syspll1_d2", 209 "univ48m", 210 "syspll1_d8", 211 "univpll2_d4", 212 "syspll_d7", 213 "syspll2_d2", 214 "univpll2_d2" 215}; 216 217static const char * const audio_parents[] = { 218 "clkxtal", 219 "syspll3_d4", 220 "syspll4_d4", 221 "syspll1_d16" 222}; 223 224static const char * const aud_intbus_parents[] = { 225 "clkxtal", 226 "syspll1_d4", 227 "syspll4_d2", 228 "dmpll_d4" 229}; 230 231static const char * const pmicspi_parents[] = { 232 "clkxtal", 233 "syspll1_d8", 234 "syspll3_d4", 235 "syspll1_d16", 236 "univpll3_d4", 237 "clkxtal", 238 "univpll2_d4", 239 "dmpll_d8" 240}; 241 242static const char * const scp_parents[] = { 243 "clkxtal", 244 "syspll1_d8", 245 "univpll2_d2", 246 "univpll2_d4" 247}; 248 249static const char * const atb_parents[] = { 250 "clkxtal", 251 "syspll1_d2", 252 "syspll_d5" 253}; 254 255static const char * const hif_parents[] = { 256 "clkxtal", 257 "syspll1_d2", 258 "univpll1_d2", 259 "syspll1_d4", 260 "univpll_d5", 261 "clk_null", 262 "univpll_d7" 263}; 264 265static const char * const sata_parents[] = { 266 "clkxtal", 267 "univpll2_d4" 268}; 269 270static const char * const usb20_parents[] = { 271 "clkxtal", 272 "univpll3_d4", 273 "syspll1_d8" 274}; 275 276static const char * const aud1_parents[] = { 277 "clkxtal" 278}; 279 280static const char * const irrx_parents[] = { 281 "clkxtal", 282 "syspll4_d16" 283}; 284 285static const char * const crypto_parents[] = { 286 "clkxtal", 287 "univpll_d3", 288 "univpll1_d2", 289 "syspll1_d2", 290 "univpll_d5", 291 "syspll_d5", 292 "univpll2_d2", 293 "syspll_d2" 294}; 295 296static const char * const gpt10m_parents[] = { 297 "clkxtal", 298 "clkxtal_d4" 299}; 300 301static const char * const peribus_ck_parents[] = { 302 "syspll1_d8", 303 "syspll1_d4" 304}; 305 306static const char * const infra_mux1_parents[] = { 307 "clkxtal", 308 "armpll", 309 "main_core_en", 310 "armpll" 311}; 312 313static const struct mtk_gate_regs apmixed_cg_regs = { 314 .set_ofs = 0x8, 315 .clr_ofs = 0x8, 316 .sta_ofs = 0x8, 317}; 318 319static const struct mtk_gate_regs infra_cg_regs = { 320 .set_ofs = 0x40, 321 .clr_ofs = 0x44, 322 .sta_ofs = 0x48, 323}; 324 325static const struct mtk_gate_regs peri0_cg_regs = { 326 .set_ofs = 0x8, 327 .clr_ofs = 0x10, 328 .sta_ofs = 0x18, 329}; 330 331static const struct mtk_gate_regs peri1_cg_regs = { 332 .set_ofs = 0xC, 333 .clr_ofs = 0x14, 334 .sta_ofs = 0x1C, 335}; 336 337static const struct mtk_pll_data plls[] = { 338 PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x00000001, 339 0, 21, 0x0204, 24, 0, 0x0204, 0), 340 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0210, 0x021C, 0x00000001, 341 HAVE_RST_BAR, 21, 0x0214, 24, 0, 0x0214, 0), 342 PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0220, 0x022C, 0x00000001, 343 HAVE_RST_BAR, 7, 0x0224, 24, 0, 0x0224, 14), 344 PLL(CLK_APMIXED_ETH1PLL, "eth1pll", 0x0300, 0x0310, 0x00000001, 345 0, 21, 0x0300, 1, 0, 0x0304, 0), 346 PLL(CLK_APMIXED_ETH2PLL, "eth2pll", 0x0314, 0x0320, 0x00000001, 347 0, 21, 0x0314, 1, 0, 0x0318, 0), 348 PLL(CLK_APMIXED_SGMIPLL, "sgmipll", 0x0358, 0x0368, 0x00000001, 349 0, 21, 0x0358, 1, 0, 0x035C, 0), 350}; 351 352static const struct mtk_gate apmixed_clks[] = { 353 GATE_APMIXED(CLK_APMIXED_MAIN_CORE_EN, "main_core_en", "mainpll", 5), 354}; 355 356static const struct mtk_gate infra_clks[] = { 357 GATE_INFRA(CLK_INFRA_DBGCLK_PD, "infra_dbgclk_pd", "hd_faxi", 0), 358 GATE_INFRA(CLK_INFRA_TRNG_PD, "infra_trng_pd", "hd_faxi", 2), 359 GATE_INFRA(CLK_INFRA_DEVAPC_PD, "infra_devapc_pd", "hd_faxi", 4), 360 GATE_INFRA(CLK_INFRA_APXGPT_PD, "infra_apxgpt_pd", "infrao_10m", 18), 361 GATE_INFRA(CLK_INFRA_SEJ_PD, "infra_sej_pd", "infrao_10m", 19), 362}; 363 364static const struct mtk_fixed_clk top_fixed_clks[] = { 365 FIXED_CLK(CLK_TOP_TO_U2_PHY, "to_u2_phy", "clkxtal", 366 31250000), 367 FIXED_CLK(CLK_TOP_TO_U2_PHY_1P, "to_u2_phy_1p", "clkxtal", 368 31250000), 369 FIXED_CLK(CLK_TOP_PCIE0_PIPE_EN, "pcie0_pipe_en", "clkxtal", 370 125000000), 371 FIXED_CLK(CLK_TOP_PCIE1_PIPE_EN, "pcie1_pipe_en", "clkxtal", 372 125000000), 373 FIXED_CLK(CLK_TOP_SSUSB_TX250M, "ssusb_tx250m", "clkxtal", 374 250000000), 375 FIXED_CLK(CLK_TOP_SSUSB_EQ_RX250M, "ssusb_eq_rx250m", "clkxtal", 376 250000000), 377 FIXED_CLK(CLK_TOP_SSUSB_CDR_REF, "ssusb_cdr_ref", "clkxtal", 378 33333333), 379 FIXED_CLK(CLK_TOP_SSUSB_CDR_FB, "ssusb_cdr_fb", "clkxtal", 380 50000000), 381 FIXED_CLK(CLK_TOP_SATA_ASIC, "sata_asic", "clkxtal", 382 50000000), 383 FIXED_CLK(CLK_TOP_SATA_RBC, "sata_rbc", "clkxtal", 384 50000000), 385}; 386 387static const struct mtk_fixed_factor top_divs[] = { 388 FACTOR(CLK_TOP_TO_USB3_SYS, "to_usb3_sys", "eth1pll", 1, 4), 389 FACTOR(CLK_TOP_P1_1MHZ, "p1_1mhz", "eth1pll", 1, 500), 390 FACTOR(CLK_TOP_4MHZ, "free_run_4mhz", "eth1pll", 1, 125), 391 FACTOR(CLK_TOP_P0_1MHZ, "p0_1mhz", "eth1pll", 1, 500), 392 FACTOR(CLK_TOP_ETH_500M, "eth_500m", "eth1pll", 1, 1), 393 FACTOR(CLK_TOP_TXCLK_SRC_PRE, "txclk_src_pre", "sgmiipll_d2", 1, 1), 394 FACTOR(CLK_TOP_RTC, "rtc", "clkxtal", 1, 1024), 395 FACTOR(CLK_TOP_PWM_QTR_26M, "pwm_qtr_26m", "clkxtal", 1, 1), 396 FACTOR(CLK_TOP_CPUM_TCK_IN, "cpum_tck_in", "cpum_tck", 1, 1), 397 FACTOR(CLK_TOP_TO_USB3_DA_TOP, "to_usb3_da_top", "clkxtal", 1, 1), 398 FACTOR(CLK_TOP_MEMPLL, "mempll", "clkxtal", 32, 1), 399 FACTOR(CLK_TOP_DMPLL, "dmpll_ck", "mempll", 1, 1), 400 FACTOR(CLK_TOP_DMPLL_D4, "dmpll_d4", "mempll", 1, 4), 401 FACTOR(CLK_TOP_DMPLL_D8, "dmpll_d8", "mempll", 1, 8), 402 FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll", 1, 2), 403 FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "mainpll", 1, 4), 404 FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "mainpll", 1, 8), 405 FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "mainpll", 1, 16), 406 FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "mainpll", 1, 32), 407 FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "mainpll", 1, 6), 408 FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "mainpll", 1, 12), 409 FACTOR(CLK_TOP_SYSPLL2_D8, "syspll2_d8", "mainpll", 1, 24), 410 FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5), 411 FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "mainpll", 1, 10), 412 FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "mainpll", 1, 20), 413 FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll", 1, 7), 414 FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "mainpll", 1, 14), 415 FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "mainpll", 1, 28), 416 FACTOR(CLK_TOP_SYSPLL4_D16, "syspll4_d16", "mainpll", 1, 112), 417 FACTOR(CLK_TOP_UNIVPLL, "univpll", "univ2pll", 1, 2), 418 FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll", 1, 4), 419 FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll", 1, 8), 420 FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll", 1, 16), 421 FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3), 422 FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll", 1, 6), 423 FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll", 1, 12), 424 FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll", 1, 24), 425 FACTOR(CLK_TOP_UNIVPLL2_D16, "univpll2_d16", "univpll", 1, 48), 426 FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5), 427 FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll", 1, 10), 428 FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll", 1, 20), 429 FACTOR(CLK_TOP_UNIVPLL3_D16, "univpll3_d16", "univpll", 1, 80), 430 FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7), 431 FACTOR(CLK_TOP_UNIVPLL_D80_D4, "univpll_d80_d4", "univpll", 1, 320), 432 FACTOR(CLK_TOP_UNIV48M, "univ48m", "univpll", 1, 25), 433 FACTOR(CLK_TOP_SGMIIPLL_D2, "sgmiipll_d2", "sgmipll", 1, 2), 434 FACTOR(CLK_TOP_CLKXTAL_D4, "clkxtal_d4", "clkxtal", 1, 4), 435 FACTOR(CLK_TOP_HD_FAXI, "hd_faxi", "axi_sel", 1, 1), 436 FACTOR(CLK_TOP_FAXI, "faxi", "axi_sel", 1, 1), 437 FACTOR(CLK_TOP_F_FAUD_INTBUS, "f_faud_intbus", "aud_intbus_sel", 1, 1), 438 FACTOR(CLK_TOP_AP2WBHIF_HCLK, "ap2wbhif_hclk", "syspll1_d8", 1, 1), 439 FACTOR(CLK_TOP_10M_INFRAO, "infrao_10m", "gpt10m_sel", 1, 1), 440 FACTOR(CLK_TOP_MSDC30_1, "msdc30_1", "msdc30_1_sel", 1, 1), 441 FACTOR(CLK_TOP_SPI, "spi", "spi0_sel", 1, 1), 442 FACTOR(CLK_TOP_SF, "sf", "nfi_infra_sel", 1, 1), 443 FACTOR(CLK_TOP_FLASH, "flash", "flash_sel", 1, 1), 444 FACTOR(CLK_TOP_TO_USB3_REF, "to_usb3_ref", "sata_sel", 1, 4), 445 FACTOR(CLK_TOP_TO_USB3_MCU, "to_usb3_mcu", "axi_sel", 1, 1), 446 FACTOR(CLK_TOP_TO_USB3_DMA, "to_usb3_dma", "hif_sel", 1, 1), 447 FACTOR(CLK_TOP_FROM_TOP_AHB, "from_top_ahb", "axi_sel", 1, 1), 448 FACTOR(CLK_TOP_FROM_TOP_AXI, "from_top_axi", "hif_sel", 1, 1), 449 FACTOR(CLK_TOP_PCIE1_MAC_EN, "pcie1_mac_en", "sata_sel", 1, 1), 450 FACTOR(CLK_TOP_PCIE0_MAC_EN, "pcie0_mac_en", "sata_sel", 1, 1), 451}; 452 453static const struct mtk_gate peri_clks[] = { 454 /* PERI0 */ 455 GATE_PERI0(CLK_PERI_PWM1_PD, "peri_pwm1_pd", "pwm_qtr_26m", 2), 456 GATE_PERI0(CLK_PERI_PWM2_PD, "peri_pwm2_pd", "pwm_qtr_26m", 3), 457 GATE_PERI0(CLK_PERI_PWM3_PD, "peri_pwm3_pd", "pwm_qtr_26m", 4), 458 GATE_PERI0(CLK_PERI_PWM4_PD, "peri_pwm4_pd", "pwm_qtr_26m", 5), 459 GATE_PERI0(CLK_PERI_PWM5_PD, "peri_pwm5_pd", "pwm_qtr_26m", 6), 460 GATE_PERI0(CLK_PERI_PWM6_PD, "peri_pwm6_pd", "pwm_qtr_26m", 7), 461 GATE_PERI0(CLK_PERI_PWM7_PD, "peri_pwm7_pd", "pwm_qtr_26m", 8), 462 GATE_PERI0(CLK_PERI_PWM_PD, "peri_pwm_pd", "pwm_qtr_26m", 9), 463 GATE_PERI0(CLK_PERI_AP_DMA_PD, "peri_ap_dma_pd", "faxi", 12), 464 GATE_PERI0(CLK_PERI_MSDC30_1_PD, "peri_msdc30_1", "msdc30_1", 14), 465 GATE_PERI0(CLK_PERI_UART0_PD, "peri_uart0_pd", "faxi", 17), 466 GATE_PERI0(CLK_PERI_UART1_PD, "peri_uart1_pd", "faxi", 18), 467 GATE_PERI0(CLK_PERI_UART2_PD, "peri_uart2_pd", "faxi", 19), 468 GATE_PERI0(CLK_PERI_UART3_PD, "peri_uart3_pd", "faxi", 20), 469 GATE_PERI0(CLK_PERI_BTIF_PD, "peri_btif_pd", "faxi", 22), 470 GATE_PERI0(CLK_PERI_I2C0_PD, "peri_i2c0_pd", "faxi", 23), 471 GATE_PERI0(CLK_PERI_SPI0_PD, "peri_spi0_pd", "spi", 28), 472 GATE_PERI0(CLK_PERI_SNFI_PD, "peri_snfi_pd", "sf", 29), 473 GATE_PERI0(CLK_PERI_NFI_PD, "peri_nfi_pd", "faxi", 30), 474 GATE_PERI0(CLK_PERI_NFIECC_PD, "peri_nfiecc_pd", "faxi", 31), 475 /* PERI1 */ 476 GATE_PERI1(CLK_PERI_FLASH_PD, "peri_flash_pd", "flash", 1), 477}; 478 479static struct mtk_composite infra_muxes[] = { 480 /* INFRA_TOPCKGEN_CKMUXSEL */ 481 MUX(CLK_INFRA_MUX1_SEL, "infra_mux1_sel", infra_mux1_parents, 0x000, 482 2, 2), 483}; 484 485static struct mtk_composite top_muxes[] = { 486 /* CLK_CFG_0 */ 487 MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 488 0x040, 0, 3, 7), 489 MUX_GATE(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 490 0x040, 8, 1, 15), 491 MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents, 492 0x040, 16, 1, 23), 493 MUX_GATE(CLK_TOP_ETH_SEL, "eth_sel", eth_parents, 494 0x040, 24, 3, 31), 495 /* CLK_CFG_1 */ 496 MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 497 0x050, 0, 2, 7), 498 MUX_GATE(CLK_TOP_F10M_REF_SEL, "f10m_ref_sel", f10m_ref_parents, 499 0x050, 8, 1, 15), 500 MUX_GATE(CLK_TOP_NFI_INFRA_SEL, "nfi_infra_sel", nfi_infra_parents, 501 0x050, 16, 4, 23), 502 MUX_GATE(CLK_TOP_FLASH_SEL, "flash_sel", flash_parents, 503 0x050, 24, 3, 31), 504 /* CLK_CFG_2 */ 505 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 506 0x060, 0, 1, 7), 507 MUX_GATE(CLK_TOP_SPI0_SEL, "spi0_sel", spi0_parents, 508 0x060, 8, 3, 15), 509 MUX_GATE(CLK_TOP_SPI1_SEL, "spi1_sel", spi1_parents, 510 0x060, 16, 3, 23), 511 MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", uart_parents, 512 0x060, 24, 3, 31), 513 /* CLK_CFG_3 */ 514 MUX_GATE(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_0_parents, 515 0x070, 0, 3, 7), 516 MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_1_parents, 517 0x070, 8, 3, 15), 518 MUX_GATE(CLK_TOP_AP2WBMCU_SEL, "ap2wbmcu_sel", ap2wbmcu_parents, 519 0x070, 16, 3, 23), 520 MUX_GATE(CLK_TOP_AP2WBHIF_SEL, "ap2wbhif_sel", ap2wbmcu_parents, 521 0x070, 24, 3, 31), 522 /* CLK_CFG_4 */ 523 MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents, 524 0x080, 0, 2, 7), 525 MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents, 526 0x080, 8, 2, 15), 527 MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents, 528 0x080, 16, 3, 23), 529 MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", scp_parents, 530 0x080, 24, 2, 31), 531 /* CLK_CFG_5 */ 532 MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel", atb_parents, 533 0x090, 0, 2, 7), 534 MUX_GATE(CLK_TOP_HIF_SEL, "hif_sel", hif_parents, 535 0x090, 8, 3, 15), 536 MUX_GATE(CLK_TOP_SATA_SEL, "sata_sel", sata_parents, 537 0x090, 16, 1, 23), 538 MUX_GATE(CLK_TOP_U2_SEL, "usb20_sel", usb20_parents, 539 0x090, 24, 2, 31), 540 /* CLK_CFG_6 */ 541 MUX_GATE(CLK_TOP_AUD1_SEL, "aud1_sel", aud1_parents, 542 0x0A0, 0, 1, 7), 543 MUX_GATE(CLK_TOP_AUD2_SEL, "aud2_sel", aud1_parents, 544 0x0A0, 8, 1, 15), 545 MUX_GATE(CLK_TOP_IRRX_SEL, "irrx_sel", irrx_parents, 546 0x0A0, 16, 1, 23), 547 MUX_GATE(CLK_TOP_IRTX_SEL, "irtx_sel", irrx_parents, 548 0x0A0, 24, 1, 31), 549 /* CLK_CFG_7 */ 550 MUX_GATE(CLK_TOP_SATA_MCU_SEL, "sata_mcu_sel", scp_parents, 551 0x0B0, 0, 2, 7), 552 MUX_GATE(CLK_TOP_PCIE0_MCU_SEL, "pcie0_mcu_sel", scp_parents, 553 0x0B0, 8, 2, 15), 554 MUX_GATE(CLK_TOP_PCIE1_MCU_SEL, "pcie1_mcu_sel", scp_parents, 555 0x0B0, 16, 2, 23), 556 MUX_GATE(CLK_TOP_SSUSB_MCU_SEL, "ssusb_mcu_sel", scp_parents, 557 0x0B0, 24, 2, 31), 558 /* CLK_CFG_8 */ 559 MUX_GATE(CLK_TOP_CRYPTO_SEL, "crypto_sel", crypto_parents, 560 0x0C0, 0, 3, 7), 561 MUX_GATE(CLK_TOP_SGMII_REF_1_SEL, "sgmii_ref_1_sel", f10m_ref_parents, 562 0x0C0, 8, 1, 15), 563 MUX_GATE(CLK_TOP_10M_SEL, "gpt10m_sel", gpt10m_parents, 564 0x0C0, 16, 1, 23), 565}; 566 567static struct mtk_composite peri_muxes[] = { 568 /* PERI_GLOBALCON_CKSEL */ 569 MUX(CLK_PERIBUS_SEL, "peribus_ck_sel", peribus_ck_parents, 0x05C, 0, 1), 570}; 571 572static int mtk_topckgen_init(struct platform_device *pdev) 573{ 574 struct clk_onecell_data *clk_data; 575 void __iomem *base; 576 struct device_node *node = pdev->dev.of_node; 577 578 base = devm_platform_ioremap_resource(pdev, 0); 579 if (IS_ERR(base)) 580 return PTR_ERR(base); 581 582 clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK); 583 if (!clk_data) 584 return -ENOMEM; 585 586 mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), 587 clk_data); 588 589 mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), 590 clk_data); 591 592 mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), 593 base, &mt7629_clk_lock, clk_data); 594 595 clk_prepare_enable(clk_data->clks[CLK_TOP_AXI_SEL]); 596 clk_prepare_enable(clk_data->clks[CLK_TOP_MEM_SEL]); 597 clk_prepare_enable(clk_data->clks[CLK_TOP_DDRPHYCFG_SEL]); 598 599 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 600} 601 602static int mtk_infrasys_init(struct platform_device *pdev) 603{ 604 struct device_node *node = pdev->dev.of_node; 605 struct clk_onecell_data *clk_data; 606 607 clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK); 608 if (!clk_data) 609 return -ENOMEM; 610 611 mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), 612 clk_data); 613 614 mtk_clk_register_cpumuxes(node, infra_muxes, ARRAY_SIZE(infra_muxes), 615 clk_data); 616 617 return of_clk_add_provider(node, of_clk_src_onecell_get, 618 clk_data); 619} 620 621static int mtk_pericfg_init(struct platform_device *pdev) 622{ 623 struct clk_onecell_data *clk_data; 624 void __iomem *base; 625 int r; 626 struct device_node *node = pdev->dev.of_node; 627 628 base = devm_platform_ioremap_resource(pdev, 0); 629 if (IS_ERR(base)) 630 return PTR_ERR(base); 631 632 clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK); 633 if (!clk_data) 634 return -ENOMEM; 635 636 mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks), 637 clk_data); 638 639 mtk_clk_register_composites(peri_muxes, ARRAY_SIZE(peri_muxes), base, 640 &mt7629_clk_lock, clk_data); 641 642 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 643 if (r) 644 return r; 645 646 clk_prepare_enable(clk_data->clks[CLK_PERI_UART0_PD]); 647 648 return 0; 649} 650 651static int mtk_apmixedsys_init(struct platform_device *pdev) 652{ 653 struct clk_onecell_data *clk_data; 654 struct device_node *node = pdev->dev.of_node; 655 656 clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK); 657 if (!clk_data) 658 return -ENOMEM; 659 660 mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), 661 clk_data); 662 663 mtk_clk_register_gates(node, apmixed_clks, 664 ARRAY_SIZE(apmixed_clks), clk_data); 665 666 clk_prepare_enable(clk_data->clks[CLK_APMIXED_ARMPLL]); 667 clk_prepare_enable(clk_data->clks[CLK_APMIXED_MAIN_CORE_EN]); 668 669 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 670} 671 672 673static const struct of_device_id of_match_clk_mt7629[] = { 674 { 675 .compatible = "mediatek,mt7629-apmixedsys", 676 .data = mtk_apmixedsys_init, 677 }, { 678 .compatible = "mediatek,mt7629-infracfg", 679 .data = mtk_infrasys_init, 680 }, { 681 .compatible = "mediatek,mt7629-topckgen", 682 .data = mtk_topckgen_init, 683 }, { 684 .compatible = "mediatek,mt7629-pericfg", 685 .data = mtk_pericfg_init, 686 }, { 687 /* sentinel */ 688 } 689}; 690 691static int clk_mt7629_probe(struct platform_device *pdev) 692{ 693 int (*clk_init)(struct platform_device *); 694 int r; 695 696 clk_init = of_device_get_match_data(&pdev->dev); 697 if (!clk_init) 698 return -EINVAL; 699 700 r = clk_init(pdev); 701 if (r) 702 dev_err(&pdev->dev, 703 "could not register clock provider: %s: %d\n", 704 pdev->name, r); 705 706 return r; 707} 708 709static struct platform_driver clk_mt7629_drv = { 710 .probe = clk_mt7629_probe, 711 .driver = { 712 .name = "clk-mt7629", 713 .of_match_table = of_match_clk_mt7629, 714 }, 715}; 716 717static int clk_mt7629_init(void) 718{ 719 return platform_driver_register(&clk_mt7629_drv); 720} 721 722arch_initcall(clk_mt7629_init); 723