18c2ecf20Sopenharmony_ci// SPDX-License-Identifier: GPL-2.0
28c2ecf20Sopenharmony_ci/*
38c2ecf20Sopenharmony_ci * Copyright (C) 2018 MediaTek Inc.
48c2ecf20Sopenharmony_ci * Author: Wenzhen Yu <Wenzhen Yu@mediatek.com>
58c2ecf20Sopenharmony_ci *	   Ryder Lee <ryder.lee@mediatek.com>
68c2ecf20Sopenharmony_ci */
78c2ecf20Sopenharmony_ci
88c2ecf20Sopenharmony_ci#include <linux/clk-provider.h>
98c2ecf20Sopenharmony_ci#include <linux/of.h>
108c2ecf20Sopenharmony_ci#include <linux/of_address.h>
118c2ecf20Sopenharmony_ci#include <linux/of_device.h>
128c2ecf20Sopenharmony_ci#include <linux/platform_device.h>
138c2ecf20Sopenharmony_ci
148c2ecf20Sopenharmony_ci#include "clk-mtk.h"
158c2ecf20Sopenharmony_ci#include "clk-gate.h"
168c2ecf20Sopenharmony_ci
178c2ecf20Sopenharmony_ci#include <dt-bindings/clock/mt7629-clk.h>
188c2ecf20Sopenharmony_ci
198c2ecf20Sopenharmony_ci#define GATE_PCIE(_id, _name, _parent, _shift) {	\
208c2ecf20Sopenharmony_ci		.id = _id,				\
218c2ecf20Sopenharmony_ci		.name = _name,				\
228c2ecf20Sopenharmony_ci		.parent_name = _parent,			\
238c2ecf20Sopenharmony_ci		.regs = &pcie_cg_regs,			\
248c2ecf20Sopenharmony_ci		.shift = _shift,			\
258c2ecf20Sopenharmony_ci		.ops = &mtk_clk_gate_ops_no_setclr_inv,	\
268c2ecf20Sopenharmony_ci	}
278c2ecf20Sopenharmony_ci
288c2ecf20Sopenharmony_ci#define GATE_SSUSB(_id, _name, _parent, _shift) {	\
298c2ecf20Sopenharmony_ci		.id = _id,				\
308c2ecf20Sopenharmony_ci		.name = _name,				\
318c2ecf20Sopenharmony_ci		.parent_name = _parent,			\
328c2ecf20Sopenharmony_ci		.regs = &ssusb_cg_regs,			\
338c2ecf20Sopenharmony_ci		.shift = _shift,			\
348c2ecf20Sopenharmony_ci		.ops = &mtk_clk_gate_ops_no_setclr_inv,	\
358c2ecf20Sopenharmony_ci	}
368c2ecf20Sopenharmony_ci
378c2ecf20Sopenharmony_cistatic const struct mtk_gate_regs pcie_cg_regs = {
388c2ecf20Sopenharmony_ci	.set_ofs = 0x30,
398c2ecf20Sopenharmony_ci	.clr_ofs = 0x30,
408c2ecf20Sopenharmony_ci	.sta_ofs = 0x30,
418c2ecf20Sopenharmony_ci};
428c2ecf20Sopenharmony_ci
438c2ecf20Sopenharmony_cistatic const struct mtk_gate_regs ssusb_cg_regs = {
448c2ecf20Sopenharmony_ci	.set_ofs = 0x30,
458c2ecf20Sopenharmony_ci	.clr_ofs = 0x30,
468c2ecf20Sopenharmony_ci	.sta_ofs = 0x30,
478c2ecf20Sopenharmony_ci};
488c2ecf20Sopenharmony_ci
498c2ecf20Sopenharmony_cistatic const struct mtk_gate ssusb_clks[] = {
508c2ecf20Sopenharmony_ci	GATE_SSUSB(CLK_SSUSB_U2_PHY_1P_EN, "ssusb_u2_phy_1p",
518c2ecf20Sopenharmony_ci		   "to_u2_phy_1p", 0),
528c2ecf20Sopenharmony_ci	GATE_SSUSB(CLK_SSUSB_U2_PHY_EN, "ssusb_u2_phy_en", "to_u2_phy", 1),
538c2ecf20Sopenharmony_ci	GATE_SSUSB(CLK_SSUSB_REF_EN, "ssusb_ref_en", "to_usb3_ref", 5),
548c2ecf20Sopenharmony_ci	GATE_SSUSB(CLK_SSUSB_SYS_EN, "ssusb_sys_en", "to_usb3_sys", 6),
558c2ecf20Sopenharmony_ci	GATE_SSUSB(CLK_SSUSB_MCU_EN, "ssusb_mcu_en", "to_usb3_mcu", 7),
568c2ecf20Sopenharmony_ci	GATE_SSUSB(CLK_SSUSB_DMA_EN, "ssusb_dma_en", "to_usb3_dma", 8),
578c2ecf20Sopenharmony_ci};
588c2ecf20Sopenharmony_ci
598c2ecf20Sopenharmony_cistatic const struct mtk_gate pcie_clks[] = {
608c2ecf20Sopenharmony_ci	GATE_PCIE(CLK_PCIE_P1_AUX_EN, "pcie_p1_aux_en", "p1_1mhz", 12),
618c2ecf20Sopenharmony_ci	GATE_PCIE(CLK_PCIE_P1_OBFF_EN, "pcie_p1_obff_en", "free_run_4mhz", 13),
628c2ecf20Sopenharmony_ci	GATE_PCIE(CLK_PCIE_P1_AHB_EN, "pcie_p1_ahb_en", "from_top_ahb", 14),
638c2ecf20Sopenharmony_ci	GATE_PCIE(CLK_PCIE_P1_AXI_EN, "pcie_p1_axi_en", "from_top_axi", 15),
648c2ecf20Sopenharmony_ci	GATE_PCIE(CLK_PCIE_P1_MAC_EN, "pcie_p1_mac_en", "pcie1_mac_en", 16),
658c2ecf20Sopenharmony_ci	GATE_PCIE(CLK_PCIE_P1_PIPE_EN, "pcie_p1_pipe_en", "pcie1_pipe_en", 17),
668c2ecf20Sopenharmony_ci	GATE_PCIE(CLK_PCIE_P0_AUX_EN, "pcie_p0_aux_en", "p0_1mhz", 18),
678c2ecf20Sopenharmony_ci	GATE_PCIE(CLK_PCIE_P0_OBFF_EN, "pcie_p0_obff_en", "free_run_4mhz", 19),
688c2ecf20Sopenharmony_ci	GATE_PCIE(CLK_PCIE_P0_AHB_EN, "pcie_p0_ahb_en", "from_top_ahb", 20),
698c2ecf20Sopenharmony_ci	GATE_PCIE(CLK_PCIE_P0_AXI_EN, "pcie_p0_axi_en", "from_top_axi", 21),
708c2ecf20Sopenharmony_ci	GATE_PCIE(CLK_PCIE_P0_MAC_EN, "pcie_p0_mac_en", "pcie0_mac_en", 22),
718c2ecf20Sopenharmony_ci	GATE_PCIE(CLK_PCIE_P0_PIPE_EN, "pcie_p0_pipe_en", "pcie0_pipe_en", 23),
728c2ecf20Sopenharmony_ci};
738c2ecf20Sopenharmony_ci
748c2ecf20Sopenharmony_cistatic int clk_mt7629_ssusbsys_init(struct platform_device *pdev)
758c2ecf20Sopenharmony_ci{
768c2ecf20Sopenharmony_ci	struct clk_onecell_data *clk_data;
778c2ecf20Sopenharmony_ci	struct device_node *node = pdev->dev.of_node;
788c2ecf20Sopenharmony_ci	int r;
798c2ecf20Sopenharmony_ci
808c2ecf20Sopenharmony_ci	clk_data = mtk_alloc_clk_data(CLK_SSUSB_NR_CLK);
818c2ecf20Sopenharmony_ci
828c2ecf20Sopenharmony_ci	mtk_clk_register_gates(node, ssusb_clks, ARRAY_SIZE(ssusb_clks),
838c2ecf20Sopenharmony_ci			       clk_data);
848c2ecf20Sopenharmony_ci
858c2ecf20Sopenharmony_ci	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
868c2ecf20Sopenharmony_ci	if (r)
878c2ecf20Sopenharmony_ci		dev_err(&pdev->dev,
888c2ecf20Sopenharmony_ci			"could not register clock provider: %s: %d\n",
898c2ecf20Sopenharmony_ci			pdev->name, r);
908c2ecf20Sopenharmony_ci
918c2ecf20Sopenharmony_ci	mtk_register_reset_controller(node, 1, 0x34);
928c2ecf20Sopenharmony_ci
938c2ecf20Sopenharmony_ci	return r;
948c2ecf20Sopenharmony_ci}
958c2ecf20Sopenharmony_ci
968c2ecf20Sopenharmony_cistatic int clk_mt7629_pciesys_init(struct platform_device *pdev)
978c2ecf20Sopenharmony_ci{
988c2ecf20Sopenharmony_ci	struct clk_onecell_data *clk_data;
998c2ecf20Sopenharmony_ci	struct device_node *node = pdev->dev.of_node;
1008c2ecf20Sopenharmony_ci	int r;
1018c2ecf20Sopenharmony_ci
1028c2ecf20Sopenharmony_ci	clk_data = mtk_alloc_clk_data(CLK_PCIE_NR_CLK);
1038c2ecf20Sopenharmony_ci
1048c2ecf20Sopenharmony_ci	mtk_clk_register_gates(node, pcie_clks, ARRAY_SIZE(pcie_clks),
1058c2ecf20Sopenharmony_ci			       clk_data);
1068c2ecf20Sopenharmony_ci
1078c2ecf20Sopenharmony_ci	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1088c2ecf20Sopenharmony_ci	if (r)
1098c2ecf20Sopenharmony_ci		dev_err(&pdev->dev,
1108c2ecf20Sopenharmony_ci			"could not register clock provider: %s: %d\n",
1118c2ecf20Sopenharmony_ci			pdev->name, r);
1128c2ecf20Sopenharmony_ci
1138c2ecf20Sopenharmony_ci	mtk_register_reset_controller(node, 1, 0x34);
1148c2ecf20Sopenharmony_ci
1158c2ecf20Sopenharmony_ci	return r;
1168c2ecf20Sopenharmony_ci}
1178c2ecf20Sopenharmony_ci
1188c2ecf20Sopenharmony_cistatic const struct of_device_id of_match_clk_mt7629_hif[] = {
1198c2ecf20Sopenharmony_ci	{
1208c2ecf20Sopenharmony_ci		.compatible = "mediatek,mt7629-pciesys",
1218c2ecf20Sopenharmony_ci		.data = clk_mt7629_pciesys_init,
1228c2ecf20Sopenharmony_ci	}, {
1238c2ecf20Sopenharmony_ci		.compatible = "mediatek,mt7629-ssusbsys",
1248c2ecf20Sopenharmony_ci		.data = clk_mt7629_ssusbsys_init,
1258c2ecf20Sopenharmony_ci	}, {
1268c2ecf20Sopenharmony_ci		/* sentinel */
1278c2ecf20Sopenharmony_ci	}
1288c2ecf20Sopenharmony_ci};
1298c2ecf20Sopenharmony_ci
1308c2ecf20Sopenharmony_cistatic int clk_mt7629_hif_probe(struct platform_device *pdev)
1318c2ecf20Sopenharmony_ci{
1328c2ecf20Sopenharmony_ci	int (*clk_init)(struct platform_device *);
1338c2ecf20Sopenharmony_ci	int r;
1348c2ecf20Sopenharmony_ci
1358c2ecf20Sopenharmony_ci	clk_init = of_device_get_match_data(&pdev->dev);
1368c2ecf20Sopenharmony_ci	if (!clk_init)
1378c2ecf20Sopenharmony_ci		return -EINVAL;
1388c2ecf20Sopenharmony_ci
1398c2ecf20Sopenharmony_ci	r = clk_init(pdev);
1408c2ecf20Sopenharmony_ci	if (r)
1418c2ecf20Sopenharmony_ci		dev_err(&pdev->dev,
1428c2ecf20Sopenharmony_ci			"could not register clock provider: %s: %d\n",
1438c2ecf20Sopenharmony_ci			pdev->name, r);
1448c2ecf20Sopenharmony_ci
1458c2ecf20Sopenharmony_ci	return r;
1468c2ecf20Sopenharmony_ci}
1478c2ecf20Sopenharmony_ci
1488c2ecf20Sopenharmony_cistatic struct platform_driver clk_mt7629_hif_drv = {
1498c2ecf20Sopenharmony_ci	.probe = clk_mt7629_hif_probe,
1508c2ecf20Sopenharmony_ci	.driver = {
1518c2ecf20Sopenharmony_ci		.name = "clk-mt7629-hif",
1528c2ecf20Sopenharmony_ci		.of_match_table = of_match_clk_mt7629_hif,
1538c2ecf20Sopenharmony_ci	},
1548c2ecf20Sopenharmony_ci};
1558c2ecf20Sopenharmony_ci
1568c2ecf20Sopenharmony_cibuiltin_platform_driver(clk_mt7629_hif_drv);
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