1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2017 MediaTek Inc.
4 * Author: Kevin Chen <kevin-cw.chen@mediatek.com>
5 */
6
7#include <linux/clk-provider.h>
8#include <linux/platform_device.h>
9#include <dt-bindings/clock/mt6797-clk.h>
10
11#include "clk-mtk.h"
12#include "clk-gate.h"
13
14static const struct mtk_gate_regs mm0_cg_regs = {
15	.set_ofs = 0x0104,
16	.clr_ofs = 0x0108,
17	.sta_ofs = 0x0100,
18};
19
20static const struct mtk_gate_regs mm1_cg_regs = {
21	.set_ofs = 0x0114,
22	.clr_ofs = 0x0118,
23	.sta_ofs = 0x0110,
24};
25
26#define GATE_MM0(_id, _name, _parent, _shift) {			\
27	.id = _id,					\
28	.name = _name,					\
29	.parent_name = _parent,				\
30	.regs = &mm0_cg_regs,				\
31	.shift = _shift,				\
32	.ops = &mtk_clk_gate_ops_setclr,		\
33}
34
35#define GATE_MM1(_id, _name, _parent, _shift) {			\
36	.id = _id,					\
37	.name = _name,					\
38	.parent_name = _parent,				\
39	.regs = &mm1_cg_regs,				\
40	.shift = _shift,				\
41	.ops = &mtk_clk_gate_ops_setclr,		\
42}
43
44static const struct mtk_gate mm_clks[] = {
45	GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "mm_sel", 0),
46	GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1),
47	GATE_MM0(CLK_MM_SMI_LARB5, "mm_smi_larb5", "mm_sel", 2),
48	GATE_MM0(CLK_MM_CAM_MDP, "mm_cam_mdp", "mm_sel", 3),
49	GATE_MM0(CLK_MM_MDP_RDMA0, "mm_mdp_rdma0", "mm_sel", 4),
50	GATE_MM0(CLK_MM_MDP_RDMA1, "mm_mdp_rdma1", "mm_sel", 5),
51	GATE_MM0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_sel", 6),
52	GATE_MM0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 7),
53	GATE_MM0(CLK_MM_MDP_RSZ2, "mm_mdp_rsz2", "mm_sel", 8),
54	GATE_MM0(CLK_MM_MDP_TDSHP, "mm_mdp_tdshp", "mm_sel", 9),
55	GATE_MM0(CLK_MM_MDP_COLOR, "mm_mdp_color", "mm_sel", 10),
56	GATE_MM0(CLK_MM_MDP_WDMA, "mm_mdp_wdma", "mm_sel", 11),
57	GATE_MM0(CLK_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_sel", 12),
58	GATE_MM0(CLK_MM_MDP_WROT1, "mm_mdp_wrot1", "mm_sel", 13),
59	GATE_MM0(CLK_MM_FAKE_ENG, "mm_fake_eng", "mm_sel", 14),
60	GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "mm_sel", 15),
61	GATE_MM0(CLK_MM_DISP_OVL1, "mm_disp_ovl1", "mm_sel", 16),
62	GATE_MM0(CLK_MM_DISP_OVL0_2L, "mm_disp_ovl0_2l", "mm_sel", 17),
63	GATE_MM0(CLK_MM_DISP_OVL1_2L, "mm_disp_ovl1_2l", "mm_sel", 18),
64	GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_sel", 19),
65	GATE_MM0(CLK_MM_DISP_RDMA1, "mm_disp_rdma1", "mm_sel", 20),
66	GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_sel", 21),
67	GATE_MM0(CLK_MM_DISP_WDMA1, "mm_disp_wdma1", "mm_sel", 22),
68	GATE_MM0(CLK_MM_DISP_COLOR, "mm_disp_color", "mm_sel", 23),
69	GATE_MM0(CLK_MM_DISP_CCORR, "mm_disp_ccorr", "mm_sel", 24),
70	GATE_MM0(CLK_MM_DISP_AAL, "mm_disp_aal", "mm_sel", 25),
71	GATE_MM0(CLK_MM_DISP_GAMMA, "mm_disp_gamma", "mm_sel", 26),
72	GATE_MM0(CLK_MM_DISP_OD, "mm_disp_od", "mm_sel", 27),
73	GATE_MM0(CLK_MM_DISP_DITHER, "mm_disp_dither", "mm_sel", 28),
74	GATE_MM0(CLK_MM_DISP_UFOE, "mm_disp_ufoe", "mm_sel", 29),
75	GATE_MM0(CLK_MM_DISP_DSC, "mm_disp_dsc", "mm_sel", 30),
76	GATE_MM0(CLK_MM_DISP_SPLIT, "mm_disp_split", "mm_sel", 31),
77	GATE_MM1(CLK_MM_DSI0_MM_CLOCK, "mm_dsi0_mm_clock", "mm_sel", 0),
78	GATE_MM1(CLK_MM_DSI1_MM_CLOCK, "mm_dsi1_mm_clock", "mm_sel", 2),
79	GATE_MM1(CLK_MM_DPI_MM_CLOCK, "mm_dpi_mm_clock", "mm_sel", 4),
80	GATE_MM1(CLK_MM_DPI_INTERFACE_CLOCK, "mm_dpi_interface_clock",
81		 "dpi0_sel", 5),
82	GATE_MM1(CLK_MM_LARB4_AXI_ASIF_MM_CLOCK, "mm_larb4_axi_asif_mm_clock",
83		 "mm_sel", 6),
84	GATE_MM1(CLK_MM_LARB4_AXI_ASIF_MJC_CLOCK, "mm_larb4_axi_asif_mjc_clock",
85		 "mjc_sel", 7),
86	GATE_MM1(CLK_MM_DISP_OVL0_MOUT_CLOCK, "mm_disp_ovl0_mout_clock",
87		 "mm_sel", 8),
88	GATE_MM1(CLK_MM_FAKE_ENG2, "mm_fake_eng2", "mm_sel", 9),
89	GATE_MM1(CLK_MM_DSI0_INTERFACE_CLOCK, "mm_dsi0_interface_clock",
90		 "clk26m", 1),
91	GATE_MM1(CLK_MM_DSI1_INTERFACE_CLOCK, "mm_dsi1_interface_clock",
92		 "clk26m", 3),
93};
94
95static int clk_mt6797_mm_probe(struct platform_device *pdev)
96{
97	struct device *dev = &pdev->dev;
98	struct device_node *node = dev->parent->of_node;
99	struct clk_onecell_data *clk_data;
100	int r;
101
102	clk_data = mtk_alloc_clk_data(CLK_MM_NR);
103
104	mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks),
105			       clk_data);
106
107	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
108	if (r)
109		dev_err(&pdev->dev,
110			"could not register clock provider: %s: %d\n",
111			pdev->name, r);
112
113	return r;
114}
115
116static struct platform_driver clk_mt6797_mm_drv = {
117	.probe = clk_mt6797_mm_probe,
118	.driver = {
119		.name = "clk-mt6797-mm",
120	},
121};
122
123builtin_platform_driver(clk_mt6797_mm_drv);
124